Lines Matching +full:qcm2290 +full:- +full:bimc
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
17 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 clock-frequency = <32764>;
37 #clock-cells = <0>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a53";
50 capacity-dmips-mhz = <1024>;
51 dynamic-power-coefficient = <100>;
52 enable-method = "psci";
53 next-level-cache = <&l2_0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
55 power-domains = <&cpu_pd0>;
56 power-domain-names = "psci";
57 l2_0: l2-cache {
59 cache-level = <2>;
60 cache-unified;
66 compatible = "arm,cortex-a53";
69 capacity-dmips-mhz = <1024>;
70 dynamic-power-coefficient = <100>;
71 enable-method = "psci";
72 next-level-cache = <&l2_0>;
73 qcom,freq-domain = <&cpufreq_hw 0>;
74 power-domains = <&cpu_pd1>;
75 power-domain-names = "psci";
80 compatible = "arm,cortex-a53";
83 capacity-dmips-mhz = <1024>;
84 dynamic-power-coefficient = <100>;
85 enable-method = "psci";
86 next-level-cache = <&l2_0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 power-domains = <&cpu_pd2>;
89 power-domain-names = "psci";
94 compatible = "arm,cortex-a53";
97 capacity-dmips-mhz = <1024>;
98 dynamic-power-coefficient = <100>;
99 enable-method = "psci";
100 next-level-cache = <&l2_0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 power-domains = <&cpu_pd3>;
103 power-domain-names = "psci";
106 cpu-map {
126 domain-idle-states {
127 cluster_sleep: cluster-sleep-0 {
128 compatible = "domain-idle-state";
129 arm,psci-suspend-param = <0x41000043>;
130 entry-latency-us = <800>;
131 exit-latency-us = <2118>;
132 min-residency-us = <7376>;
136 idle-states {
137 entry-method = "psci";
139 cpu_sleep: cpu-sleep-0 {
140 compatible = "arm,idle-state";
141 idle-state-name = "power-collapse";
142 arm,psci-suspend-param = <0x40000003>;
143 entry-latency-us = <290>;
144 exit-latency-us = <376>;
145 min-residency-us = <1182>;
146 local-timer-stop;
153 compatible = "qcom,scm-qcm2290", "qcom,scm";
155 clock-names = "core";
156 #reset-cells = <1>;
158 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
169 compatible = "arm,cortex-a53-pmu";
174 compatible = "arm,psci-1.0";
177 cpu_pd0: power-domain-cpu0 {
178 #power-domain-cells = <0>;
179 power-domains = <&cluster_pd>;
180 domain-idle-states = <&cpu_sleep>;
183 cpu_pd1: power-domain-cpu1 {
184 #power-domain-cells = <0>;
185 power-domains = <&cluster_pd>;
186 domain-idle-states = <&cpu_sleep>;
189 cpu_pd2: power-domain-cpu2 {
190 #power-domain-cells = <0>;
191 power-domains = <&cluster_pd>;
192 domain-idle-states = <&cpu_sleep>;
195 cpu_pd3: power-domain-cpu3 {
196 #power-domain-cells = <0>;
197 power-domains = <&cluster_pd>;
198 domain-idle-states = <&cpu_sleep>;
201 cluster_pd: power-domain-cpu-cluster {
202 #power-domain-cells = <0>;
203 power-domains = <&mpm>;
204 domain-idle-states = <&cluster_sleep>;
209 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
211 glink-edge {
212 compatible = "qcom,glink-rpm";
214 qcom,rpm-msg-ram = <&rpm_msg_ram>;
217 rpm_requests: rpm-requests {
218 compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm";
219 qcom,glink-channels = "rpm_requests";
221 rpmcc: clock-controller {
222 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
224 clock-names = "xo";
225 #clock-cells = <1>;
228 rpmpd: power-controller {
229 compatible = "qcom,qcm2290-rpmpd";
230 #power-domain-cells = <1>;
231 operating-points-v2 = <&rpmpd_opp_table>;
233 rpmpd_opp_table: opp-table {
234 compatible = "operating-points-v2";
237 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
241 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
245 opp-level = <RPM_SMD_LEVEL_SVS>;
249 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
253 opp-level = <RPM_SMD_LEVEL_NOM>;
257 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
261 opp-level = <RPM_SMD_LEVEL_TURBO>;
265 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
272 mpm: interrupt-controller {
274 qcom,rpm-msg-ram = <&apss_mpm>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
279 #power-domain-cells = <0>;
280 interrupt-parent = <&intc>;
281 qcom,mpm-pin-count = <96>;
282 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
291 reserved_memory: reserved-memory {
292 #address-cells = <2>;
293 #size-cells = <2>;
298 no-map;
301 xbl_aop_mem: xbl-aop@45e00000 {
303 no-map;
306 sec_apps_mem: sec-apps@45fff000 {
308 no-map;
314 no-map;
317 qcom,rpm-msg-ram = <&rpm_msg_ram>;
322 no-map;
327 no-map;
330 wlan_msa_mem: wlan-msa@51900000 {
332 no-map;
337 no-map;
340 pil_ipa_fw_mem: ipa-fw@53600000 {
342 no-map;
345 pil_ipa_gsi_mem: ipa-gsi@53610000 {
347 no-map;
351 compatible = "shared-dma-pool";
353 no-map;
358 no-map;
361 dfps_data_memory: dpfs-data@5cf00000 {
363 no-map;
368 no-map;
372 compatible = "qcom,rmtfs-mem";
374 no-map;
376 qcom,client-id = <1>;
381 smp2p-adsp {
389 qcom,local-pid = <0>;
390 qcom,remote-pid = <2>;
392 adsp_smp2p_out: master-kernel {
393 qcom,entry-name = "master-kernel";
394 #qcom,smem-state-cells = <1>;
397 adsp_smp2p_in: slave-kernel {
398 qcom,entry-name = "slave-kernel";
399 interrupt-controller;
400 #interrupt-cells = <2>;
404 smp2p-mpss {
412 qcom,local-pid = <0>;
413 qcom,remote-pid = <1>;
415 modem_smp2p_out: master-kernel {
416 qcom,entry-name = "master-kernel";
417 #qcom,smem-state-cells = <1>;
420 modem_smp2p_in: slave-kernel {
421 qcom,entry-name = "slave-kernel";
422 interrupt-controller;
423 #interrupt-cells = <2>;
426 wlan_smp2p_in: wlan-wpss-to-ap {
427 qcom,entry-name = "wlan";
428 interrupt-controller;
429 #interrupt-cells = <2>;
434 compatible = "simple-bus";
435 #address-cells = <2>;
436 #size-cells = <2>;
438 dma-ranges = <0 0 0 0 0x10 0>;
441 compatible = "qcom,tcsr-mutex";
443 #hwlock-cells = <1>;
447 compatible = "qcom,qcm2290-tcsr", "syscon";
452 compatible = "qcom,qcm2290-tlmm";
455 gpio-controller;
456 gpio-ranges = <&tlmm 0 0 127>;
457 wakeup-parent = <&mpm>;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
462 qup_i2c0_default: qup-i2c0-default-state {
465 drive-strength = <2>;
466 bias-pull-up;
469 qup_i2c1_default: qup-i2c1-default-state {
472 drive-strength = <2>;
473 bias-pull-up;
476 qup_i2c2_default: qup-i2c2-default-state {
479 drive-strength = <2>;
480 bias-pull-up;
483 qup_i2c3_default: qup-i2c3-default-state {
486 drive-strength = <2>;
487 bias-pull-up;
490 qup_i2c4_default: qup-i2c4-default-state {
493 drive-strength = <2>;
494 bias-pull-up;
497 qup_i2c5_default: qup-i2c5-default-state {
500 drive-strength = <2>;
501 bias-pull-up;
504 qup_spi0_default: qup-spi0-default-state {
507 drive-strength = <2>;
508 bias-pull-up;
511 qup_spi1_default: qup-spi1-default-state {
514 drive-strength = <2>;
515 bias-pull-up;
518 qup_spi2_default: qup-spi2-default-state {
521 drive-strength = <2>;
522 bias-pull-up;
525 qup_spi3_default: qup-spi3-default-state {
528 drive-strength = <2>;
529 bias-pull-up;
532 qup_spi4_default: qup-spi4-default-state {
535 drive-strength = <2>;
536 bias-pull-up;
539 qup_spi5_default: qup-spi5-default-state {
542 drive-strength = <2>;
543 bias-pull-up;
546 qup_uart0_default: qup-uart0-default-state {
549 drive-strength = <2>;
550 bias-disable;
553 qup_uart4_default: qup-uart4-default-state {
556 drive-strength = <2>;
557 bias-disable;
560 sdc1_state_on: sdc1-on-state {
561 clk-pins {
563 drive-strength = <16>;
564 bias-disable;
567 cmd-pins {
569 drive-strength = <10>;
570 bias-pull-up;
573 data-pins {
575 drive-strength = <10>;
576 bias-pull-up;
579 rclk-pins {
581 bias-pull-down;
585 sdc1_state_off: sdc1-off-state {
586 clk-pins {
588 drive-strength = <2>;
589 bias-disable;
592 cmd-pins {
594 drive-strength = <2>;
595 bias-pull-up;
598 data-pins {
600 drive-strength = <2>;
601 bias-pull-up;
604 rclk-pins {
606 bias-pull-down;
610 sdc2_state_on: sdc2-on-state {
611 clk-pins {
613 drive-strength = <16>;
614 bias-disable;
617 cmd-pins {
619 drive-strength = <10>;
620 bias-pull-up;
623 data-pins {
625 drive-strength = <10>;
626 bias-pull-up;
630 sdc2_state_off: sdc2-off-state {
631 clk-pins {
633 drive-strength = <2>;
634 bias-disable;
637 cmd-pins {
639 drive-strength = <2>;
640 bias-pull-up;
643 data-pins {
645 drive-strength = <2>;
646 bias-pull-up;
651 gcc: clock-controller@1400000 {
652 compatible = "qcom,gcc-qcm2290";
655 clock-names = "bi_tcxo", "sleep_clk";
656 #clock-cells = <1>;
657 #reset-cells = <1>;
658 #power-domain-cells = <1>;
662 compatible = "qcom,qcm2290-qusb2-phy";
667 clock-names = "cfg_ahb", "ref";
670 nvmem-cells = <&qusb2_hstx_trim>;
671 #phy-cells = <0>;
677 compatible = "qcom,qcm2290-qmp-usb3-phy";
684 clock-names = "cfg_ahb",
691 reset-names = "phy",
694 #clock-cells = <0>;
695 clock-output-names = "usb3_phy_pipe_clk_src";
697 #phy-cells = <0>;
698 orientation-switch;
700 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
705 #address-cells = <1>;
706 #size-cells = <0>;
719 remote-endpoint = <&usb_dwc3_ss>;
726 compatible = "qcom,qcm2290-snoc";
728 #interconnect-cells = <2>;
730 qup_virt: interconnect-qup {
731 compatible = "qcom,qcm2290-qup-virt";
732 #interconnect-cells = <2>;
735 mmnrt_virt: interconnect-mmnrt {
736 compatible = "qcom,qcm2290-mmnrt-virt";
737 #interconnect-cells = <2>;
740 mmrt_virt: interconnect-mmrt {
741 compatible = "qcom,qcm2290-mmrt-virt";
742 #interconnect-cells = <2>;
747 compatible = "qcom,qcm2290-cnoc";
749 #interconnect-cells = <2>;
753 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
755 #address-cells = <1>;
756 #size-cells = <1>;
758 qusb2_hstx_trim: hstx-trim@25b {
763 gpu_speed_bin: gpu-speed-bin@2006 {
770 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon";
774 operating-points-v2 = <&cpu_bwmon_opp_table>;
775 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
776 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>;
778 cpu_bwmon_opp_table: opp-table {
779 compatible = "operating-points-v2";
781 opp-0 {
782 opp-peak-kBps = <(200 * 4 * 1000)>;
785 opp-1 {
786 opp-peak-kBps = <(300 * 4 * 1000)>;
789 opp-2 {
790 opp-peak-kBps = <(451 * 4 * 1000)>;
793 opp-3 {
794 opp-peak-kBps = <(547 * 4 * 1000)>;
797 opp-4 {
798 opp-peak-kBps = <(681 * 4 * 1000)>;
801 opp-5 {
802 opp-peak-kBps = <(768 * 4 * 1000)>;
805 opp-6 {
806 opp-peak-kBps = <(1017 * 4 * 1000)>;
809 opp-7 {
810 opp-peak-kBps = <(1353 * 4 * 1000)>;
813 opp-8 {
814 opp-peak-kBps = <(1555 * 4 * 1000)>;
817 opp-9 {
818 opp-peak-kBps = <(1804 * 4 * 1000)>;
824 compatible = "qcom,spmi-pmic-arb";
830 reg-names = "core",
835 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "periph_irq";
839 #address-cells = <2>;
840 #size-cells = <0>;
841 interrupt-controller;
842 #interrupt-cells = <4>;
845 tsens0: thermal-sensor@4411000 {
846 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
850 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
852 interrupt-names = "uplow", "critical";
853 #thermal-sensor-cells = <1>;
857 compatible = "qcom,prng-ee";
860 clock-names = "core";
863 bimc: interconnect@4480000 { label
864 compatible = "qcom,qcm2290-bimc";
866 #interconnect-cells = <2>;
870 compatible = "qcom,rpm-msg-ram", "mmio-sram";
872 #address-cells = <1>;
873 #size-cells = <1>;
882 compatible = "qcom,rpm-stats";
887 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
891 reg-names = "hc",
897 interrupt-names = "hc_irq", "pwr_irq";
903 clock-names = "iface",
910 power-domains = <&rpmpd QCM2290_VDDCX>;
911 operating-points-v2 = <&sdhc1_opp_table>;
914 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
915 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
917 interconnect-names = "sdhc-ddr",
918 "cpu-sdhc";
920 qcom,dll-config = <0x000f642c>;
921 qcom,ddr-config = <0x80040868>;
922 bus-width = <8>;
926 sdhc1_opp_table: opp-table {
927 compatible = "operating-points-v2";
929 opp-100000000 {
930 opp-hz = /bits/ 64 <100000000>;
931 required-opps = <&rpmpd_opp_low_svs>;
932 opp-peak-kBps = <250000 133320>;
933 opp-avg-kBps = <102400 65000>;
936 opp-192000000 {
937 opp-hz = /bits/ 64 <192000000>;
938 required-opps = <&rpmpd_opp_low_svs>;
939 opp-peak-kBps = <800000 300000>;
940 opp-avg-kBps = <204800 200000>;
943 opp-384000000 {
944 opp-hz = /bits/ 64 <384000000>;
945 required-opps = <&rpmpd_opp_svs_plus>;
946 opp-peak-kBps = <800000 300000>;
947 opp-avg-kBps = <204800 200000>;
953 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
955 reg-names = "hc";
959 interrupt-names = "hc_irq", "pwr_irq";
964 clock-names = "iface",
970 power-domains = <&rpmpd QCM2290_VDDCX>;
971 operating-points-v2 = <&sdhc2_opp_table>;
974 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
975 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
977 interconnect-names = "sdhc-ddr",
978 "cpu-sdhc";
980 qcom,dll-config = <0x0007642c>;
981 qcom,ddr-config = <0x80040868>;
982 bus-width = <4>;
986 sdhc2_opp_table: opp-table {
987 compatible = "operating-points-v2";
989 opp-100000000 {
990 opp-hz = /bits/ 64 <100000000>;
991 required-opps = <&rpmpd_opp_low_svs>;
992 opp-peak-kBps = <250000 133320>;
993 opp-avg-kBps = <261438 150000>;
996 opp-202000000 {
997 opp-hz = /bits/ 64 <202000000>;
998 required-opps = <&rpmpd_opp_svs_plus>;
999 opp-peak-kBps = <800000 300000>;
1000 opp-avg-kBps = <261438 300000>;
1005 gpi_dma0: dma-controller@4a00000 {
1006 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
1018 dma-channels = <10>;
1019 dma-channel-mask = <0x1f>;
1021 #dma-cells = <3>;
1026 compatible = "qcom,geni-se-qup";
1030 clock-names = "m-ahb", "s-ahb";
1032 #address-cells = <2>;
1033 #size-cells = <2>;
1038 compatible = "qcom,geni-i2c";
1042 clock-names = "se";
1043 pinctrl-0 = <&qup_i2c0_default>;
1044 pinctrl-names = "default";
1047 dma-names = "tx", "rx";
1050 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1053 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1054 interconnect-names = "qup-core",
1055 "qup-config",
1056 "qup-memory";
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1063 compatible = "qcom,geni-spi";
1067 clock-names = "se";
1068 pinctrl-0 = <&qup_spi0_default>;
1069 pinctrl-names = "default";
1072 dma-names = "tx", "rx";
1075 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1077 interconnect-names = "qup-core",
1078 "qup-config";
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1085 compatible = "qcom,geni-uart";
1089 clock-names = "se";
1090 pinctrl-0 = <&qup_uart0_default>;
1091 pinctrl-names = "default";
1094 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1096 interconnect-names = "qup-core",
1097 "qup-config";
1102 compatible = "qcom,geni-i2c";
1106 clock-names = "se";
1107 pinctrl-0 = <&qup_i2c1_default>;
1108 pinctrl-names = "default";
1111 dma-names = "tx", "rx";
1114 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1117 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1118 interconnect-names = "qup-core",
1119 "qup-config",
1120 "qup-memory";
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1127 compatible = "qcom,geni-spi";
1131 clock-names = "se";
1132 pinctrl-0 = <&qup_spi1_default>;
1133 pinctrl-names = "default";
1136 dma-names = "tx", "rx";
1139 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1141 interconnect-names = "qup-core",
1142 "qup-config";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1149 compatible = "qcom,geni-i2c";
1153 clock-names = "se";
1154 pinctrl-0 = <&qup_i2c2_default>;
1155 pinctrl-names = "default";
1158 dma-names = "tx", "rx";
1161 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1164 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1165 interconnect-names = "qup-core",
1166 "qup-config",
1167 "qup-memory";
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1174 compatible = "qcom,geni-spi";
1178 clock-names = "se";
1179 pinctrl-0 = <&qup_spi2_default>;
1180 pinctrl-names = "default";
1183 dma-names = "tx", "rx";
1186 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1188 interconnect-names = "qup-core",
1189 "qup-config";
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1196 compatible = "qcom,geni-i2c";
1200 clock-names = "se";
1201 pinctrl-0 = <&qup_i2c3_default>;
1202 pinctrl-names = "default";
1205 dma-names = "tx", "rx";
1208 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1211 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1212 interconnect-names = "qup-core",
1213 "qup-config",
1214 "qup-memory";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "qcom,geni-spi";
1225 clock-names = "se";
1226 pinctrl-0 = <&qup_spi3_default>;
1227 pinctrl-names = "default";
1230 dma-names = "tx", "rx";
1233 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1235 interconnect-names = "qup-core",
1236 "qup-config";
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1243 compatible = "qcom,geni-i2c";
1247 clock-names = "se";
1248 pinctrl-0 = <&qup_i2c4_default>;
1249 pinctrl-names = "default";
1252 dma-names = "tx", "rx";
1255 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1258 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1259 interconnect-names = "qup-core",
1260 "qup-config",
1261 "qup-memory";
1262 #address-cells = <1>;
1263 #size-cells = <0>;
1268 compatible = "qcom,geni-spi";
1271 clock-names = "se";
1273 pinctrl-names = "default";
1274 pinctrl-0 = <&qup_spi4_default>;
1277 dma-names = "tx", "rx";
1280 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1282 interconnect-names = "qup-core",
1283 "qup-config";
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1290 compatible = "qcom,geni-uart";
1294 clock-names = "se";
1295 pinctrl-0 = <&qup_uart4_default>;
1296 pinctrl-names = "default";
1299 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1301 interconnect-names = "qup-core",
1302 "qup-config";
1307 compatible = "qcom,geni-i2c";
1311 clock-names = "se";
1312 pinctrl-0 = <&qup_i2c5_default>;
1313 pinctrl-names = "default";
1316 dma-names = "tx", "rx";
1319 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1322 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1323 interconnect-names = "qup-core",
1324 "qup-config",
1325 "qup-memory";
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1332 compatible = "qcom,geni-spi";
1336 clock-names = "se";
1337 pinctrl-0 = <&qup_spi5_default>;
1338 pinctrl-names = "default";
1341 dma-names = "tx", "rx";
1344 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1346 interconnect-names = "qup-core",
1347 "qup-config";
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1355 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1357 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1359 interrupt-names = "hs_phy_irq",
1368 clock-names = "cfg_noc",
1375 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1377 assigned-clock-rates = <19200000>, <133333333>;
1380 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1381 /* TODO: USB<->IPA path */
1383 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
1384 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1386 interconnect-names = "usb-ddr",
1387 "apps-usb";
1388 wakeup-source;
1390 #address-cells = <2>;
1391 #size-cells = <2>;
1401 phy-names = "usb2-phy", "usb3-phy";
1405 snps,has-lpm-erratum;
1406 snps,hird-threshold = /bits/ 8 <0x10>;
1408 maximum-speed = "super-speed";
1410 usb-role-switch;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1427 remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1435 compatible = "qcom,adreno-07000200", "qcom,adreno";
1437 reg-names = "kgsl_3d0_reg_memory";
1447 clock-names = "core",
1454 interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG
1455 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1456 interconnect-names = "gfx-mem";
1460 operating-points-v2 = <&gpu_opp_table>;
1461 power-domains = <&rpmpd QCM2290_VDDCX>;
1464 nvmem-cells = <&gpu_speed_bin>;
1465 nvmem-cell-names = "speed_bin";
1466 #cooling-cells = <2>;
1470 zap-shader {
1471 memory-region = <&pil_gpu_mem>;
1474 gpu_opp_table: opp-table {
1475 compatible = "operating-points-v2";
1478 opp-1123200000 {
1479 opp-hz = /bits/ 64 <1123200000>;
1480 required-opps = <&rpmpd_opp_turbo_plus>;
1481 opp-peak-kBps = <6881000>;
1482 opp-supported-hw = <0x3>;
1483 turbo-mode;
1486 opp-1017600000 {
1487 opp-hz = /bits/ 64 <1017600000>;
1488 required-opps = <&rpmpd_opp_turbo>;
1489 opp-peak-kBps = <6881000>;
1490 opp-supported-hw = <0x3>;
1491 turbo-mode;
1494 opp-921600000 {
1495 opp-hz = /bits/ 64 <921600000>;
1496 required-opps = <&rpmpd_opp_nom_plus>;
1497 opp-peak-kBps = <6881000>;
1498 opp-supported-hw = <0x3>;
1501 opp-844800000 {
1502 opp-hz = /bits/ 64 <844800000>;
1503 required-opps = <&rpmpd_opp_nom>;
1504 opp-peak-kBps = <6881000>;
1505 opp-supported-hw = <0x7>;
1508 opp-672000000 {
1509 opp-hz = /bits/ 64 <672000000>;
1510 required-opps = <&rpmpd_opp_svs_plus>;
1511 opp-peak-kBps = <3879000>;
1512 opp-supported-hw = <0xf>;
1515 opp-537600000 {
1516 opp-hz = /bits/ 64 <537600000>;
1517 required-opps = <&rpmpd_opp_svs>;
1518 opp-peak-kBps = <2929000>;
1519 opp-supported-hw = <0xf>;
1522 opp-355200000 {
1523 opp-hz = /bits/ 64 <355200000>;
1524 required-opps = <&rpmpd_opp_low_svs>;
1525 opp-peak-kBps = <1720000>;
1526 opp-supported-hw = <0xf>;
1532 compatible = "qcom,adreno-gmu-wrapper";
1534 reg-names = "gmu";
1535 power-domains = <&gpucc GPU_CX_GDSC>,
1537 power-domain-names = "cx",
1541 gpucc: clock-controller@5990000 {
1542 compatible = "qcom,qcm2290-gpucc";
1548 power-domains = <&rpmpd QCM2290_VDDCX>;
1549 required-opps = <&rpmpd_opp_low_svs>;
1550 #clock-cells = <1>;
1551 #reset-cells = <1>;
1552 #power-domain-cells = <1>;
1556 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu",
1557 "qcom,smmu-500", "arm,mmu-500";
1572 clock-names = "mem",
1576 power-domains = <&gpucc GPU_CX_GDSC>;
1578 #global-interrupts = <1>;
1579 #iommu-cells = <2>;
1582 mdss: display-subsystem@5e00000 {
1583 compatible = "qcom,qcm2290-mdss";
1585 reg-names = "mdss";
1587 interrupt-controller;
1588 #interrupt-cells = <1>;
1593 clock-names = "iface",
1599 power-domains = <&dispcc MDSS_GDSC>;
1604 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
1605 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1607 interconnect-names = "mdp0-mem",
1608 "cpu-cfg";
1610 #address-cells = <2>;
1611 #size-cells = <2>;
1616 mdp: display-controller@5e01000 {
1617 compatible = "qcom,qcm2290-dpu";
1620 reg-names = "mdp",
1623 interrupt-parent = <&mdss>;
1631 clock-names = "bus",
1637 operating-points-v2 = <&mdp_opp_table>;
1638 power-domains = <&rpmpd QCM2290_VDDCX>;
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1647 remote-endpoint = <&mdss_dsi0_in>;
1652 mdp_opp_table: opp-table {
1653 compatible = "operating-points-v2";
1655 opp-19200000 {
1656 opp-hz = /bits/ 64 <19200000>;
1657 required-opps = <&rpmpd_opp_min_svs>;
1660 opp-192000000 {
1661 opp-hz = /bits/ 64 <192000000>;
1662 required-opps = <&rpmpd_opp_low_svs>;
1665 opp-256000000 {
1666 opp-hz = /bits/ 64 <256000000>;
1667 required-opps = <&rpmpd_opp_svs>;
1670 opp-307200000 {
1671 opp-hz = /bits/ 64 <307200000>;
1672 required-opps = <&rpmpd_opp_svs_plus>;
1675 opp-384000000 {
1676 opp-hz = /bits/ 64 <384000000>;
1677 required-opps = <&rpmpd_opp_nom>;
1683 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1685 reg-names = "dsi_ctrl";
1687 interrupt-parent = <&mdss>;
1696 clock-names = "byte",
1703 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1705 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1708 operating-points-v2 = <&dsi_opp_table>;
1709 power-domains = <&rpmpd QCM2290_VDDCX>;
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1717 dsi_opp_table: opp-table {
1718 compatible = "operating-points-v2";
1720 opp-19200000 {
1721 opp-hz = /bits/ 64 <19200000>;
1722 required-opps = <&rpmpd_opp_min_svs>;
1725 opp-164000000 {
1726 opp-hz = /bits/ 64 <164000000>;
1727 required-opps = <&rpmpd_opp_low_svs>;
1730 opp-187500000 {
1731 opp-hz = /bits/ 64 <187500000>;
1732 required-opps = <&rpmpd_opp_svs>;
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1744 remote-endpoint = <&dpu_intf1_out>;
1758 compatible = "qcom,dsi-phy-14nm-2290";
1762 reg-names = "dsi_phy",
1768 clock-names = "iface",
1771 power-domains = <&rpmpd QCM2290_VDDMX>;
1772 required-opps = <&rpmpd_opp_nom>;
1774 #clock-cells = <1>;
1775 #phy-cells = <0>;
1781 dispcc: clock-controller@5f00000 {
1782 compatible = "qcom,qcm2290-dispcc";
1790 clock-names = "bi_tcxo",
1796 #power-domain-cells = <1>;
1797 #clock-cells = <1>;
1798 #reset-cells = <1>;
1802 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1805 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1811 interrupt-names = "wdog",
1815 "stop-ack",
1816 "shutdown-ack";
1819 clock-names = "xo";
1821 power-domains = <&rpmpd QCM2290_VDDCX>;
1823 memory-region = <&pil_modem_mem>;
1825 qcom,smem-states = <&modem_smp2p_out 0>;
1826 qcom,smem-state-names = "stop";
1830 glink-edge {
1833 qcom,remote-pid = <1>;
1839 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1842 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1847 interrupt-names = "wdog",
1851 "stop-ack";
1854 clock-names = "xo";
1856 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
1859 memory-region = <&pil_adsp_mem>;
1861 qcom,smem-states = <&adsp_smp2p_out 0>;
1862 qcom,smem-state-names = "stop";
1866 glink-edge {
1869 qcom,remote-pid = <2>;
1875 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1877 #iommu-cells = <2>;
1878 #global-interrupts = <1>;
1948 compatible = "qcom,wcn3990-wifi";
1950 reg-names = "membase";
1951 memory-region = <&wlan_msa_mem>;
1965 qcom,msa-fixed-perm;
1970 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
1978 compatible = "qcom,qcm2290-apcs-hmss-global";
1980 #mbox-cells = <1>;
1984 compatible = "arm,armv7-timer-mem";
1986 #address-cells = <1>;
1987 #size-cells = <1>;
1995 frame-number = <0>;
2001 frame-number = <1>;
2008 frame-number = <2>;
2015 frame-number = <3>;
2022 frame-number = <4>;
2029 frame-number = <5>;
2036 frame-number = <6>;
2041 intc: interrupt-controller@f200000 {
2042 compatible = "arm,gic-v3";
2046 #interrupt-cells = <3>;
2047 interrupt-controller;
2048 interrupt-parent = <&intc>;
2049 #redistributor-regions = <1>;
2050 redistributor-stride = <0x0 0x20000>;
2054 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
2056 reg-names = "freq-domain0";
2057 interrupts-extended = <&lmh_cluster 0>;
2058 interrupt-names = "dcvsh-irq-0";
2060 clock-names = "xo", "alternate";
2062 #freq-domain-cells = <1>;
2063 #clock-cells = <1>;
2067 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh";
2071 qcom,lmh-temp-arm-millicelsius = <65000>;
2072 qcom,lmh-temp-low-millicelsius = <94500>;
2073 qcom,lmh-temp-high-millicelsius = <95000>;
2074 interrupt-controller;
2075 #interrupt-cells = <1>;
2079 thermal-zones {
2080 mapss-thermal {
2081 thermal-sensors = <&tsens0 0>;
2084 mapss_alert0: trip-point0 {
2090 mapss_alert1: trip-point1 {
2096 mapss_crit: mapss-crit {
2104 video-thermal {
2105 thermal-sensors = <&tsens0 1>;
2108 video_alert0: trip-point0 {
2114 video_alert1: trip-point1 {
2120 video_crit: video-crit {
2128 wlan-thermal {
2129 thermal-sensors = <&tsens0 2>;
2132 wlan_alert0: trip-point0 {
2138 wlan_alert1: trip-point1 {
2144 wlan_crit: wlan-crit {
2152 cpuss0-thermal {
2153 thermal-sensors = <&tsens0 3>;
2156 cpuss0_alert0: trip-point0 {
2162 cpuss0_alert1: trip-point1 {
2168 cpuss0_crit: cpuss0-crit {
2176 cpuss1-thermal {
2177 thermal-sensors = <&tsens0 4>;
2180 cpuss1_alert0: trip-point0 {
2186 cpuss1_alert1: trip-point1 {
2192 cpuss1_crit: cpuss1-crit {
2200 mdm0-thermal {
2201 thermal-sensors = <&tsens0 5>;
2204 mdm0_alert0: trip-point0 {
2210 mdm0_alert1: trip-point1 {
2216 mdm0_crit: mdm0-crit {
2224 mdm1-thermal {
2225 thermal-sensors = <&tsens0 6>;
2228 mdm1_alert0: trip-point0 {
2234 mdm1_alert1: trip-point1 {
2240 mdm1_crit: mdm1-crit {
2248 gpu-thermal {
2249 thermal-sensors = <&tsens0 7>;
2252 gpu_alert0: trip-point0 {
2258 gpu_alert1: trip-point1 {
2264 gpu_crit: gpu-crit {
2272 hm-center-thermal {
2273 thermal-sensors = <&tsens0 8>;
2276 hm_center_alert0: trip-point0 {
2282 hm_center_alert1: trip-point1 {
2288 hm_center_crit: hm-center-crit {
2296 camera-thermal {
2297 thermal-sensors = <&tsens0 9>;
2300 camera_alert0: trip-point0 {
2306 camera_alert1: trip-point1 {
2312 camera_crit: camera-crit {
2322 compatible = "arm,armv8-timer";