Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
11 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
12 #include <dt-bindings/clock/qcom,rpmcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interconnect/qcom,qcm2290.h>
18 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
22 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
30 xo_board: xo-board {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 clock-frequency = <32764>;
38 #clock-cells = <0>;
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a53";
51 capacity-dmips-mhz = <1024>;
52 dynamic-power-coefficient = <100>;
53 enable-method = "psci";
54 next-level-cache = <&l2_0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
56 power-domains = <&cpu_pd0>;
57 power-domain-names = "psci";
58 l2_0: l2-cache {
60 cache-level = <2>;
61 cache-unified;
67 compatible = "arm,cortex-a53";
70 capacity-dmips-mhz = <1024>;
71 dynamic-power-coefficient = <100>;
72 enable-method = "psci";
73 next-level-cache = <&l2_0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
75 power-domains = <&cpu_pd1>;
76 power-domain-names = "psci";
81 compatible = "arm,cortex-a53";
84 capacity-dmips-mhz = <1024>;
85 dynamic-power-coefficient = <100>;
86 enable-method = "psci";
87 next-level-cache = <&l2_0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
89 power-domains = <&cpu_pd2>;
90 power-domain-names = "psci";
95 compatible = "arm,cortex-a53";
98 capacity-dmips-mhz = <1024>;
99 dynamic-power-coefficient = <100>;
100 enable-method = "psci";
101 next-level-cache = <&l2_0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 power-domains = <&cpu_pd3>;
104 power-domain-names = "psci";
107 cpu-map {
127 domain-idle-states {
128 cluster_sleep: cluster-sleep-0 {
129 compatible = "domain-idle-state";
130 arm,psci-suspend-param = <0x41000043>;
131 entry-latency-us = <800>;
132 exit-latency-us = <2118>;
133 min-residency-us = <7376>;
137 idle-states {
138 entry-method = "psci";
140 cpu_sleep: cpu-sleep-0 {
141 compatible = "arm,idle-state";
142 idle-state-name = "power-collapse";
143 arm,psci-suspend-param = <0x40000003>;
144 entry-latency-us = <290>;
145 exit-latency-us = <376>;
146 min-residency-us = <1182>;
147 local-timer-stop;
154 compatible = "qcom,scm-qcm2290", "qcom,scm";
156 clock-names = "core";
157 #reset-cells = <1>;
170 compatible = "arm,cortex-a53-pmu";
174 psci {
175 compatible = "arm,psci-1.0";
178 cpu_pd0: power-domain-cpu0 {
179 #power-domain-cells = <0>;
180 power-domains = <&cluster_pd>;
181 domain-idle-states = <&cpu_sleep>;
184 cpu_pd1: power-domain-cpu1 {
185 #power-domain-cells = <0>;
186 power-domains = <&cluster_pd>;
187 domain-idle-states = <&cpu_sleep>;
190 cpu_pd2: power-domain-cpu2 {
191 #power-domain-cells = <0>;
192 power-domains = <&cluster_pd>;
193 domain-idle-states = <&cpu_sleep>;
196 cpu_pd3: power-domain-cpu3 {
197 #power-domain-cells = <0>;
198 power-domains = <&cluster_pd>;
199 domain-idle-states = <&cpu_sleep>;
202 cluster_pd: power-domain-cpu-cluster {
203 #power-domain-cells = <0>;
204 power-domains = <&mpm>;
205 domain-idle-states = <&cluster_sleep>;
210 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
212 glink-edge {
213 compatible = "qcom,glink-rpm";
215 qcom,rpm-msg-ram = <&rpm_msg_ram>;
218 rpm_requests: rpm-requests {
219 compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm";
220 qcom,glink-channels = "rpm_requests";
222 rpmcc: clock-controller {
223 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
225 clock-names = "xo";
226 #clock-cells = <1>;
229 rpmpd: power-controller {
230 compatible = "qcom,qcm2290-rpmpd";
231 #power-domain-cells = <1>;
232 operating-points-v2 = <&rpmpd_opp_table>;
234 rpmpd_opp_table: opp-table {
235 compatible = "operating-points-v2";
238 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
242 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
246 opp-level = <RPM_SMD_LEVEL_SVS>;
250 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
254 opp-level = <RPM_SMD_LEVEL_NOM>;
258 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
262 opp-level = <RPM_SMD_LEVEL_TURBO>;
266 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
273 mpm: interrupt-controller {
275 qcom,rpm-msg-ram = <&apss_mpm>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
280 #power-domain-cells = <0>;
281 interrupt-parent = <&intc>;
282 qcom,mpm-pin-count = <96>;
283 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
292 reserved_memory: reserved-memory {
293 #address-cells = <2>;
294 #size-cells = <2>;
299 no-map;
302 xbl_aop_mem: xbl-aop@45e00000 {
304 no-map;
307 sec_apps_mem: sec-apps@45fff000 {
309 no-map;
315 no-map;
318 qcom,rpm-msg-ram = <&rpm_msg_ram>;
323 no-map;
328 no-map;
331 wlan_msa_mem: wlan-msa@51900000 {
333 no-map;
338 no-map;
341 pil_ipa_fw_mem: ipa-fw@53600000 {
343 no-map;
346 pil_ipa_gsi_mem: ipa-gsi@53610000 {
348 no-map;
352 compatible = "shared-dma-pool";
354 no-map;
359 no-map;
362 dfps_data_memory: dpfs-data@5cf00000 {
364 no-map;
369 no-map;
373 compatible = "qcom,rmtfs-mem";
375 no-map;
377 qcom,client-id = <1>;
382 smp2p-adsp {
390 qcom,local-pid = <0>;
391 qcom,remote-pid = <2>;
393 adsp_smp2p_out: master-kernel {
394 qcom,entry-name = "master-kernel";
395 #qcom,smem-state-cells = <1>;
398 adsp_smp2p_in: slave-kernel {
399 qcom,entry-name = "slave-kernel";
400 interrupt-controller;
401 #interrupt-cells = <2>;
405 smp2p-mpss {
413 qcom,local-pid = <0>;
414 qcom,remote-pid = <1>;
416 modem_smp2p_out: master-kernel {
417 qcom,entry-name = "master-kernel";
418 #qcom,smem-state-cells = <1>;
421 modem_smp2p_in: slave-kernel {
422 qcom,entry-name = "slave-kernel";
423 interrupt-controller;
424 #interrupt-cells = <2>;
427 wlan_smp2p_in: wlan-wpss-to-ap {
428 qcom,entry-name = "wlan";
429 interrupt-controller;
430 #interrupt-cells = <2>;
435 compatible = "simple-bus";
436 #address-cells = <2>;
437 #size-cells = <2>;
439 dma-ranges = <0 0 0 0 0x10 0>;
442 compatible = "qcom,tcsr-mutex";
444 #hwlock-cells = <1>;
448 compatible = "qcom,qcm2290-tcsr", "syscon";
453 compatible = "qcom,qcm2290-tlmm";
456 gpio-controller;
457 gpio-ranges = <&tlmm 0 0 127>;
458 wakeup-parent = <&mpm>;
459 #gpio-cells = <2>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
463 qup_i2c0_default: qup-i2c0-default-state {
466 drive-strength = <2>;
467 bias-pull-up;
470 qup_i2c1_default: qup-i2c1-default-state {
473 drive-strength = <2>;
474 bias-pull-up;
477 qup_i2c2_default: qup-i2c2-default-state {
480 drive-strength = <2>;
481 bias-pull-up;
484 qup_i2c3_default: qup-i2c3-default-state {
487 drive-strength = <2>;
488 bias-pull-up;
491 qup_i2c4_default: qup-i2c4-default-state {
494 drive-strength = <2>;
495 bias-pull-up;
498 qup_i2c5_default: qup-i2c5-default-state {
501 drive-strength = <2>;
502 bias-pull-up;
505 qup_spi0_default: qup-spi0-default-state {
508 drive-strength = <2>;
509 bias-pull-up;
512 qup_spi1_default: qup-spi1-default-state {
515 drive-strength = <2>;
516 bias-pull-up;
519 qup_spi2_default: qup-spi2-default-state {
522 drive-strength = <2>;
523 bias-pull-up;
526 qup_spi3_default: qup-spi3-default-state {
529 drive-strength = <2>;
530 bias-pull-up;
533 qup_spi4_default: qup-spi4-default-state {
536 drive-strength = <2>;
537 bias-pull-up;
540 qup_spi5_default: qup-spi5-default-state {
543 drive-strength = <2>;
544 bias-pull-up;
547 qup_uart0_default: qup-uart0-default-state {
550 drive-strength = <2>;
551 bias-disable;
554 qup_uart3_default: qup-uart3-default-state {
557 drive-strength = <2>;
558 bias-disable;
561 qup_uart4_default: qup-uart4-default-state {
564 drive-strength = <2>;
565 bias-disable;
568 sdc1_state_on: sdc1-on-state {
569 clk-pins {
571 drive-strength = <16>;
572 bias-disable;
575 cmd-pins {
577 drive-strength = <10>;
578 bias-pull-up;
581 data-pins {
583 drive-strength = <10>;
584 bias-pull-up;
587 rclk-pins {
589 bias-pull-down;
593 sdc1_state_off: sdc1-off-state {
594 clk-pins {
596 drive-strength = <2>;
597 bias-disable;
600 cmd-pins {
602 drive-strength = <2>;
603 bias-pull-up;
606 data-pins {
608 drive-strength = <2>;
609 bias-pull-up;
612 rclk-pins {
614 bias-pull-down;
618 sdc2_state_on: sdc2-on-state {
619 clk-pins {
621 drive-strength = <16>;
622 bias-disable;
625 cmd-pins {
627 drive-strength = <10>;
628 bias-pull-up;
631 data-pins {
633 drive-strength = <10>;
634 bias-pull-up;
638 sdc2_state_off: sdc2-off-state {
639 clk-pins {
641 drive-strength = <2>;
642 bias-disable;
645 cmd-pins {
647 drive-strength = <2>;
648 bias-pull-up;
651 data-pins {
653 drive-strength = <2>;
654 bias-pull-up;
659 gcc: clock-controller@1400000 {
660 compatible = "qcom,gcc-qcm2290";
663 clock-names = "bi_tcxo", "sleep_clk";
664 #clock-cells = <1>;
665 #reset-cells = <1>;
666 #power-domain-cells = <1>;
670 compatible = "qcom,qcm2290-qusb2-phy";
675 clock-names = "cfg_ahb", "ref";
678 nvmem-cells = <&qusb2_hstx_trim>;
679 #phy-cells = <0>;
685 compatible = "qcom,qcm2290-qmp-usb3-phy";
692 clock-names = "cfg_ahb",
699 reset-names = "phy",
702 #clock-cells = <0>;
703 clock-output-names = "usb3_phy_pipe_clk_src";
705 #phy-cells = <0>;
706 orientation-switch;
708 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
713 #address-cells = <1>;
714 #size-cells = <0>;
727 remote-endpoint = <&usb_dwc3_ss>;
734 compatible = "qcom,qcm2290-snoc";
736 #interconnect-cells = <2>;
738 qup_virt: interconnect-qup {
739 compatible = "qcom,qcm2290-qup-virt";
740 #interconnect-cells = <2>;
743 mmnrt_virt: interconnect-mmnrt {
744 compatible = "qcom,qcm2290-mmnrt-virt";
745 #interconnect-cells = <2>;
748 mmrt_virt: interconnect-mmrt {
749 compatible = "qcom,qcm2290-mmrt-virt";
750 #interconnect-cells = <2>;
755 compatible = "qcom,qcm2290-cnoc";
757 #interconnect-cells = <2>;
760 cryptobam: dma-controller@1b04000 {
761 compatible = "qcom,bam-v1.7.0";
765 clock-names = "bam_clk";
766 #dma-cells = <1>;
768 qcom,controlled-remotely;
774 compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce";
777 clock-names = "core";
779 dma-names = "rx", "tx";
785 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
787 #address-cells = <1>;
788 #size-cells = <1>;
790 qusb2_hstx_trim: hstx-trim@25b {
795 gpu_speed_bin: gpu-speed-bin@2006 {
802 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon";
806 operating-points-v2 = <&cpu_bwmon_opp_table>;
810 cpu_bwmon_opp_table: opp-table {
811 compatible = "operating-points-v2";
813 opp-0 {
814 opp-peak-kBps = <(200 * 4 * 1000)>;
817 opp-1 {
818 opp-peak-kBps = <(300 * 4 * 1000)>;
821 opp-2 {
822 opp-peak-kBps = <(451 * 4 * 1000)>;
825 opp-3 {
826 opp-peak-kBps = <(547 * 4 * 1000)>;
829 opp-4 {
830 opp-peak-kBps = <(681 * 4 * 1000)>;
833 opp-5 {
834 opp-peak-kBps = <(768 * 4 * 1000)>;
837 opp-6 {
838 opp-peak-kBps = <(1017 * 4 * 1000)>;
841 opp-7 {
842 opp-peak-kBps = <(1353 * 4 * 1000)>;
845 opp-8 {
846 opp-peak-kBps = <(1555 * 4 * 1000)>;
849 opp-9 {
850 opp-peak-kBps = <(1804 * 4 * 1000)>;
856 compatible = "qcom,spmi-pmic-arb";
862 reg-names = "core",
867 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "periph_irq";
871 #address-cells = <2>;
872 #size-cells = <0>;
873 interrupt-controller;
874 #interrupt-cells = <4>;
877 tsens0: thermal-sensor@4411000 {
878 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
882 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
884 interrupt-names = "uplow", "critical";
885 #thermal-sensor-cells = <1>;
889 compatible = "qcom,prng-ee";
892 clock-names = "core";
896 compatible = "qcom,qcm2290-bimc";
898 #interconnect-cells = <2>;
902 compatible = "qcom,rpm-msg-ram", "mmio-sram";
904 #address-cells = <1>;
905 #size-cells = <1>;
914 compatible = "qcom,rpm-stats";
919 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
923 reg-names = "hc",
929 interrupt-names = "hc_irq", "pwr_irq";
935 clock-names = "iface",
942 power-domains = <&rpmpd QCM2290_VDDCX>;
943 operating-points-v2 = <&sdhc1_opp_table>;
949 interconnect-names = "sdhc-ddr",
950 "cpu-sdhc";
952 qcom,dll-config = <0x000f642c>;
953 qcom,ddr-config = <0x80040868>;
954 bus-width = <8>;
958 sdhc1_opp_table: opp-table {
959 compatible = "operating-points-v2";
961 opp-100000000 {
962 opp-hz = /bits/ 64 <100000000>;
963 required-opps = <&rpmpd_opp_low_svs>;
964 opp-peak-kBps = <250000 133320>;
965 opp-avg-kBps = <102400 65000>;
968 opp-192000000 {
969 opp-hz = /bits/ 64 <192000000>;
970 required-opps = <&rpmpd_opp_low_svs>;
971 opp-peak-kBps = <800000 300000>;
972 opp-avg-kBps = <204800 200000>;
975 opp-384000000 {
976 opp-hz = /bits/ 64 <384000000>;
977 required-opps = <&rpmpd_opp_svs_plus>;
978 opp-peak-kBps = <800000 300000>;
979 opp-avg-kBps = <204800 200000>;
985 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
987 reg-names = "hc";
991 interrupt-names = "hc_irq", "pwr_irq";
996 clock-names = "iface",
1002 power-domains = <&rpmpd QCM2290_VDDCX>;
1003 operating-points-v2 = <&sdhc2_opp_table>;
1009 interconnect-names = "sdhc-ddr",
1010 "cpu-sdhc";
1012 qcom,dll-config = <0x0007642c>;
1013 qcom,ddr-config = <0x80040868>;
1014 bus-width = <4>;
1018 sdhc2_opp_table: opp-table {
1019 compatible = "operating-points-v2";
1021 opp-100000000 {
1022 opp-hz = /bits/ 64 <100000000>;
1023 required-opps = <&rpmpd_opp_low_svs>;
1024 opp-peak-kBps = <250000 133320>;
1025 opp-avg-kBps = <261438 150000>;
1028 opp-202000000 {
1029 opp-hz = /bits/ 64 <202000000>;
1030 required-opps = <&rpmpd_opp_svs_plus>;
1031 opp-peak-kBps = <800000 300000>;
1032 opp-avg-kBps = <261438 300000>;
1037 gpi_dma0: dma-controller@4a00000 {
1038 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
1050 dma-channels = <10>;
1051 dma-channel-mask = <0x1f>;
1053 #dma-cells = <3>;
1058 compatible = "qcom,geni-se-qup";
1062 clock-names = "m-ahb", "s-ahb";
1064 #address-cells = <2>;
1065 #size-cells = <2>;
1070 compatible = "qcom,geni-i2c";
1074 clock-names = "se";
1075 pinctrl-0 = <&qup_i2c0_default>;
1076 pinctrl-names = "default";
1079 dma-names = "tx", "rx";
1086 interconnect-names = "qup-core",
1087 "qup-config",
1088 "qup-memory";
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1095 compatible = "qcom,geni-spi";
1099 clock-names = "se";
1100 pinctrl-0 = <&qup_spi0_default>;
1101 pinctrl-names = "default";
1104 dma-names = "tx", "rx";
1109 interconnect-names = "qup-core",
1110 "qup-config";
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1117 compatible = "qcom,geni-uart";
1121 clock-names = "se";
1122 pinctrl-0 = <&qup_uart0_default>;
1123 pinctrl-names = "default";
1128 interconnect-names = "qup-core",
1129 "qup-config";
1134 compatible = "qcom,geni-i2c";
1138 clock-names = "se";
1139 pinctrl-0 = <&qup_i2c1_default>;
1140 pinctrl-names = "default";
1143 dma-names = "tx", "rx";
1150 interconnect-names = "qup-core",
1151 "qup-config",
1152 "qup-memory";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1159 compatible = "qcom,geni-spi";
1163 clock-names = "se";
1164 pinctrl-0 = <&qup_spi1_default>;
1165 pinctrl-names = "default";
1168 dma-names = "tx", "rx";
1173 interconnect-names = "qup-core",
1174 "qup-config";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "qcom,geni-i2c";
1185 clock-names = "se";
1186 pinctrl-0 = <&qup_i2c2_default>;
1187 pinctrl-names = "default";
1190 dma-names = "tx", "rx";
1197 interconnect-names = "qup-core",
1198 "qup-config",
1199 "qup-memory";
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1206 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1211 pinctrl-0 = <&qup_spi2_default>;
1212 pinctrl-names = "default";
1215 dma-names = "tx", "rx";
1220 interconnect-names = "qup-core",
1221 "qup-config";
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1228 compatible = "qcom,geni-i2c";
1232 clock-names = "se";
1233 pinctrl-0 = <&qup_i2c3_default>;
1234 pinctrl-names = "default";
1237 dma-names = "tx", "rx";
1244 interconnect-names = "qup-core",
1245 "qup-config",
1246 "qup-memory";
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1253 compatible = "qcom,geni-spi";
1257 clock-names = "se";
1258 pinctrl-0 = <&qup_spi3_default>;
1259 pinctrl-names = "default";
1262 dma-names = "tx", "rx";
1267 interconnect-names = "qup-core",
1268 "qup-config";
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1275 compatible = "qcom,geni-uart";
1279 clock-names = "se";
1280 pinctrl-0 = <&qup_uart3_default>;
1281 pinctrl-names = "default";
1286 interconnect-names = "qup-core",
1287 "qup-config";
1292 compatible = "qcom,geni-i2c";
1296 clock-names = "se";
1297 pinctrl-0 = <&qup_i2c4_default>;
1298 pinctrl-names = "default";
1301 dma-names = "tx", "rx";
1308 interconnect-names = "qup-core",
1309 "qup-config",
1310 "qup-memory";
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1317 compatible = "qcom,geni-spi";
1320 clock-names = "se";
1322 pinctrl-names = "default";
1323 pinctrl-0 = <&qup_spi4_default>;
1326 dma-names = "tx", "rx";
1331 interconnect-names = "qup-core",
1332 "qup-config";
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1339 compatible = "qcom,geni-uart";
1343 clock-names = "se";
1344 pinctrl-0 = <&qup_uart4_default>;
1345 pinctrl-names = "default";
1350 interconnect-names = "qup-core",
1351 "qup-config";
1356 compatible = "qcom,geni-i2c";
1360 clock-names = "se";
1361 pinctrl-0 = <&qup_i2c5_default>;
1362 pinctrl-names = "default";
1365 dma-names = "tx", "rx";
1372 interconnect-names = "qup-core",
1373 "qup-config",
1374 "qup-memory";
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1381 compatible = "qcom,geni-spi";
1385 clock-names = "se";
1386 pinctrl-0 = <&qup_spi5_default>;
1387 pinctrl-names = "default";
1390 dma-names = "tx", "rx";
1395 interconnect-names = "qup-core",
1396 "qup-config";
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1404 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1406 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1408 interrupt-names = "hs_phy_irq",
1417 clock-names = "cfg_noc",
1424 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1426 assigned-clock-rates = <19200000>, <133333333>;
1429 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1430 /* TODO: USB<->IPA path */
1435 interconnect-names = "usb-ddr",
1436 "apps-usb";
1437 wakeup-source;
1439 #address-cells = <2>;
1440 #size-cells = <2>;
1450 phy-names = "usb2-phy", "usb3-phy";
1454 snps,has-lpm-erratum;
1455 snps,hird-threshold = /bits/ 8 <0x10>;
1457 maximum-speed = "super-speed";
1459 usb-role-switch;
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1476 remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1484 compatible = "qcom,adreno-07000200", "qcom,adreno";
1486 reg-names = "kgsl_3d0_reg_memory";
1496 clock-names = "core",
1505 interconnect-names = "gfx-mem";
1509 operating-points-v2 = <&gpu_opp_table>;
1510 power-domains = <&rpmpd QCM2290_VDDCX>;
1513 nvmem-cells = <&gpu_speed_bin>;
1514 nvmem-cell-names = "speed_bin";
1515 #cooling-cells = <2>;
1519 zap-shader {
1520 memory-region = <&pil_gpu_mem>;
1523 gpu_opp_table: opp-table {
1524 compatible = "operating-points-v2";
1527 opp-1123200000 {
1528 opp-hz = /bits/ 64 <1123200000>;
1529 required-opps = <&rpmpd_opp_turbo_plus>;
1530 opp-peak-kBps = <6881000>;
1531 opp-supported-hw = <0x3>;
1532 turbo-mode;
1535 opp-1017600000 {
1536 opp-hz = /bits/ 64 <1017600000>;
1537 required-opps = <&rpmpd_opp_turbo>;
1538 opp-peak-kBps = <6881000>;
1539 opp-supported-hw = <0x3>;
1540 turbo-mode;
1543 opp-921600000 {
1544 opp-hz = /bits/ 64 <921600000>;
1545 required-opps = <&rpmpd_opp_nom_plus>;
1546 opp-peak-kBps = <6881000>;
1547 opp-supported-hw = <0x3>;
1550 opp-844800000 {
1551 opp-hz = /bits/ 64 <844800000>;
1552 required-opps = <&rpmpd_opp_nom>;
1553 opp-peak-kBps = <6881000>;
1554 opp-supported-hw = <0x7>;
1557 opp-672000000 {
1558 opp-hz = /bits/ 64 <672000000>;
1559 required-opps = <&rpmpd_opp_svs_plus>;
1560 opp-peak-kBps = <3879000>;
1561 opp-supported-hw = <0xf>;
1564 opp-537600000 {
1565 opp-hz = /bits/ 64 <537600000>;
1566 required-opps = <&rpmpd_opp_svs>;
1567 opp-peak-kBps = <2929000>;
1568 opp-supported-hw = <0xf>;
1571 opp-355200000 {
1572 opp-hz = /bits/ 64 <355200000>;
1573 required-opps = <&rpmpd_opp_low_svs>;
1574 opp-peak-kBps = <1720000>;
1575 opp-supported-hw = <0xf>;
1581 compatible = "qcom,adreno-gmu-wrapper";
1583 reg-names = "gmu";
1584 power-domains = <&gpucc GPU_CX_GDSC>,
1586 power-domain-names = "cx",
1590 gpucc: clock-controller@5990000 {
1591 compatible = "qcom,qcm2290-gpucc";
1597 power-domains = <&rpmpd QCM2290_VDDCX>;
1598 required-opps = <&rpmpd_opp_low_svs>;
1599 #clock-cells = <1>;
1600 #reset-cells = <1>;
1601 #power-domain-cells = <1>;
1605 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu",
1606 "qcom,smmu-500", "arm,mmu-500";
1621 clock-names = "mem",
1625 power-domains = <&gpucc GPU_CX_GDSC>;
1627 #global-interrupts = <1>;
1628 #iommu-cells = <2>;
1632 compatible = "qcom,qcm2290-camss";
1643 reg-names = "csid0",
1668 clock-names = "ahb",
1692 interrupt-names = "csid0",
1707 interconnect-names = "ahb",
1716 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
1721 #address-cells = <1>;
1722 #size-cells = <0>;
1734 mdss: display-subsystem@5e00000 {
1735 compatible = "qcom,qcm2290-mdss";
1737 reg-names = "mdss";
1739 interrupt-controller;
1740 #interrupt-cells = <1>;
1745 clock-names = "iface",
1751 power-domains = <&dispcc MDSS_GDSC>;
1759 interconnect-names = "mdp0-mem",
1760 "cpu-cfg";
1762 #address-cells = <2>;
1763 #size-cells = <2>;
1768 mdp: display-controller@5e01000 {
1769 compatible = "qcom,qcm2290-dpu";
1772 reg-names = "mdp",
1775 interrupt-parent = <&mdss>;
1783 clock-names = "bus",
1789 operating-points-v2 = <&mdp_opp_table>;
1790 power-domains = <&rpmpd QCM2290_VDDCX>;
1793 #address-cells = <1>;
1794 #size-cells = <0>;
1799 remote-endpoint = <&mdss_dsi0_in>;
1804 mdp_opp_table: opp-table {
1805 compatible = "operating-points-v2";
1807 opp-19200000 {
1808 opp-hz = /bits/ 64 <19200000>;
1809 required-opps = <&rpmpd_opp_min_svs>;
1812 opp-192000000 {
1813 opp-hz = /bits/ 64 <192000000>;
1814 required-opps = <&rpmpd_opp_low_svs>;
1817 opp-256000000 {
1818 opp-hz = /bits/ 64 <256000000>;
1819 required-opps = <&rpmpd_opp_svs>;
1822 opp-307200000 {
1823 opp-hz = /bits/ 64 <307200000>;
1824 required-opps = <&rpmpd_opp_svs_plus>;
1827 opp-384000000 {
1828 opp-hz = /bits/ 64 <384000000>;
1829 required-opps = <&rpmpd_opp_nom>;
1835 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1837 reg-names = "dsi_ctrl";
1839 interrupt-parent = <&mdss>;
1848 clock-names = "byte",
1855 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1857 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1860 operating-points-v2 = <&dsi_opp_table>;
1861 power-domains = <&rpmpd QCM2290_VDDCX>;
1864 #address-cells = <1>;
1865 #size-cells = <0>;
1869 dsi_opp_table: opp-table {
1870 compatible = "operating-points-v2";
1872 opp-19200000 {
1873 opp-hz = /bits/ 64 <19200000>;
1874 required-opps = <&rpmpd_opp_min_svs>;
1877 opp-164000000 {
1878 opp-hz = /bits/ 64 <164000000>;
1879 required-opps = <&rpmpd_opp_low_svs>;
1882 opp-187500000 {
1883 opp-hz = /bits/ 64 <187500000>;
1884 required-opps = <&rpmpd_opp_svs>;
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1896 remote-endpoint = <&dpu_intf1_out>;
1910 compatible = "qcom,dsi-phy-14nm-2290";
1914 reg-names = "dsi_phy",
1920 clock-names = "iface",
1923 power-domains = <&rpmpd QCM2290_VDDMX>;
1924 required-opps = <&rpmpd_opp_nom>;
1926 #clock-cells = <1>;
1927 #phy-cells = <0>;
1933 dispcc: clock-controller@5f00000 {
1934 compatible = "qcom,qcm2290-dispcc";
1942 clock-names = "bi_tcxo",
1948 #power-domain-cells = <1>;
1949 #clock-cells = <1>;
1950 #reset-cells = <1>;
1954 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1957 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1963 interrupt-names = "wdog",
1967 "stop-ack",
1968 "shutdown-ack";
1971 clock-names = "xo";
1973 power-domains = <&rpmpd QCM2290_VDDCX>;
1975 memory-region = <&pil_modem_mem>;
1977 qcom,smem-states = <&modem_smp2p_out 0>;
1978 qcom,smem-state-names = "stop";
1982 glink-edge {
1985 qcom,remote-pid = <1>;
1991 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1994 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1999 interrupt-names = "wdog",
2003 "stop-ack";
2006 clock-names = "xo";
2008 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
2011 memory-region = <&pil_adsp_mem>;
2013 qcom,smem-states = <&adsp_smp2p_out 0>;
2014 qcom,smem-state-names = "stop";
2018 glink-edge {
2021 qcom,remote-pid = <2>;
2027 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2029 #iommu-cells = <2>;
2030 #global-interrupts = <1>;
2100 compatible = "qcom,wcn3990-wifi";
2102 reg-names = "membase";
2103 memory-region = <&wlan_msa_mem>;
2117 qcom,msa-fixed-perm;
2122 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
2130 compatible = "qcom,qcm2290-apcs-hmss-global";
2132 #mbox-cells = <1>;
2136 compatible = "arm,armv7-timer-mem";
2138 #address-cells = <1>;
2139 #size-cells = <1>;
2147 frame-number = <0>;
2153 frame-number = <1>;
2160 frame-number = <2>;
2167 frame-number = <3>;
2174 frame-number = <4>;
2181 frame-number = <5>;
2188 frame-number = <6>;
2193 intc: interrupt-controller@f200000 {
2194 compatible = "arm,gic-v3";
2198 #interrupt-cells = <3>;
2199 interrupt-controller;
2200 interrupt-parent = <&intc>;
2201 #redistributor-regions = <1>;
2202 redistributor-stride = <0x0 0x20000>;
2206 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
2208 reg-names = "freq-domain0";
2209 interrupts-extended = <&lmh_cluster 0>;
2210 interrupt-names = "dcvsh-irq-0";
2212 clock-names = "xo", "alternate";
2214 #freq-domain-cells = <1>;
2215 #clock-cells = <1>;
2219 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh";
2223 qcom,lmh-temp-arm-millicelsius = <65000>;
2224 qcom,lmh-temp-low-millicelsius = <94500>;
2225 qcom,lmh-temp-high-millicelsius = <95000>;
2226 interrupt-controller;
2227 #interrupt-cells = <1>;
2231 thermal-zones {
2232 mapss-thermal {
2233 thermal-sensors = <&tsens0 0>;
2236 mapss_alert0: trip-point0 {
2242 mapss_alert1: trip-point1 {
2248 mapss_crit: mapss-crit {
2256 video-thermal {
2257 thermal-sensors = <&tsens0 1>;
2260 video_alert0: trip-point0 {
2266 video_alert1: trip-point1 {
2272 video_crit: video-crit {
2280 wlan-thermal {
2281 thermal-sensors = <&tsens0 2>;
2284 wlan_alert0: trip-point0 {
2290 wlan_alert1: trip-point1 {
2296 wlan_crit: wlan-crit {
2304 cpuss0-thermal {
2305 thermal-sensors = <&tsens0 3>;
2308 cpuss0_alert0: trip-point0 {
2314 cpuss0_alert1: trip-point1 {
2320 cpuss0_crit: cpuss0-crit {
2328 cpuss1-thermal {
2329 thermal-sensors = <&tsens0 4>;
2332 cpuss1_alert0: trip-point0 {
2338 cpuss1_alert1: trip-point1 {
2344 cpuss1_crit: cpuss1-crit {
2352 mdm0-thermal {
2353 thermal-sensors = <&tsens0 5>;
2356 mdm0_alert0: trip-point0 {
2362 mdm0_alert1: trip-point1 {
2368 mdm0_crit: mdm0-crit {
2376 mdm1-thermal {
2377 thermal-sensors = <&tsens0 6>;
2380 mdm1_alert0: trip-point0 {
2386 mdm1_alert1: trip-point1 {
2392 mdm1_crit: mdm1-crit {
2400 gpu-thermal {
2401 thermal-sensors = <&tsens0 7>;
2404 gpu_alert0: trip-point0 {
2410 gpu_alert1: trip-point1 {
2416 gpu_crit: gpu-crit {
2424 hm-center-thermal {
2425 thermal-sensors = <&tsens0 8>;
2428 hm_center_alert0: trip-point0 {
2434 hm_center_alert1: trip-point1 {
2440 hm_center_crit: hm-center-crit {
2448 camera-thermal {
2449 thermal-sensors = <&tsens0 9>;
2452 camera_alert0: trip-point0 {
2458 camera_alert1: trip-point1 {
2464 camera_crit: camera-crit {
2474 compatible = "arm,armv8-timer";