Lines Matching +full:0 +full:x05e00000
31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
67 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 0>;
73 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x2>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
95 reg = <0x0 0x3>;
96 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
127 CLUSTER_SLEEP: cluster-sleep-0 {
129 arm,psci-suspend-param = <0x41000043>;
139 CPU_SLEEP: cpu-sleep-0 {
142 arm,psci-suspend-param = <0x40000003>;
165 reg = <0 0x40000000 0 0>;
178 #power-domain-cells = <0>;
184 #power-domain-cells = <0>;
190 #power-domain-cells = <0>;
196 #power-domain-cells = <0>;
202 #power-domain-cells = <0>;
215 mboxes = <&apcs_glb 0>;
279 #power-domain-cells = <0>;
297 reg = <0x0 0x45700000 0x0 0x600000>;
302 reg = <0x0 0x45e00000 0x0 0x140000>;
307 reg = <0x0 0x45fff000 0x0 0x1000>;
313 reg = <0x0 0x46000000 0x0 0x200000>;
321 reg = <0x0 0x4ab00000 0x0 0x6900000>;
326 reg = <0x0 0x51400000 0x0 0x500000>;
331 reg = <0x0 0x51900000 0x0 0x100000>;
336 reg = <0x0 0x51a00000 0x0 0x1c00000>;
341 reg = <0x0 0x53600000 0x0 0x10000>;
346 reg = <0x0 0x53610000 0x0 0x5000>;
352 reg = <0x0 0x53615000 0x0 0x2000>;
357 reg = <0x0 0x5c000000 0x0 0x00f00000>;
362 reg = <0x0 0x5cf00000 0x0 0x0100000>;
367 reg = <0x0 0x60000000 0x0 0x3900000>;
373 reg = <0x0 0x89b01000 0x0 0x200000>;
389 qcom,local-pid = <0>;
412 qcom,local-pid = <0>;
433 soc: soc@0 {
437 ranges = <0 0 0 0 0x10 0>;
438 dma-ranges = <0 0 0 0 0x10 0>;
442 reg = <0x0 0x00340000 0x0 0x20000>;
448 reg = <0x0 0x003c0000 0x0 0x40000>;
453 reg = <0x0 0x00500000 0x0 0x300000>;
456 gpio-ranges = <&tlmm 0 0 127>;
653 reg = <0x0 0x01400000 0x0 0x1f0000>;
663 reg = <0x0 0x01613000 0x0 0x180>;
671 #phy-cells = <0>;
678 reg = <0x0 0x01615000 0x0 0x1000>;
694 #clock-cells = <0>;
697 #phy-cells = <0>;
700 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
706 #size-cells = <0>;
708 port@0 {
709 reg = <0>;
727 reg = <0x0 0x01880000 0x0 0x60200>;
748 reg = <0x0 0x01900000 0x0 0x8200>;
754 reg = <0x0 0x01b44000 0x0 0x3000>;
759 reg = <0x25b 0x1>;
764 reg = <0x2006 0x2>;
771 reg = <0x0 0x01b8e300 0x0 0x600>;
781 opp-0 {
825 reg = <0x0 0x01c40000 0x0 0x1100>,
826 <0x0 0x01e00000 0x0 0x2000000>,
827 <0x0 0x03e00000 0x0 0x100000>,
828 <0x0 0x03f00000 0x0 0xa0000>,
829 <0x0 0x01c0a000 0x0 0x26000>;
837 qcom,ee = <0>;
838 qcom,channel = <0>;
840 #size-cells = <0>;
847 reg = <0x0 0x04411000 0x0 0x1ff>,
848 <0x0 0x04410000 0x0 0x8>;
858 reg = <0x0 0x04453000 0x0 0x1000>;
865 reg = <0x0 0x04480000 0x0 0x80000>;
871 reg = <0x0 0x045f0000 0x0 0x7000>;
874 ranges = <0 0x0 0x045f0000 0x7000>;
877 reg = <0x1b8 0x48>;
883 reg = <0x0 0x04690000 0x0 0x10000>;
888 reg = <0x0 0x04744000 0x0 0x1000>,
889 <0x0 0x04745000 0x0 0x1000>,
890 <0x0 0x04748000 0x0 0x8000>;
912 iommus = <&apps_smmu 0xc0 0x0>;
920 qcom,dll-config = <0x000f642c>;
921 qcom,ddr-config = <0x80040868>;
954 reg = <0x0 0x04784000 0x0 0x1000>;
972 iommus = <&apps_smmu 0xa0 0x0>;
980 qcom,dll-config = <0x0007642c>;
981 qcom,ddr-config = <0x80040868>;
1007 reg = <0x0 0x04a00000 0x0 0x60000>;
1019 dma-channel-mask = <0x1f>;
1020 iommus = <&apps_smmu 0xf6 0x0>;
1027 reg = <0x0 0x04ac0000 0x0 0x2000>;
1031 iommus = <&apps_smmu 0xe3 0x0>;
1039 reg = <0x0 0x04a80000 0x0 0x4000>;
1043 pinctrl-0 = <&qup_i2c0_default>;
1045 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1046 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1058 #size-cells = <0>;
1064 reg = <0x0 0x04a80000 0x0 0x4000>;
1068 pinctrl-0 = <&qup_spi0_default>;
1070 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1071 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1080 #size-cells = <0>;
1086 reg = <0x0 0x04a80000 0x0 0x4000>;
1090 pinctrl-0 = <&qup_uart0_default>;
1103 reg = <0x0 0x04a84000 0x0 0x4000>;
1107 pinctrl-0 = <&qup_i2c1_default>;
1109 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1122 #size-cells = <0>;
1128 reg = <0x0 0x04a84000 0x0 0x4000>;
1132 pinctrl-0 = <&qup_spi1_default>;
1134 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1144 #size-cells = <0>;
1150 reg = <0x0 0x04a88000 0x0 0x4000>;
1154 pinctrl-0 = <&qup_i2c2_default>;
1156 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1169 #size-cells = <0>;
1175 reg = <0x0 0x04a88000 0x0 0x4000>;
1179 pinctrl-0 = <&qup_spi2_default>;
1181 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1191 #size-cells = <0>;
1197 reg = <0x0 0x04a8c000 0x0 0x4000>;
1201 pinctrl-0 = <&qup_i2c3_default>;
1203 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1216 #size-cells = <0>;
1222 reg = <0x0 0x04a8c000 0x0 0x4000>;
1226 pinctrl-0 = <&qup_spi3_default>;
1228 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1238 #size-cells = <0>;
1244 reg = <0x0 0x04a90000 0x0 0x4000>;
1248 pinctrl-0 = <&qup_i2c4_default>;
1250 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1263 #size-cells = <0>;
1269 reg = <0x0 0x04a90000 0x0 0x4000>;
1274 pinctrl-0 = <&qup_spi4_default>;
1275 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1285 #size-cells = <0>;
1291 reg = <0x0 0x04a90000 0x0 0x4000>;
1295 pinctrl-0 = <&qup_uart4_default>;
1308 reg = <0x0 0x04a94000 0x0 0x4000>;
1312 pinctrl-0 = <&qup_i2c5_default>;
1314 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1327 #size-cells = <0>;
1333 reg = <0x0 0x04a94000 0x0 0x4000>;
1337 pinctrl-0 = <&qup_spi5_default>;
1339 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1349 #size-cells = <0>;
1356 reg = <0x0 0x04ef8800 0x0 0x400>;
1398 reg = <0x0 0x04e00000 0x0 0xcd00>;
1402 iommus = <&apps_smmu 0x120 0x0>;
1406 snps,hird-threshold = /bits/ 8 <0x10>;
1414 #size-cells = <0>;
1416 port@0 {
1417 reg = <0>;
1436 reg = <0x0 0x05900000 0x0 0x40000>;
1458 iommus = <&adreno_smmu 0 1>,
1459 <&adreno_smmu 2 0>;
1482 opp-supported-hw = <0x3>;
1490 opp-supported-hw = <0x3>;
1498 opp-supported-hw = <0x3>;
1505 opp-supported-hw = <0x7>;
1512 opp-supported-hw = <0xf>;
1519 opp-supported-hw = <0xf>;
1526 opp-supported-hw = <0xf>;
1533 reg = <0x0 0x0596a000 0x0 0x30000>;
1543 reg = <0x0 0x05990000 0x0 0x9000>;
1558 reg = <0x0 0x059a0000 0x0 0x10000>;
1584 reg = <0x0 0x05e00000 0x0 0x1000>;
1601 iommus = <&apps_smmu 0x420 0x2>,
1602 <&apps_smmu 0x421 0x0>;
1618 reg = <0x0 0x05e01000 0x0 0x8f000>,
1619 <0x0 0x05eb0000 0x0 0x2008>;
1624 interrupts = <0>;
1642 #size-cells = <0>;
1644 port@0 {
1645 reg = <0>;
1684 reg = <0x0 0x05e94000 0x0 0x400>;
1705 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1713 #size-cells = <0>;
1738 #size-cells = <0>;
1740 port@0 {
1741 reg = <0>;
1759 reg = <0x0 0x05e94400 0x0 0x100>,
1760 <0x0 0x05e94500 0x0 0x300>,
1761 <0x0 0x05e94800 0x0 0x188>;
1775 #phy-cells = <0>;
1783 reg = <0x0 0x05f00000 0x0 0x20000>;
1788 <&mdss_dsi0_phy 0>,
1803 reg = <0x0 0x06080000 0x0 0x100>;
1806 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1825 qcom,smem-states = <&modem_smp2p_out 0>;
1840 reg = <0x0 0x0ab00000 0x0 0x100>;
1843 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1861 qcom,smem-states = <&adsp_smp2p_out 0>;
1876 reg = <0x0 0x0c600000 0x0 0x80000>;
1949 reg = <0x0 0x0c800000 0x0 0x800000>;
1964 iommus = <&apps_smmu 0x1a0 0x1>;
1971 reg = <0x0 0x0f017000 0x0 0x1000>;
1979 reg = <0x0 0x0f111000 0x0 0x1000>;
1985 reg = <0x0 0x0f120000 0x0 0x1000>;
1988 ranges = <0 0x0 0x0f121000 0x8000>;
1990 frame@0 {
1991 reg = <0x0 0x1000>,
1992 <0x1000 0x1000>;
1995 frame-number = <0>;
1999 reg = <0x2000 0x1000>;
2006 reg = <0x3000 0x1000>;
2013 reg = <0x4000 0x1000>;
2020 reg = <0x5000 0x1000>;
2027 reg = <0x6000 0x1000>;
2034 reg = <0x7000 0x1000>;
2043 reg = <0x0 0x0f200000 0x0 0x10000>,
2044 <0x0 0x0f300000 0x0 0x100000>;
2050 redistributor-stride = <0x0 0x20000>;
2055 reg = <0x0 0x0f521000 0x0 0x1000>;
2057 interrupts-extended = <&lmh_cluster 0>;
2058 interrupt-names = "dcvsh-irq-0";
2068 reg = <0x0 0x0f550800 0x0 0x400>;
2081 thermal-sensors = <&tsens0 0>;
2326 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;