Lines Matching refs:mmcc
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
2774 mmcc: clock-controller@c8c0000 { label
2775 compatible = "qcom,mmcc-msm8998";
2812 clocks = <&mmcc MDSS_AHB_CLK>,
2813 <&mmcc MDSS_AXI_CLK>,
2814 <&mmcc MDSS_MDP_CLK>;
2819 power-domains = <&mmcc MDSS_GDSC>;
2842 clocks = <&mmcc MDSS_AHB_CLK>,
2843 <&mmcc MDSS_AXI_CLK>,
2844 <&mmcc MNOC_AHB_CLK>,
2845 <&mmcc MDSS_MDP_CLK>,
2846 <&mmcc MDSS_VSYNC_CLK>;
2853 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2921 clocks = <&mmcc MDSS_BYTE0_CLK>,
2922 <&mmcc MDSS_BYTE0_INTF_CLK>,
2923 <&mmcc MDSS_PCLK0_CLK>,
2924 <&mmcc MDSS_ESC0_CLK>,
2925 <&mmcc MDSS_AHB_CLK>,
2926 <&mmcc MDSS_AXI_CLK>;
2933 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2934 <&mmcc PCLK0_CLK_SRC>;
2979 clocks = <&mmcc MDSS_AHB_CLK>,
2997 clocks = <&mmcc MDSS_BYTE1_CLK>,
2998 <&mmcc MDSS_BYTE1_INTF_CLK>,
2999 <&mmcc MDSS_PCLK1_CLK>,
3000 <&mmcc MDSS_ESC1_CLK>,
3001 <&mmcc MDSS_AHB_CLK>,
3002 <&mmcc MDSS_AXI_CLK>;
3009 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
3010 <&mmcc PCLK1_CLK_SRC>;
3055 clocks = <&mmcc MDSS_AHB_CLK>,
3078 clocks = <&mmcc MDSS_MDP_CLK>,
3079 <&mmcc MDSS_AHB_CLK>,
3080 <&mmcc MDSS_HDMI_CLK>,
3081 <&mmcc MDSS_HDMI_DP_AHB_CLK>,
3082 <&mmcc MDSS_EXTPCLK_CLK>,
3083 <&mmcc MDSS_AXI_CLK>,
3084 <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc MISC_AHB_CLK>;
3146 clocks = <&mmcc MDSS_AHB_CLK>,
3161 power-domains = <&mmcc VIDEO_TOP_GDSC>;
3162 clocks = <&mmcc VIDEO_CORE_CLK>,
3163 <&mmcc VIDEO_AHB_CLK>,
3164 <&mmcc VIDEO_AXI_CLK>,
3165 <&mmcc VIDEO_MAXI_CLK>;
3192 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
3194 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3199 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
3201 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3210 clocks = <&mmcc MNOC_AHB_CLK>,
3211 <&mmcc BIMC_SMMU_AHB_CLK>,
3212 <&mmcc BIMC_SMMU_AXI_CLK>;
3240 power-domains = <&mmcc BIMC_SMMU_GDSC>;