Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h>
14 interrupt-parent = <&intc>;
16 qcom,msm-id = <292 0x0>;
18 #address-cells = <2>;
19 #size-cells = <2>;
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
36 no-map;
41 no-map;
44 smem_mem: smem-mem@86000000 {
46 no-map;
51 no-map;
55 compatible = "qcom,rmtfs-mem";
57 no-map;
59 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
65 no-map;
70 no-map;
75 no-map;
80 no-map;
85 no-map;
90 no-map;
95 no-map;
100 no-map;
105 no-map;
110 no-map;
113 mdata_mem: mpss-metadata {
114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
116 no-map;
121 xo: xo-board {
122 compatible = "fixed-clock";
123 #clock-cells = <0>;
124 clock-frequency = <19200000>;
125 clock-output-names = "xo_board";
128 sleep_clk: sleep-clk {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <32764>;
136 #address-cells = <2>;
137 #size-cells = <0>;
141 compatible = "qcom,kryo280";
143 enable-method = "psci";
144 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
146 next-level-cache = <&l2_0>;
147 l2_0: l2-cache {
149 cache-level = <2>;
150 cache-unified;
156 compatible = "qcom,kryo280";
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
161 next-level-cache = <&l2_0>;
166 compatible = "qcom,kryo280";
168 enable-method = "psci";
169 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
171 next-level-cache = <&l2_0>;
176 compatible = "qcom,kryo280";
178 enable-method = "psci";
179 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
181 next-level-cache = <&l2_0>;
186 compatible = "qcom,kryo280";
188 enable-method = "psci";
189 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
191 next-level-cache = <&l2_1>;
192 l2_1: l2-cache {
194 cache-level = <2>;
195 cache-unified;
201 compatible = "qcom,kryo280";
203 enable-method = "psci";
204 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
206 next-level-cache = <&l2_1>;
211 compatible = "qcom,kryo280";
213 enable-method = "psci";
214 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
216 next-level-cache = <&l2_1>;
221 compatible = "qcom,kryo280";
223 enable-method = "psci";
224 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
226 next-level-cache = <&l2_1>;
229 cpu-map {
267 idle-states {
268 entry-method = "psci";
270 little_cpu_sleep_0: cpu-sleep-0-0 {
271 compatible = "arm,idle-state";
272 idle-state-name = "little-retention";
274 arm,psci-suspend-param = <0x00000002>;
275 entry-latency-us = <81>;
276 exit-latency-us = <86>;
277 min-residency-us = <504>;
280 little_cpu_sleep_1: cpu-sleep-0-1 {
281 compatible = "arm,idle-state";
282 idle-state-name = "little-power-collapse";
284 arm,psci-suspend-param = <0x40000003>;
285 entry-latency-us = <814>;
286 exit-latency-us = <4562>;
287 min-residency-us = <9183>;
288 local-timer-stop;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "big-retention";
295 arm,psci-suspend-param = <0x00000002>;
296 entry-latency-us = <79>;
297 exit-latency-us = <82>;
298 min-residency-us = <1302>;
301 big_cpu_sleep_1: cpu-sleep-1-1 {
302 compatible = "arm,idle-state";
303 idle-state-name = "big-power-collapse";
305 arm,psci-suspend-param = <0x40000003>;
306 entry-latency-us = <724>;
307 exit-latency-us = <2027>;
308 min-residency-us = <9419>;
309 local-timer-stop;
316 compatible = "qcom,scm-msm8998", "qcom,scm";
320 dsi_opp_table: opp-table-dsi {
321 compatible = "operating-points-v2";
323 opp-131250000 {
324 opp-hz = /bits/ 64 <131250000>;
325 required-opps = <&rpmpd_opp_low_svs>;
328 opp-210000000 {
329 opp-hz = /bits/ 64 <210000000>;
330 required-opps = <&rpmpd_opp_svs>;
333 opp-312500000 {
334 opp-hz = /bits/ 64 <312500000>;
335 required-opps = <&rpmpd_opp_nom>;
340 compatible = "arm,psci-1.0";
345 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
347 glink-edge {
348 compatible = "qcom,glink-rpm";
351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
354 rpm_requests: rpm-requests {
355 compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm";
356 qcom,glink-channels = "rpm_requests";
358 rpmcc: clock-controller {
359 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
361 clock-names = "xo";
362 #clock-cells = <1>;
365 rpmpd: power-controller {
366 compatible = "qcom,msm8998-rpmpd";
367 #power-domain-cells = <1>;
368 operating-points-v2 = <&rpmpd_opp_table>;
370 rpmpd_opp_table: opp-table {
371 compatible = "operating-points-v2";
374 opp-level = <RPM_SMD_LEVEL_RETENTION>;
378 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
382 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
386 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
390 opp-level = <RPM_SMD_LEVEL_SVS>;
394 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
398 opp-level = <RPM_SMD_LEVEL_NOM>;
402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
406 opp-level = <RPM_SMD_LEVEL_TURBO>;
410 opp-level = <RPM_SMD_LEVEL_BINNING>;
419 compatible = "qcom,smem";
420 memory-region = <&smem_mem>;
424 smp2p-lpass {
425 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>;
432 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>;
435 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells = <1>;
440 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "slave-kernel";
443 interrupt-controller;
444 #interrupt-cells = <2>;
448 smp2p-mpss {
449 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>;
453 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>;
456 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells = <1>;
461 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "slave-kernel";
463 interrupt-controller;
464 #interrupt-cells = <2>;
468 smp2p-slpi {
469 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>;
473 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>;
476 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells = <1>;
481 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "slave-kernel";
483 interrupt-controller;
484 #interrupt-cells = <2>;
488 thermal-zones {
489 cpu0-thermal {
490 polling-delay-passive = <250>;
492 thermal-sensors = <&tsens0 1>;
495 cpu0_alert0: trip-point0 {
501 cpu0_crit: cpu-crit {
509 cpu1-thermal {
510 polling-delay-passive = <250>;
512 thermal-sensors = <&tsens0 2>;
515 cpu1_alert0: trip-point0 {
521 cpu1_crit: cpu-crit {
529 cpu2-thermal {
530 polling-delay-passive = <250>;
532 thermal-sensors = <&tsens0 3>;
535 cpu2_alert0: trip-point0 {
541 cpu2_crit: cpu-crit {
549 cpu3-thermal {
550 polling-delay-passive = <250>;
552 thermal-sensors = <&tsens0 4>;
555 cpu3_alert0: trip-point0 {
561 cpu3_crit: cpu-crit {
569 cpu4-thermal {
570 polling-delay-passive = <250>;
572 thermal-sensors = <&tsens0 7>;
575 cpu4_alert0: trip-point0 {
581 cpu4_crit: cpu-crit {
589 cpu5-thermal {
590 polling-delay-passive = <250>;
592 thermal-sensors = <&tsens0 8>;
595 cpu5_alert0: trip-point0 {
601 cpu5_crit: cpu-crit {
609 cpu6-thermal {
610 polling-delay-passive = <250>;
612 thermal-sensors = <&tsens0 9>;
615 cpu6_alert0: trip-point0 {
621 cpu6_crit: cpu-crit {
629 cpu7-thermal {
630 polling-delay-passive = <250>;
632 thermal-sensors = <&tsens0 10>;
635 cpu7_alert0: trip-point0 {
641 cpu7_crit: cpu-crit {
649 gpu-bottom-thermal {
650 polling-delay-passive = <250>;
652 thermal-sensors = <&tsens0 12>;
655 gpu1_alert0: trip-point0 {
663 gpu-top-thermal {
664 polling-delay-passive = <250>;
666 thermal-sensors = <&tsens0 13>;
669 gpu2_alert0: trip-point0 {
677 clust0-mhm-thermal {
678 polling-delay-passive = <250>;
680 thermal-sensors = <&tsens0 5>;
683 cluster0_mhm_alert0: trip-point0 {
691 clust1-mhm-thermal {
692 polling-delay-passive = <250>;
694 thermal-sensors = <&tsens0 6>;
697 cluster1_mhm_alert0: trip-point0 {
705 cluster1-l2-thermal {
706 polling-delay-passive = <250>;
708 thermal-sensors = <&tsens0 11>;
711 cluster1_l2_alert0: trip-point0 {
719 modem-thermal {
720 polling-delay-passive = <250>;
722 thermal-sensors = <&tsens1 1>;
725 modem_alert0: trip-point0 {
733 mem-thermal {
734 polling-delay-passive = <250>;
736 thermal-sensors = <&tsens1 2>;
739 mem_alert0: trip-point0 {
747 wlan-thermal {
748 polling-delay-passive = <250>;
750 thermal-sensors = <&tsens1 3>;
753 wlan_alert0: trip-point0 {
761 q6-dsp-thermal {
762 polling-delay-passive = <250>;
764 thermal-sensors = <&tsens1 4>;
767 q6_dsp_alert0: trip-point0 {
775 camera-thermal {
776 polling-delay-passive = <250>;
778 thermal-sensors = <&tsens1 5>;
781 camera_alert0: trip-point0 {
789 multimedia-thermal {
790 polling-delay-passive = <250>;
792 thermal-sensors = <&tsens1 6>;
795 multimedia_alert0: trip-point0 {
805 compatible = "arm,armv8-timer";
813 #address-cells = <1>;
814 #size-cells = <1>;
816 compatible = "simple-bus";
818 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>;
821 #reset-cells = <1>;
822 #power-domain-cells = <1>;
825 clock-names = "xo", "sleep_clk";
830 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
832 * enabled but unused during boot-up), the device will most likely decide
835 * as protected. The board dts (or a user-supplied dts) can override the
839 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
845 compatible = "qcom,rpm-msg-ram";
850 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
852 #address-cells = <1>;
853 #size-cells = <1>;
855 qusb2_hstx_trim: hstx-trim@23a {
862 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
865 #qcom,sensors = <14>;
868 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells = <1>;
873 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
876 #qcom,sensors = <8>;
879 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells = <1>;
884 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
886 #iommu-cells = <1>;
888 #global-interrupts = <0>;
899 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
901 #iommu-cells = <1>;
903 #global-interrupts = <0>;
918 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
923 reg-names = "parf", "dbi", "elbi", "config";
925 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff>;
927 #address-cells = <3>;
928 #size-cells = <2>;
929 num-lanes = <1>;
931 phy-names = "pciephy";
937 #interrupt-cells = <1>;
939 interrupt-names = "msi";
940 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
951 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
953 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
960 bus-range = <0x01 0xff>;
962 #address-cells = <3>;
963 #size-cells = <2>;
968 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm8998-qmp-pcie-phy";
977 clock-names = "aux",
982 clock-output-names = "pcie_0_pipe_clk_src";
983 #clock-cells = <0>;
985 #phy-cells = <0>;
988 reset-names = "phy", "common";
990 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vreg_l2a_1p2>;
995 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
999 phy-names = "ufsphy";
1000 lanes-per-direction = <2>;
1001 power-domains = <&gcc UFS_GDSC>;
1003 #reset-cells = <1>;
1005 clock-names =
1023 freq-table-hz =
1034 reset-names = "rst";
1037 ufsphy: phy@1da7000 {
1038 compatible = "qcom,msm8998-qmp-ufs-phy";
1044 clock-names = "ref",
1048 reset-names = "ufsphy";
1051 #phy-cells = <0>;
1056 compatible = "qcom,tcsr-mutex";
1058 #hwlock-cells = <1>;
1062 compatible = "qcom,msm8998-tcsr", "syscon";
1067 compatible = "qcom,msm8998-tcsr", "syscon";
1072 compatible = "qcom,msm8998-pinctrl";
1075 gpio-ranges = <&tlmm 0 0 150>;
1076 gpio-controller;
1077 #gpio-cells = <2>;
1078 interrupt-controller;
1079 #interrupt-cells = <2>;
1081 sdc2_on: sdc2-on-state {
1082 clk-pins {
1084 drive-strength = <16>;
1085 bias-disable;
1088 cmd-pins {
1090 drive-strength = <10>;
1091 bias-pull-up;
1094 data-pins {
1096 drive-strength = <10>;
1097 bias-pull-up;
1101 sdc2_off: sdc2-off-state {
1102 clk-pins {
1104 drive-strength = <2>;
1105 bias-disable;
1108 cmd-pins {
1110 drive-strength = <2>;
1111 bias-pull-up;
1114 data-pins {
1116 drive-strength = <2>;
1117 bias-pull-up;
1121 sdc2_cd: sdc2-cd-state {
1124 bias-pull-up;
1125 drive-strength = <2>;
1128 blsp1_uart3_on: blsp1-uart3-on-state {
1129 tx-pins {
1132 drive-strength = <2>;
1133 bias-disable;
1136 rx-pins {
1139 drive-strength = <2>;
1140 bias-disable;
1143 cts-pins {
1146 drive-strength = <2>;
1147 bias-disable;
1150 rfr-pins {
1153 drive-strength = <2>;
1154 bias-disable;
1158 blsp1_i2c1_default: blsp1-i2c1-default-state {
1161 drive-strength = <2>;
1162 bias-disable;
1165 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1168 drive-strength = <2>;
1169 bias-pull-up;
1172 blsp1_i2c2_default: blsp1-i2c2-default-state {
1175 drive-strength = <2>;
1176 bias-disable;
1179 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1182 drive-strength = <2>;
1183 bias-pull-up;
1186 blsp1_i2c3_default: blsp1-i2c3-default-state {
1189 drive-strength = <2>;
1190 bias-disable;
1193 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1196 drive-strength = <2>;
1197 bias-pull-up;
1200 blsp1_i2c4_default: blsp1-i2c4-default-state {
1203 drive-strength = <2>;
1204 bias-disable;
1207 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1210 drive-strength = <2>;
1211 bias-pull-up;
1214 blsp1_i2c5_default: blsp1-i2c5-default-state {
1217 drive-strength = <2>;
1218 bias-disable;
1221 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1224 drive-strength = <2>;
1225 bias-pull-up;
1228 blsp1_i2c6_default: blsp1-i2c6-default-state {
1231 drive-strength = <2>;
1232 bias-disable;
1235 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1238 drive-strength = <2>;
1239 bias-pull-up;
1242 blsp1_spi_b_default: blsp1-spi-b-default-state {
1245 drive-strength = <6>;
1246 bias-disable;
1249 blsp1_spi1_default: blsp1-spi1-default-state {
1252 drive-strength = <6>;
1253 bias-disable;
1256 blsp1_spi2_default: blsp1-spi2-default-state {
1259 drive-strength = <6>;
1260 bias-disable;
1263 blsp1_spi3_default: blsp1-spi3-default-state {
1266 drive-strength = <6>;
1267 bias-disable;
1270 blsp1_spi4_default: blsp1-spi4-default-state {
1273 drive-strength = <6>;
1274 bias-disable;
1277 blsp1_spi5_default: blsp1-spi5-default-state {
1280 drive-strength = <6>;
1281 bias-disable;
1284 blsp1_spi6_default: blsp1-spi6-default-state {
1287 drive-strength = <6>;
1288 bias-disable;
1293 blsp2_i2c1_default: blsp2-i2c1-default-state {
1296 drive-strength = <2>;
1297 bias-disable;
1300 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1303 drive-strength = <2>;
1304 bias-pull-up;
1307 blsp2_i2c2_default: blsp2-i2c2-default-state {
1310 drive-strength = <2>;
1311 bias-disable;
1314 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1317 drive-strength = <2>;
1318 bias-pull-up;
1321 blsp2_i2c3_default: blsp2-i2c3-default-state {
1324 drive-strength = <2>;
1325 bias-disable;
1328 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1331 drive-strength = <2>;
1332 bias-pull-up;
1335 blsp2_i2c4_default: blsp2-i2c4-default-state {
1338 drive-strength = <2>;
1339 bias-disable;
1342 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1345 drive-strength = <2>;
1346 bias-pull-up;
1349 blsp2_i2c5_default: blsp2-i2c5-default-state {
1352 drive-strength = <2>;
1353 bias-disable;
1356 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1359 drive-strength = <2>;
1360 bias-pull-up;
1363 blsp2_i2c6_default: blsp2-i2c6-default-state {
1366 drive-strength = <2>;
1367 bias-disable;
1370 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1373 drive-strength = <2>;
1374 bias-pull-up;
1377 blsp2_spi1_default: blsp2-spi1-default-state {
1380 drive-strength = <6>;
1381 bias-disable;
1384 blsp2_spi2_default: blsp2-spi2-default-state {
1387 drive-strength = <6>;
1388 bias-disable;
1391 blsp2_spi3_default: blsp2-spi3-default-state {
1394 drive-strength = <6>;
1395 bias-disable;
1398 blsp2_spi4_default: blsp2-spi4-default-state {
1401 drive-strength = <6>;
1402 bias-disable;
1405 blsp2_spi5_default: blsp2-spi5-default-state {
1408 drive-strength = <6>;
1409 bias-disable;
1412 blsp2_spi6_default: blsp2-spi6-default-state {
1415 drive-strength = <6>;
1416 bias-disable;
1419 hdmi_cec_default: hdmi-cec-default-state {
1422 drive-strength = <2>;
1423 bias-pull-up;
1426 hdmi_ddc_default: hdmi-ddc-default-state {
1429 drive-strength = <2>;
1430 bias-pull-up;
1433 hdmi_hpd_default: hdmi-hpd-default-state {
1436 drive-strength = <16>;
1437 bias-pull-down;
1440 hdmi_hpd_sleep: hdmi-hpd-sleep-state {
1443 drive-strength = <2>;
1444 bias-pull-down;
1449 compatible = "qcom,msm8998-mss-pil";
1451 reg-names = "qdsp6", "rmb";
1453 interrupts-extended =
1460 interrupt-names = "wdog", "fatal", "ready",
1461 "handover", "stop-ack",
1462 "shutdown-ack";
1472 clock-names = "iface", "bus", "mem", "gpll0_mss",
1475 qcom,smem-states = <&modem_smp2p_out 0>;
1476 qcom,smem-state-names = "stop";
1479 reset-names = "mss_restart";
1481 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1483 power-domains = <&rpmpd MSM8998_VDDCX>,
1485 power-domain-names = "cx", "mx";
1490 memory-region = <&mba_mem>;
1494 memory-region = <&mpss_mem>;
1498 memory-region = <&mdata_mem>;
1501 glink-edge {
1504 qcom,remote-pid = <1>;
1510 compatible = "qcom,adreno-540.1", "qcom,adreno";
1512 reg-names = "kgsl_3d0_reg_memory";
1520 clock-names = "iface",
1529 operating-points-v2 = <&gpu_opp_table>;
1530 power-domains = <&rpmpd MSM8998_VDDMX>;
1533 gpu_opp_table: opp-table {
1534 compatible = "operating-points-v2";
1535 opp-710000097 {
1536 opp-hz = /bits/ 64 <710000097>;
1537 opp-level = <RPM_SMD_LEVEL_TURBO>;
1538 opp-supported-hw = <0xff>;
1541 opp-670000048 {
1542 opp-hz = /bits/ 64 <670000048>;
1543 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1544 opp-supported-hw = <0xff>;
1547 opp-596000097 {
1548 opp-hz = /bits/ 64 <596000097>;
1549 opp-level = <RPM_SMD_LEVEL_NOM>;
1550 opp-supported-hw = <0xff>;
1553 opp-515000097 {
1554 opp-hz = /bits/ 64 <515000097>;
1555 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1556 opp-supported-hw = <0xff>;
1559 opp-414000000 {
1560 opp-hz = /bits/ 64 <414000000>;
1561 opp-level = <RPM_SMD_LEVEL_SVS>;
1562 opp-supported-hw = <0xff>;
1565 opp-342000000 {
1566 opp-hz = /bits/ 64 <342000000>;
1567 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1568 opp-supported-hw = <0xff>;
1571 opp-257000000 {
1572 opp-hz = /bits/ 64 <257000000>;
1573 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1574 opp-supported-hw = <0xff>;
1580 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1585 clock-names = "iface", "mem", "mem_iface";
1587 #global-interrupts = <0>;
1588 #iommu-cells = <1>;
1594 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1595 * GPU-CX for SMMU but we need both of them up for Adreno.
1601 power-domains = <&gpucc GPU_GX_GDSC>;
1604 gpucc: clock-controller@5065000 {
1605 compatible = "qcom,msm8998-gpucc";
1606 #clock-cells = <1>;
1607 #reset-cells = <1>;
1608 #power-domain-cells = <1>;
1613 clock-names = "xo",
1618 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1621 clock-names = "bus";
1623 #global-interrupts = <0>;
1624 #iommu-cells = <1>;
1640 power-domains = <&gcc LPASS_ADSP_GDSC>;
1645 compatible = "qcom,msm8998-slpi-pas";
1648 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1653 interrupt-names = "wdog", "fatal", "ready",
1654 "handover", "stop-ack";
1656 px-supply = <&vreg_lvs2a_1p8>;
1659 clock-names = "xo";
1661 memory-region = <&slpi_mem>;
1663 qcom,smem-states = <&slpi_smp2p_out 0>;
1664 qcom,smem-state-names = "stop";
1666 power-domains = <&rpmpd MSM8998_SSCCX>;
1667 power-domain-names = "ssc_cx";
1671 glink-edge {
1674 qcom,remote-pid = <3>;
1680 compatible = "arm,coresight-stm", "arm,primecell";
1683 reg-names = "stm-base", "stm-stimulus-base";
1687 clock-names = "apb_pclk", "atclk";
1689 out-ports {
1692 remote-endpoint = <&funnel0_in7>;
1699 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1704 clock-names = "apb_pclk", "atclk";
1706 out-ports {
1709 remote-endpoint =
1715 in-ports {
1716 #address-cells = <1>;
1717 #size-cells = <0>;
1722 remote-endpoint = <&stm_out>;
1729 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1734 clock-names = "apb_pclk", "atclk";
1736 out-ports {
1739 remote-endpoint =
1745 in-ports {
1746 #address-cells = <1>;
1747 #size-cells = <0>;
1752 remote-endpoint =
1760 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1765 clock-names = "apb_pclk", "atclk";
1767 out-ports {
1770 remote-endpoint =
1776 in-ports {
1777 #address-cells = <1>;
1778 #size-cells = <0>;
1783 remote-endpoint =
1791 remote-endpoint =
1799 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1804 clock-names = "apb_pclk", "atclk";
1806 out-ports {
1809 remote-endpoint = <&etr_in>;
1814 in-ports {
1817 remote-endpoint = <&etf_out>;
1824 compatible = "arm,coresight-tmc", "arm,primecell";
1829 clock-names = "apb_pclk", "atclk";
1831 out-ports {
1834 remote-endpoint =
1840 in-ports {
1843 remote-endpoint =
1851 compatible = "arm,coresight-tmc", "arm,primecell";
1856 clock-names = "apb_pclk", "atclk";
1857 arm,scatter-gather;
1859 in-ports {
1862 remote-endpoint =
1870 compatible = "arm,coresight-etm4x", "arm,primecell";
1875 clock-names = "apb_pclk", "atclk";
1879 out-ports {
1882 remote-endpoint =
1890 compatible = "arm,coresight-etm4x", "arm,primecell";
1895 clock-names = "apb_pclk", "atclk";
1899 out-ports {
1902 remote-endpoint =
1910 compatible = "arm,coresight-etm4x", "arm,primecell";
1915 clock-names = "apb_pclk", "atclk";
1919 out-ports {
1922 remote-endpoint =
1930 compatible = "arm,coresight-etm4x", "arm,primecell";
1935 clock-names = "apb_pclk", "atclk";
1939 out-ports {
1942 remote-endpoint =
1950 compatible = "arm,coresight-etm4x", "arm,primecell";
1955 clock-names = "apb_pclk", "atclk";
1957 out-ports {
1960 remote-endpoint =
1966 in-ports {
1967 #address-cells = <1>;
1968 #size-cells = <0>;
1973 remote-endpoint =
1981 remote-endpoint =
1989 remote-endpoint =
1997 remote-endpoint =
2005 remote-endpoint =
2013 remote-endpoint =
2021 remote-endpoint =
2029 remote-endpoint =
2037 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2042 clock-names = "apb_pclk", "atclk";
2044 out-ports {
2047 remote-endpoint =
2053 in-ports {
2056 remote-endpoint =
2064 compatible = "arm,coresight-etm4x", "arm,primecell";
2069 clock-names = "apb_pclk", "atclk";
2073 out-ports {
2076 remote-endpoint = <&apss_funnel_in4>;
2083 compatible = "arm,coresight-etm4x", "arm,primecell";
2088 clock-names = "apb_pclk", "atclk";
2092 out-ports {
2095 remote-endpoint = <&apss_funnel_in5>;
2102 compatible = "arm,coresight-etm4x", "arm,primecell";
2107 clock-names = "apb_pclk", "atclk";
2111 out-ports {
2114 remote-endpoint = <&apss_funnel_in6>;
2121 compatible = "arm,coresight-etm4x", "arm,primecell";
2126 clock-names = "apb_pclk", "atclk";
2130 out-ports {
2133 remote-endpoint = <&apss_funnel_in7>;
2140 compatible = "qcom,rpm-stats";
2145 compatible = "qcom,spmi-pmic-arb";
2151 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2152 interrupt-names = "periph_irq";
2154 qcom,ee = <0>;
2155 qcom,channel = <0>;
2156 #address-cells = <2>;
2157 #size-cells = <0>;
2158 interrupt-controller;
2159 #interrupt-cells = <4>;
2163 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2166 #address-cells = <1>;
2167 #size-cells = <1>;
2175 clock-names = "cfg_noc",
2181 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2183 assigned-clock-rates = <19200000>, <120000000>;
2188 interrupt-names = "pwr_event",
2192 power-domains = <&gcc USB_30_GDSC>;
2202 snps,parkmode-disable-ss-quirk;
2204 phy-names = "usb2-phy", "usb3-phy";
2205 snps,has-lpm-erratum;
2206 snps,hird-threshold = /bits/ 8 <0x10>;
2210 usb3phy: phy@c010000 {
2211 compatible = "qcom,msm8998-qmp-usb3-phy";
2218 clock-names = "aux",
2222 clock-output-names = "usb3_phy_pipe_clk_src";
2223 #clock-cells = <0>;
2224 #phy-cells = <0>;
2228 reset-names = "phy",
2231 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2236 qusb2phy: phy@c012000 {
2237 compatible = "qcom,msm8998-qusb2-phy";
2240 #phy-cells = <0>;
2244 clock-names = "cfg_ahb", "ref";
2248 nvmem-cells = <&qusb2_hstx_trim>;
2252 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2254 reg-names = "hc", "core";
2258 interrupt-names = "hc_irq", "pwr_irq";
2260 clock-names = "iface", "core", "xo";
2264 bus-width = <4>;
2268 blsp1_dma: dma-controller@c144000 {
2269 compatible = "qcom,bam-v1.7.0";
2273 clock-names = "bam_clk";
2274 #dma-cells = <1>;
2275 qcom,ee = <0>;
2276 qcom,controlled-remotely;
2277 num-channels = <18>;
2278 qcom,num-ees = <4>;
2282 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2287 clock-names = "core", "iface";
2289 dma-names = "tx", "rx";
2290 pinctrl-names = "default";
2291 pinctrl-0 = <&blsp1_uart3_on>;
2296 compatible = "qcom,i2c-qup-v2.2.1";
2302 clock-names = "core", "iface";
2304 dma-names = "tx", "rx";
2305 pinctrl-names = "default", "sleep";
2306 pinctrl-0 = <&blsp1_i2c1_default>;
2307 pinctrl-1 = <&blsp1_i2c1_sleep>;
2308 clock-frequency = <400000>;
2311 #address-cells = <1>;
2312 #size-cells = <0>;
2316 compatible = "qcom,i2c-qup-v2.2.1";
2322 clock-names = "core", "iface";
2324 dma-names = "tx", "rx";
2325 pinctrl-names = "default", "sleep";
2326 pinctrl-0 = <&blsp1_i2c2_default>;
2327 pinctrl-1 = <&blsp1_i2c2_sleep>;
2328 clock-frequency = <400000>;
2331 #address-cells = <1>;
2332 #size-cells = <0>;
2336 compatible = "qcom,i2c-qup-v2.2.1";
2342 clock-names = "core", "iface";
2344 dma-names = "tx", "rx";
2345 pinctrl-names = "default", "sleep";
2346 pinctrl-0 = <&blsp1_i2c3_default>;
2347 pinctrl-1 = <&blsp1_i2c3_sleep>;
2348 clock-frequency = <400000>;
2351 #address-cells = <1>;
2352 #size-cells = <0>;
2356 compatible = "qcom,i2c-qup-v2.2.1";
2362 clock-names = "core", "iface";
2364 dma-names = "tx", "rx";
2365 pinctrl-names = "default", "sleep";
2366 pinctrl-0 = <&blsp1_i2c4_default>;
2367 pinctrl-1 = <&blsp1_i2c4_sleep>;
2368 clock-frequency = <400000>;
2371 #address-cells = <1>;
2372 #size-cells = <0>;
2376 compatible = "qcom,i2c-qup-v2.2.1";
2382 clock-names = "core", "iface";
2384 dma-names = "tx", "rx";
2385 pinctrl-names = "default", "sleep";
2386 pinctrl-0 = <&blsp1_i2c5_default>;
2387 pinctrl-1 = <&blsp1_i2c5_sleep>;
2388 clock-frequency = <400000>;
2391 #address-cells = <1>;
2392 #size-cells = <0>;
2396 compatible = "qcom,i2c-qup-v2.2.1";
2402 clock-names = "core", "iface";
2404 dma-names = "tx", "rx";
2405 pinctrl-names = "default", "sleep";
2406 pinctrl-0 = <&blsp1_i2c6_default>;
2407 pinctrl-1 = <&blsp1_i2c6_sleep>;
2408 clock-frequency = <400000>;
2411 #address-cells = <1>;
2412 #size-cells = <0>;
2416 compatible = "qcom,spi-qup-v2.2.1";
2422 clock-names = "core", "iface";
2424 dma-names = "tx", "rx";
2425 pinctrl-names = "default";
2426 pinctrl-0 = <&blsp1_spi1_default>;
2429 #address-cells = <1>;
2430 #size-cells = <0>;
2434 compatible = "qcom,spi-qup-v2.2.1";
2440 clock-names = "core", "iface";
2442 dma-names = "tx", "rx";
2443 pinctrl-names = "default";
2444 pinctrl-0 = <&blsp1_spi2_default>;
2447 #address-cells = <1>;
2448 #size-cells = <0>;
2452 compatible = "qcom,spi-qup-v2.2.1";
2458 clock-names = "core", "iface";
2460 dma-names = "tx", "rx";
2461 pinctrl-names = "default";
2462 pinctrl-0 = <&blsp1_spi3_default>;
2465 #address-cells = <1>;
2466 #size-cells = <0>;
2470 compatible = "qcom,spi-qup-v2.2.1";
2476 clock-names = "core", "iface";
2478 dma-names = "tx", "rx";
2479 pinctrl-names = "default";
2480 pinctrl-0 = <&blsp1_spi4_default>;
2483 #address-cells = <1>;
2484 #size-cells = <0>;
2488 compatible = "qcom,spi-qup-v2.2.1";
2494 clock-names = "core", "iface";
2496 dma-names = "tx", "rx";
2497 pinctrl-names = "default";
2498 pinctrl-0 = <&blsp1_spi5_default>;
2501 #address-cells = <1>;
2502 #size-cells = <0>;
2506 compatible = "qcom,spi-qup-v2.2.1";
2512 clock-names = "core", "iface";
2514 dma-names = "tx", "rx";
2515 pinctrl-names = "default";
2516 pinctrl-0 = <&blsp1_spi6_default>;
2519 #address-cells = <1>;
2520 #size-cells = <0>;
2523 blsp2_dma: dma-controller@c184000 {
2524 compatible = "qcom,bam-v1.7.0";
2528 clock-names = "bam_clk";
2529 #dma-cells = <1>;
2530 qcom,ee = <0>;
2531 qcom,controlled-remotely;
2532 num-channels = <18>;
2533 qcom,num-ees = <4>;
2537 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2542 clock-names = "core", "iface";
2547 compatible = "qcom,i2c-qup-v2.2.1";
2553 clock-names = "core", "iface";
2555 dma-names = "tx", "rx";
2556 pinctrl-names = "default", "sleep";
2557 pinctrl-0 = <&blsp2_i2c1_default>;
2558 pinctrl-1 = <&blsp2_i2c1_sleep>;
2559 clock-frequency = <400000>;
2562 #address-cells = <1>;
2563 #size-cells = <0>;
2567 compatible = "qcom,i2c-qup-v2.2.1";
2573 clock-names = "core", "iface";
2575 dma-names = "tx", "rx";
2576 pinctrl-names = "default", "sleep";
2577 pinctrl-0 = <&blsp2_i2c2_default>;
2578 pinctrl-1 = <&blsp2_i2c2_sleep>;
2579 clock-frequency = <400000>;
2582 #address-cells = <1>;
2583 #size-cells = <0>;
2587 compatible = "qcom,i2c-qup-v2.2.1";
2593 clock-names = "core", "iface";
2595 dma-names = "tx", "rx";
2596 pinctrl-names = "default", "sleep";
2597 pinctrl-0 = <&blsp2_i2c3_default>;
2598 pinctrl-1 = <&blsp2_i2c3_sleep>;
2599 clock-frequency = <400000>;
2602 #address-cells = <1>;
2603 #size-cells = <0>;
2607 compatible = "qcom,i2c-qup-v2.2.1";
2613 clock-names = "core", "iface";
2615 dma-names = "tx", "rx";
2616 pinctrl-names = "default", "sleep";
2617 pinctrl-0 = <&blsp2_i2c4_default>;
2618 pinctrl-1 = <&blsp2_i2c4_sleep>;
2619 clock-frequency = <400000>;
2622 #address-cells = <1>;
2623 #size-cells = <0>;
2627 compatible = "qcom,i2c-qup-v2.2.1";
2633 clock-names = "core", "iface";
2635 dma-names = "tx", "rx";
2636 pinctrl-names = "default", "sleep";
2637 pinctrl-0 = <&blsp2_i2c5_default>;
2638 pinctrl-1 = <&blsp2_i2c5_sleep>;
2639 clock-frequency = <400000>;
2642 #address-cells = <1>;
2643 #size-cells = <0>;
2647 compatible = "qcom,i2c-qup-v2.2.1";
2653 clock-names = "core", "iface";
2655 dma-names = "tx", "rx";
2656 pinctrl-names = "default", "sleep";
2657 pinctrl-0 = <&blsp2_i2c6_default>;
2658 pinctrl-1 = <&blsp2_i2c6_sleep>;
2659 clock-frequency = <400000>;
2662 #address-cells = <1>;
2663 #size-cells = <0>;
2667 compatible = "qcom,spi-qup-v2.2.1";
2673 clock-names = "core", "iface";
2675 dma-names = "tx", "rx";
2676 pinctrl-names = "default";
2677 pinctrl-0 = <&blsp2_spi1_default>;
2680 #address-cells = <1>;
2681 #size-cells = <0>;
2685 compatible = "qcom,spi-qup-v2.2.1";
2691 clock-names = "core", "iface";
2693 dma-names = "tx", "rx";
2694 pinctrl-names = "default";
2695 pinctrl-0 = <&blsp2_spi2_default>;
2698 #address-cells = <1>;
2699 #size-cells = <0>;
2703 compatible = "qcom,spi-qup-v2.2.1";
2709 clock-names = "core", "iface";
2711 dma-names = "tx", "rx";
2712 pinctrl-names = "default";
2713 pinctrl-0 = <&blsp2_spi3_default>;
2716 #address-cells = <1>;
2717 #size-cells = <0>;
2721 compatible = "qcom,spi-qup-v2.2.1";
2727 clock-names = "core", "iface";
2729 dma-names = "tx", "rx";
2730 pinctrl-names = "default";
2731 pinctrl-0 = <&blsp2_spi4_default>;
2734 #address-cells = <1>;
2735 #size-cells = <0>;
2739 compatible = "qcom,spi-qup-v2.2.1";
2745 clock-names = "core", "iface";
2747 dma-names = "tx", "rx";
2748 pinctrl-names = "default";
2749 pinctrl-0 = <&blsp2_spi5_default>;
2752 #address-cells = <1>;
2753 #size-cells = <0>;
2757 compatible = "qcom,spi-qup-v2.2.1";
2763 clock-names = "core", "iface";
2765 dma-names = "tx", "rx";
2766 pinctrl-names = "default";
2767 pinctrl-0 = <&blsp2_spi6_default>;
2770 #address-cells = <1>;
2771 #size-cells = <0>;
2774 mmcc: clock-controller@c8c0000 {
2775 compatible = "qcom,mmcc-msm8998";
2776 #clock-cells = <1>;
2777 #reset-cells = <1>;
2778 #power-domain-cells = <1>;
2781 clock-names = "xo",
2803 mdss: display-subsystem@c900000 {
2804 compatible = "qcom,msm8998-mdss";
2806 reg-names = "mdss";
2809 interrupt-controller;
2810 #interrupt-cells = <1>;
2815 clock-names = "iface",
2819 power-domains = <&mmcc MDSS_GDSC>;
2822 #address-cells = <1>;
2823 #size-cells = <1>;
2828 mdss_mdp: display-controller@c901000 {
2829 compatible = "qcom,msm8998-dpu";
2834 reg-names = "mdp",
2839 interrupt-parent = <&mdss>;
2847 clock-names = "iface",
2853 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2854 assigned-clock-rates = <19200000>;
2856 operating-points-v2 = <&mdp_opp_table>;
2857 power-domains = <&rpmpd MSM8998_VDDMX>;
2859 mdp_opp_table: opp-table {
2860 compatible = "operating-points-v2";
2862 opp-171430000 {
2863 opp-hz = /bits/ 64 <171430000>;
2864 required-opps = <&rpmpd_opp_low_svs>;
2867 opp-275000000 {
2868 opp-hz = /bits/ 64 <275000000>;
2869 required-opps = <&rpmpd_opp_svs>;
2872 opp-330000000 {
2873 opp-hz = /bits/ 64 <330000000>;
2874 required-opps = <&rpmpd_opp_nom>;
2877 opp-412500000 {
2878 opp-hz = /bits/ 64 <412500000>;
2879 required-opps = <&rpmpd_opp_turbo>;
2884 #address-cells = <1>;
2885 #size-cells = <0>;
2891 remote-endpoint = <&mdss_dsi0_in>;
2899 remote-endpoint = <&mdss_dsi1_in>;
2907 remote-endpoint = <&hdmi_in>;
2914 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2916 reg-names = "dsi_ctrl";
2918 interrupt-parent = <&mdss>;
2927 clock-names = "byte",
2933 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2935 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2938 operating-points-v2 = <&dsi_opp_table>;
2939 power-domains = <&rpmpd MSM8998_VDDCX>;
2942 phy-names = "dsi";
2944 #address-cells = <1>;
2945 #size-cells = <0>;
2950 #address-cells = <1>;
2951 #size-cells = <0>;
2957 remote-endpoint = <&dpu_intf1_out>;
2970 mdss_dsi0_phy: phy@c994400 {
2971 compatible = "qcom,dsi-phy-10nm-8998";
2975 reg-names = "dsi_phy",
2981 clock-names = "iface", "ref";
2983 #clock-cells = <1>;
2984 #phy-cells = <0>;
2990 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2992 reg-names = "dsi_ctrl";
2994 interrupt-parent = <&mdss>;
3003 clock-names = "byte",
3009 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
3011 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3014 operating-points-v2 = <&dsi_opp_table>;
3015 power-domains = <&rpmpd MSM8998_VDDCX>;
3018 phy-names = "dsi";
3020 #address-cells = <1>;
3021 #size-cells = <0>;
3026 #address-cells = <1>;
3027 #size-cells = <0>;
3033 remote-endpoint = <&dpu_intf2_out>;
3046 mdss_dsi1_phy: phy@c996400 {
3047 compatible = "qcom,dsi-phy-10nm-8998";
3051 reg-names = "dsi_phy",
3057 clock-names = "iface",
3060 #clock-cells = <1>;
3061 #phy-cells = <0>;
3066 mdss_hdmi: hdmi-tx@c9a0000 {
3067 compatible = "qcom,hdmi-tx-8998";
3071 reg-names = "core_physical",
3075 interrupt-parent = <&mdss>;
3086 clock-names =
3097 #sound-dai-cells = <1>;
3099 pinctrl-0 = <&hdmi_hpd_default>,
3102 pinctrl-1 = <&hdmi_hpd_sleep>,
3105 pinctrl-names = "default", "sleep";
3110 #address-cells = <1>;
3111 #size-cells = <0>;
3116 remote-endpoint = <&dpu_intf3_out>;
3128 mdss_hdmi_phy: hdmi-phy@c9a0600 {
3129 compatible = "qcom,hdmi-phy-8998";
3136 reg-names = "hdmi_pll",
3143 #clock-cells = <0>;
3144 #phy-cells = <0>;
3149 clock-names = "iface",
3157 venus: video-codec@cc00000 {
3158 compatible = "qcom,msm8998-venus";
3161 power-domains = <&mmcc VIDEO_TOP_GDSC>;
3166 clock-names = "core", "iface", "bus", "mbus";
3187 memory-region = <&venus_mem>;
3190 video-decoder {
3191 compatible = "venus-decoder";
3193 clock-names = "core";
3194 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3197 video-encoder {
3198 compatible = "venus-encoder";
3200 clock-names = "core";
3201 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3206 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3208 #iommu-cells = <1>;
3213 clock-names = "iface-mm",
3214 "iface-smmu",
3215 "bus-smmu";
3217 #global-interrupts = <0>;
3240 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3244 compatible = "qcom,msm8998-adsp-pas";
3247 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3252 interrupt-names = "wdog", "fatal", "ready",
3253 "handover", "stop-ack";
3256 clock-names = "xo";
3258 memory-region = <&adsp_mem>;
3260 qcom,smem-states = <&adsp_smp2p_out 0>;
3261 qcom,smem-state-names = "stop";
3263 power-domains = <&rpmpd MSM8998_VDDCX>;
3264 power-domain-names = "cx";
3268 glink-edge {
3271 qcom,remote-pid = <2>;
3277 compatible = "qcom,msm8998-apcs-hmss-global",
3278 "qcom,msm8994-apcs-kpss-global";
3281 #mbox-cells = <1>;
3285 #address-cells = <1>;
3286 #size-cells = <1>;
3288 compatible = "arm,armv7-timer-mem";
3292 frame-number = <0>;
3300 frame-number = <1>;
3307 frame-number = <2>;
3314 frame-number = <3>;
3321 frame-number = <4>;
3328 frame-number = <5>;
3335 frame-number = <6>;
3342 intc: interrupt-controller@17a00000 {
3343 compatible = "arm,gic-v3";
3346 #interrupt-cells = <3>;
3347 #address-cells = <1>;
3348 #size-cells = <1>;
3350 interrupt-controller;
3351 #redistributor-regions = <1>;
3352 redistributor-stride = <0x0 0x20000>;
3357 compatible = "qcom,wcn3990-wifi";
3360 reg-names = "membase";
3361 memory-region = <&wlan_msa_mem>;
3363 clock-names = "cxo_ref_clk_pin";
3379 qcom,snoc-host-cap-8bit-quirk;
3380 qcom,no-msa-ready-indicator;