Lines Matching +full:phy +full:- +full:qcom +full:- +full:qmp
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
7 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/gpio/gpio.h>
15 interrupt-parent = <&intc>;
17 qcom,msm-id = <292 0x0>;
19 #address-cells = <2>;
20 #size-cells = <2>;
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
37 no-map;
42 no-map;
45 smem_mem: smem-mem@86000000 {
47 no-map;
52 no-map;
56 compatible = "qcom,rmtfs-mem";
58 no-map;
60 qcom,client-id = <1>;
61 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
66 no-map;
71 no-map;
76 no-map;
81 no-map;
86 no-map;
91 no-map;
96 no-map;
101 no-map;
106 no-map;
111 no-map;
114 mdata_mem: mpss-metadata {
115 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
117 no-map;
122 xo: xo-board {
123 compatible = "fixed-clock";
124 #clock-cells = <0>;
125 clock-frequency = <19200000>;
126 clock-output-names = "xo_board";
129 sleep_clk: sleep-clk {
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
132 clock-frequency = <32764>;
137 #address-cells = <2>;
138 #size-cells = <0>;
142 compatible = "qcom,kryo280";
144 enable-method = "psci";
145 capacity-dmips-mhz = <1024>;
146 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
147 next-level-cache = <&l2_0>;
148 l2_0: l2-cache {
150 cache-level = <2>;
151 cache-unified;
157 compatible = "qcom,kryo280";
159 enable-method = "psci";
160 capacity-dmips-mhz = <1024>;
161 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
162 next-level-cache = <&l2_0>;
167 compatible = "qcom,kryo280";
169 enable-method = "psci";
170 capacity-dmips-mhz = <1024>;
171 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
172 next-level-cache = <&l2_0>;
177 compatible = "qcom,kryo280";
179 enable-method = "psci";
180 capacity-dmips-mhz = <1024>;
181 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
182 next-level-cache = <&l2_0>;
187 compatible = "qcom,kryo280";
189 enable-method = "psci";
190 capacity-dmips-mhz = <1536>;
191 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
192 next-level-cache = <&l2_1>;
193 l2_1: l2-cache {
195 cache-level = <2>;
196 cache-unified;
202 compatible = "qcom,kryo280";
204 enable-method = "psci";
205 capacity-dmips-mhz = <1536>;
206 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
207 next-level-cache = <&l2_1>;
212 compatible = "qcom,kryo280";
214 enable-method = "psci";
215 capacity-dmips-mhz = <1536>;
216 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
217 next-level-cache = <&l2_1>;
222 compatible = "qcom,kryo280";
224 enable-method = "psci";
225 capacity-dmips-mhz = <1536>;
226 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
227 next-level-cache = <&l2_1>;
230 cpu-map {
268 idle-states {
269 entry-method = "psci";
271 little_cpu_sleep_0: cpu-sleep-0-0 {
272 compatible = "arm,idle-state";
273 idle-state-name = "little-retention";
275 arm,psci-suspend-param = <0x00000002>;
276 entry-latency-us = <81>;
277 exit-latency-us = <86>;
278 min-residency-us = <504>;
281 little_cpu_sleep_1: cpu-sleep-0-1 {
282 compatible = "arm,idle-state";
283 idle-state-name = "little-power-collapse";
285 arm,psci-suspend-param = <0x40000003>;
286 entry-latency-us = <814>;
287 exit-latency-us = <4562>;
288 min-residency-us = <9183>;
289 local-timer-stop;
292 big_cpu_sleep_0: cpu-sleep-1-0 {
293 compatible = "arm,idle-state";
294 idle-state-name = "big-retention";
296 arm,psci-suspend-param = <0x00000002>;
297 entry-latency-us = <79>;
298 exit-latency-us = <82>;
299 min-residency-us = <1302>;
302 big_cpu_sleep_1: cpu-sleep-1-1 {
303 compatible = "arm,idle-state";
304 idle-state-name = "big-power-collapse";
306 arm,psci-suspend-param = <0x40000003>;
307 entry-latency-us = <724>;
308 exit-latency-us = <2027>;
309 min-residency-us = <9419>;
310 local-timer-stop;
317 compatible = "qcom,scm-msm8998", "qcom,scm";
321 dsi_opp_table: opp-table-dsi {
322 compatible = "operating-points-v2";
324 opp-131250000 {
325 opp-hz = /bits/ 64 <131250000>;
326 required-opps = <&rpmpd_opp_low_svs>;
329 opp-210000000 {
330 opp-hz = /bits/ 64 <210000000>;
331 required-opps = <&rpmpd_opp_svs>;
334 opp-312500000 {
335 opp-hz = /bits/ 64 <312500000>;
336 required-opps = <&rpmpd_opp_nom>;
341 compatible = "arm,psci-1.0";
346 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
348 glink-edge {
349 compatible = "qcom,glink-rpm";
352 qcom,rpm-msg-ram = <&rpm_msg_ram>;
355 rpm_requests: rpm-requests {
356 compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm";
357 qcom,glink-channels = "rpm_requests";
359 rpmcc: clock-controller {
360 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
362 clock-names = "xo";
363 #clock-cells = <1>;
366 rpmpd: power-controller {
367 compatible = "qcom,msm8998-rpmpd";
368 #power-domain-cells = <1>;
369 operating-points-v2 = <&rpmpd_opp_table>;
371 rpmpd_opp_table: opp-table {
372 compatible = "operating-points-v2";
375 opp-level = <RPM_SMD_LEVEL_RETENTION>;
379 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
383 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
387 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
391 opp-level = <RPM_SMD_LEVEL_SVS>;
395 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
399 opp-level = <RPM_SMD_LEVEL_NOM>;
403 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
407 opp-level = <RPM_SMD_LEVEL_TURBO>;
411 opp-level = <RPM_SMD_LEVEL_BINNING>;
420 compatible = "qcom,smem";
421 memory-region = <&smem_mem>;
425 smp2p-lpass {
426 compatible = "qcom,smp2p";
427 qcom,smem = <443>, <429>;
433 qcom,local-pid = <0>;
434 qcom,remote-pid = <2>;
436 adsp_smp2p_out: master-kernel {
437 qcom,entry-name = "master-kernel";
438 #qcom,smem-state-cells = <1>;
441 adsp_smp2p_in: slave-kernel {
442 qcom,entry-name = "slave-kernel";
444 interrupt-controller;
445 #interrupt-cells = <2>;
449 smp2p-mpss {
450 compatible = "qcom,smp2p";
451 qcom,smem = <435>, <428>;
454 qcom,local-pid = <0>;
455 qcom,remote-pid = <1>;
457 modem_smp2p_out: master-kernel {
458 qcom,entry-name = "master-kernel";
459 #qcom,smem-state-cells = <1>;
462 modem_smp2p_in: slave-kernel {
463 qcom,entry-name = "slave-kernel";
464 interrupt-controller;
465 #interrupt-cells = <2>;
469 smp2p-slpi {
470 compatible = "qcom,smp2p";
471 qcom,smem = <481>, <430>;
474 qcom,local-pid = <0>;
475 qcom,remote-pid = <3>;
477 slpi_smp2p_out: master-kernel {
478 qcom,entry-name = "master-kernel";
479 #qcom,smem-state-cells = <1>;
482 slpi_smp2p_in: slave-kernel {
483 qcom,entry-name = "slave-kernel";
484 interrupt-controller;
485 #interrupt-cells = <2>;
489 thermal-zones {
490 cpu0-thermal {
491 polling-delay-passive = <250>;
493 thermal-sensors = <&tsens0 1>;
496 cpu0_alert0: trip-point0 {
502 cpu0_crit: cpu-crit {
510 cpu1-thermal {
511 polling-delay-passive = <250>;
513 thermal-sensors = <&tsens0 2>;
516 cpu1_alert0: trip-point0 {
522 cpu1_crit: cpu-crit {
530 cpu2-thermal {
531 polling-delay-passive = <250>;
533 thermal-sensors = <&tsens0 3>;
536 cpu2_alert0: trip-point0 {
542 cpu2_crit: cpu-crit {
550 cpu3-thermal {
551 polling-delay-passive = <250>;
553 thermal-sensors = <&tsens0 4>;
556 cpu3_alert0: trip-point0 {
562 cpu3_crit: cpu-crit {
570 cpu4-thermal {
571 polling-delay-passive = <250>;
573 thermal-sensors = <&tsens0 7>;
576 cpu4_alert0: trip-point0 {
582 cpu4_crit: cpu-crit {
590 cpu5-thermal {
591 polling-delay-passive = <250>;
593 thermal-sensors = <&tsens0 8>;
596 cpu5_alert0: trip-point0 {
602 cpu5_crit: cpu-crit {
610 cpu6-thermal {
611 polling-delay-passive = <250>;
613 thermal-sensors = <&tsens0 9>;
616 cpu6_alert0: trip-point0 {
622 cpu6_crit: cpu-crit {
630 cpu7-thermal {
631 polling-delay-passive = <250>;
633 thermal-sensors = <&tsens0 10>;
636 cpu7_alert0: trip-point0 {
642 cpu7_crit: cpu-crit {
650 gpu-bottom-thermal {
651 polling-delay-passive = <250>;
653 thermal-sensors = <&tsens0 12>;
656 gpu1_alert0: trip-point0 {
664 gpu-top-thermal {
665 polling-delay-passive = <250>;
667 thermal-sensors = <&tsens0 13>;
670 gpu2_alert0: trip-point0 {
678 clust0-mhm-thermal {
679 polling-delay-passive = <250>;
681 thermal-sensors = <&tsens0 5>;
684 cluster0_mhm_alert0: trip-point0 {
692 clust1-mhm-thermal {
693 polling-delay-passive = <250>;
695 thermal-sensors = <&tsens0 6>;
698 cluster1_mhm_alert0: trip-point0 {
706 cluster1-l2-thermal {
707 polling-delay-passive = <250>;
709 thermal-sensors = <&tsens0 11>;
712 cluster1_l2_alert0: trip-point0 {
720 modem-thermal {
721 polling-delay-passive = <250>;
723 thermal-sensors = <&tsens1 1>;
726 modem_alert0: trip-point0 {
734 mem-thermal {
735 polling-delay-passive = <250>;
737 thermal-sensors = <&tsens1 2>;
740 mem_alert0: trip-point0 {
748 wlan-thermal {
749 polling-delay-passive = <250>;
751 thermal-sensors = <&tsens1 3>;
754 wlan_alert0: trip-point0 {
762 q6-dsp-thermal {
763 polling-delay-passive = <250>;
765 thermal-sensors = <&tsens1 4>;
768 q6_dsp_alert0: trip-point0 {
776 camera-thermal {
777 polling-delay-passive = <250>;
779 thermal-sensors = <&tsens1 5>;
782 camera_alert0: trip-point0 {
790 multimedia-thermal {
791 polling-delay-passive = <250>;
793 thermal-sensors = <&tsens1 6>;
796 multimedia_alert0: trip-point0 {
806 compatible = "arm,armv8-timer";
814 #address-cells = <1>;
815 #size-cells = <1>;
817 compatible = "simple-bus";
819 gcc: clock-controller@100000 {
820 compatible = "qcom,gcc-msm8998";
821 #clock-cells = <1>;
822 #reset-cells = <1>;
823 #power-domain-cells = <1>;
826 clock-names = "xo", "sleep_clk";
831 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
833 * enabled but unused during boot-up), the device will most likely decide
836 * as protected. The board dts (or a user-supplied dts) can override the
840 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
846 compatible = "qcom,rpm-msg-ram";
851 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
853 #address-cells = <1>;
854 #size-cells = <1>;
856 qusb2_hstx_trim: hstx-trim@23a {
863 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
866 #qcom,sensors = <14>;
869 interrupt-names = "uplow", "critical";
870 #thermal-sensor-cells = <1>;
874 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
877 #qcom,sensors = <8>;
880 interrupt-names = "uplow", "critical";
881 #thermal-sensor-cells = <1>;
885 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
887 #iommu-cells = <1>;
889 #global-interrupts = <0>;
900 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
902 #iommu-cells = <1>;
904 #global-interrupts = <0>;
919 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
924 reg-names = "parf", "dbi", "elbi", "config";
926 linux,pci-domain = <0>;
927 bus-range = <0x00 0xff>;
928 #address-cells = <3>;
929 #size-cells = <2>;
930 num-lanes = <1>;
932 phy-names = "pciephy";
938 #interrupt-cells = <1>;
948 interrupt-names = "msi0",
957 interrupt-map-mask = <0 0 0 0x7>;
958 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
968 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
970 power-domains = <&gcc PCIE_0_GDSC>;
971 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
972 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
977 bus-range = <0x01 0xff>;
979 #address-cells = <3>;
980 #size-cells = <2>;
985 pcie_phy: phy@1c06000 {
986 compatible = "qcom,msm8998-qmp-pcie-phy";
994 clock-names = "aux",
999 clock-output-names = "pcie_0_pipe_clk_src";
1000 #clock-cells = <0>;
1002 #phy-cells = <0>;
1005 reset-names = "phy", "common";
1007 vdda-phy-supply = <&vreg_l1a_0p875>;
1008 vdda-pll-supply = <&vreg_l2a_1p2>;
1012 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1016 phy-names = "ufsphy";
1017 lanes-per-direction = <2>;
1018 power-domains = <&gcc UFS_GDSC>;
1020 #reset-cells = <1>;
1022 clock-names =
1040 freq-table-hz =
1051 reset-names = "rst";
1054 ufsphy: phy@1da7000 {
1055 compatible = "qcom,msm8998-qmp-ufs-phy";
1061 clock-names = "ref",
1065 reset-names = "ufsphy";
1068 #phy-cells = <0>;
1073 compatible = "qcom,tcsr-mutex";
1075 #hwlock-cells = <1>;
1079 compatible = "qcom,msm8998-tcsr", "syscon";
1084 compatible = "qcom,msm8998-tcsr", "syscon";
1089 compatible = "qcom,msm8998-pinctrl";
1092 gpio-ranges = <&tlmm 0 0 150>;
1093 gpio-controller;
1094 #gpio-cells = <2>;
1095 interrupt-controller;
1096 #interrupt-cells = <2>;
1098 sdc2_on: sdc2-on-state {
1099 clk-pins {
1101 drive-strength = <16>;
1102 bias-disable;
1105 cmd-pins {
1107 drive-strength = <10>;
1108 bias-pull-up;
1111 data-pins {
1113 drive-strength = <10>;
1114 bias-pull-up;
1118 sdc2_off: sdc2-off-state {
1119 clk-pins {
1121 drive-strength = <2>;
1122 bias-disable;
1125 cmd-pins {
1127 drive-strength = <2>;
1128 bias-pull-up;
1131 data-pins {
1133 drive-strength = <2>;
1134 bias-pull-up;
1138 sdc2_cd: sdc2-cd-state {
1141 bias-pull-up;
1142 drive-strength = <2>;
1145 blsp1_uart3_on: blsp1-uart3-on-state {
1146 tx-pins {
1149 drive-strength = <2>;
1150 bias-disable;
1153 rx-pins {
1156 drive-strength = <2>;
1157 bias-disable;
1160 cts-pins {
1163 drive-strength = <2>;
1164 bias-disable;
1167 rfr-pins {
1170 drive-strength = <2>;
1171 bias-disable;
1175 blsp1_i2c1_default: blsp1-i2c1-default-state {
1178 drive-strength = <2>;
1179 bias-disable;
1182 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1185 drive-strength = <2>;
1186 bias-pull-up;
1189 blsp1_i2c2_default: blsp1-i2c2-default-state {
1192 drive-strength = <2>;
1193 bias-disable;
1196 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1199 drive-strength = <2>;
1200 bias-pull-up;
1203 blsp1_i2c3_default: blsp1-i2c3-default-state {
1206 drive-strength = <2>;
1207 bias-disable;
1210 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1213 drive-strength = <2>;
1214 bias-pull-up;
1217 blsp1_i2c4_default: blsp1-i2c4-default-state {
1220 drive-strength = <2>;
1221 bias-disable;
1224 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1227 drive-strength = <2>;
1228 bias-pull-up;
1231 blsp1_i2c5_default: blsp1-i2c5-default-state {
1234 drive-strength = <2>;
1235 bias-disable;
1238 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1241 drive-strength = <2>;
1242 bias-pull-up;
1245 blsp1_i2c6_default: blsp1-i2c6-default-state {
1248 drive-strength = <2>;
1249 bias-disable;
1252 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1255 drive-strength = <2>;
1256 bias-pull-up;
1259 blsp1_spi_b_default: blsp1-spi-b-default-state {
1262 drive-strength = <6>;
1263 bias-disable;
1266 blsp1_spi1_default: blsp1-spi1-default-state {
1269 drive-strength = <6>;
1270 bias-disable;
1273 blsp1_spi2_default: blsp1-spi2-default-state {
1276 drive-strength = <6>;
1277 bias-disable;
1280 blsp1_spi3_default: blsp1-spi3-default-state {
1283 drive-strength = <6>;
1284 bias-disable;
1287 blsp1_spi4_default: blsp1-spi4-default-state {
1290 drive-strength = <6>;
1291 bias-disable;
1294 blsp1_spi5_default: blsp1-spi5-default-state {
1297 drive-strength = <6>;
1298 bias-disable;
1301 blsp1_spi6_default: blsp1-spi6-default-state {
1304 drive-strength = <6>;
1305 bias-disable;
1310 blsp2_i2c1_default: blsp2-i2c1-default-state {
1313 drive-strength = <2>;
1314 bias-disable;
1317 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1320 drive-strength = <2>;
1321 bias-pull-up;
1324 blsp2_i2c2_default: blsp2-i2c2-default-state {
1327 drive-strength = <2>;
1328 bias-disable;
1331 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1334 drive-strength = <2>;
1335 bias-pull-up;
1338 blsp2_i2c3_default: blsp2-i2c3-default-state {
1341 drive-strength = <2>;
1342 bias-disable;
1345 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1348 drive-strength = <2>;
1349 bias-pull-up;
1352 blsp2_i2c4_default: blsp2-i2c4-default-state {
1355 drive-strength = <2>;
1356 bias-disable;
1359 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1362 drive-strength = <2>;
1363 bias-pull-up;
1366 blsp2_i2c5_default: blsp2-i2c5-default-state {
1369 drive-strength = <2>;
1370 bias-disable;
1373 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1376 drive-strength = <2>;
1377 bias-pull-up;
1380 blsp2_i2c6_default: blsp2-i2c6-default-state {
1383 drive-strength = <2>;
1384 bias-disable;
1387 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1390 drive-strength = <2>;
1391 bias-pull-up;
1394 blsp2_spi1_default: blsp2-spi1-default-state {
1397 drive-strength = <6>;
1398 bias-disable;
1401 blsp2_spi2_default: blsp2-spi2-default-state {
1404 drive-strength = <6>;
1405 bias-disable;
1408 blsp2_spi3_default: blsp2-spi3-default-state {
1411 drive-strength = <6>;
1412 bias-disable;
1415 blsp2_spi4_default: blsp2-spi4-default-state {
1418 drive-strength = <6>;
1419 bias-disable;
1422 blsp2_spi5_default: blsp2-spi5-default-state {
1425 drive-strength = <6>;
1426 bias-disable;
1429 blsp2_spi6_default: blsp2-spi6-default-state {
1432 drive-strength = <6>;
1433 bias-disable;
1436 hdmi_cec_default: hdmi-cec-default-state {
1439 drive-strength = <2>;
1440 bias-pull-up;
1443 hdmi_ddc_default: hdmi-ddc-default-state {
1446 drive-strength = <2>;
1447 bias-pull-up;
1450 hdmi_hpd_default: hdmi-hpd-default-state {
1453 drive-strength = <16>;
1454 bias-pull-down;
1457 hdmi_hpd_sleep: hdmi-hpd-sleep-state {
1460 drive-strength = <2>;
1461 bias-pull-down;
1466 compatible = "qcom,msm8998-mss-pil";
1468 reg-names = "qdsp6", "rmb";
1470 interrupts-extended =
1477 interrupt-names = "wdog", "fatal", "ready",
1478 "handover", "stop-ack",
1479 "shutdown-ack";
1489 clock-names = "iface", "bus", "mem", "gpll0_mss",
1492 qcom,smem-states = <&modem_smp2p_out 0>;
1493 qcom,smem-state-names = "stop";
1496 reset-names = "mss_restart";
1498 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1500 power-domains = <&rpmpd MSM8998_VDDCX>,
1502 power-domain-names = "cx", "mx";
1507 memory-region = <&mba_mem>;
1511 memory-region = <&mpss_mem>;
1515 memory-region = <&mdata_mem>;
1518 glink-edge {
1521 qcom,remote-pid = <1>;
1527 compatible = "qcom,adreno-540.1", "qcom,adreno";
1529 reg-names = "kgsl_3d0_reg_memory";
1537 clock-names = "iface",
1546 operating-points-v2 = <&gpu_opp_table>;
1547 power-domains = <&rpmpd MSM8998_VDDMX>;
1550 gpu_opp_table: opp-table {
1551 compatible = "operating-points-v2";
1552 opp-710000097 {
1553 opp-hz = /bits/ 64 <710000097>;
1554 opp-level = <RPM_SMD_LEVEL_TURBO>;
1555 opp-supported-hw = <0xff>;
1558 opp-670000048 {
1559 opp-hz = /bits/ 64 <670000048>;
1560 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1561 opp-supported-hw = <0xff>;
1564 opp-596000097 {
1565 opp-hz = /bits/ 64 <596000097>;
1566 opp-level = <RPM_SMD_LEVEL_NOM>;
1567 opp-supported-hw = <0xff>;
1570 opp-515000097 {
1571 opp-hz = /bits/ 64 <515000097>;
1572 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1573 opp-supported-hw = <0xff>;
1576 opp-414000000 {
1577 opp-hz = /bits/ 64 <414000000>;
1578 opp-level = <RPM_SMD_LEVEL_SVS>;
1579 opp-supported-hw = <0xff>;
1582 opp-342000000 {
1583 opp-hz = /bits/ 64 <342000000>;
1584 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1585 opp-supported-hw = <0xff>;
1588 opp-257000000 {
1589 opp-hz = /bits/ 64 <257000000>;
1590 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1591 opp-supported-hw = <0xff>;
1597 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1602 clock-names = "iface", "mem", "mem_iface";
1604 #global-interrupts = <0>;
1605 #iommu-cells = <1>;
1611 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1612 * GPU-CX for SMMU but we need both of them up for Adreno.
1618 power-domains = <&gpucc GPU_GX_GDSC>;
1621 gpucc: clock-controller@5065000 {
1622 compatible = "qcom,msm8998-gpucc";
1623 #clock-cells = <1>;
1624 #reset-cells = <1>;
1625 #power-domain-cells = <1>;
1630 clock-names = "xo",
1635 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1638 clock-names = "bus";
1640 #global-interrupts = <0>;
1641 #iommu-cells = <1>;
1657 power-domains = <&gcc LPASS_ADSP_GDSC>;
1662 compatible = "qcom,msm8998-slpi-pas";
1665 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1670 interrupt-names = "wdog", "fatal", "ready",
1671 "handover", "stop-ack";
1673 px-supply = <&vreg_lvs2a_1p8>;
1676 clock-names = "xo";
1678 memory-region = <&slpi_mem>;
1680 qcom,smem-states = <&slpi_smp2p_out 0>;
1681 qcom,smem-state-names = "stop";
1683 power-domains = <&rpmpd MSM8998_SSCCX>;
1684 power-domain-names = "ssc_cx";
1688 glink-edge {
1691 qcom,remote-pid = <3>;
1697 compatible = "arm,coresight-stm", "arm,primecell";
1700 reg-names = "stm-base", "stm-stimulus-base";
1704 clock-names = "apb_pclk", "atclk";
1706 out-ports {
1709 remote-endpoint = <&funnel0_in7>;
1716 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1721 clock-names = "apb_pclk", "atclk";
1723 out-ports {
1726 remote-endpoint =
1732 in-ports {
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1739 remote-endpoint = <&stm_out>;
1746 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1751 clock-names = "apb_pclk", "atclk";
1753 out-ports {
1756 remote-endpoint =
1762 in-ports {
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1769 remote-endpoint =
1777 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1782 clock-names = "apb_pclk", "atclk";
1784 out-ports {
1787 remote-endpoint =
1793 in-ports {
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1800 remote-endpoint =
1808 remote-endpoint =
1816 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1821 clock-names = "apb_pclk", "atclk";
1823 out-ports {
1826 remote-endpoint = <&etr_in>;
1831 in-ports {
1834 remote-endpoint = <&etf_out>;
1841 compatible = "arm,coresight-tmc", "arm,primecell";
1846 clock-names = "apb_pclk", "atclk";
1848 out-ports {
1851 remote-endpoint =
1857 in-ports {
1860 remote-endpoint =
1868 compatible = "arm,coresight-tmc", "arm,primecell";
1873 clock-names = "apb_pclk", "atclk";
1874 arm,scatter-gather;
1876 in-ports {
1879 remote-endpoint =
1887 compatible = "arm,coresight-etm4x", "arm,primecell";
1892 clock-names = "apb_pclk", "atclk";
1896 out-ports {
1899 remote-endpoint =
1907 compatible = "arm,coresight-etm4x", "arm,primecell";
1912 clock-names = "apb_pclk", "atclk";
1916 out-ports {
1919 remote-endpoint =
1927 compatible = "arm,coresight-etm4x", "arm,primecell";
1932 clock-names = "apb_pclk", "atclk";
1936 out-ports {
1939 remote-endpoint =
1947 compatible = "arm,coresight-etm4x", "arm,primecell";
1952 clock-names = "apb_pclk", "atclk";
1956 out-ports {
1959 remote-endpoint =
1967 compatible = "arm,coresight-etm4x", "arm,primecell";
1972 clock-names = "apb_pclk", "atclk";
1974 out-ports {
1977 remote-endpoint =
1983 in-ports {
1984 #address-cells = <1>;
1985 #size-cells = <0>;
1990 remote-endpoint =
1998 remote-endpoint =
2006 remote-endpoint =
2014 remote-endpoint =
2022 remote-endpoint =
2030 remote-endpoint =
2038 remote-endpoint =
2046 remote-endpoint =
2054 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2059 clock-names = "apb_pclk", "atclk";
2061 out-ports {
2064 remote-endpoint =
2070 in-ports {
2073 remote-endpoint =
2081 compatible = "arm,coresight-etm4x", "arm,primecell";
2086 clock-names = "apb_pclk", "atclk";
2090 out-ports {
2093 remote-endpoint = <&apss_funnel_in4>;
2100 compatible = "arm,coresight-etm4x", "arm,primecell";
2105 clock-names = "apb_pclk", "atclk";
2109 out-ports {
2112 remote-endpoint = <&apss_funnel_in5>;
2119 compatible = "arm,coresight-etm4x", "arm,primecell";
2124 clock-names = "apb_pclk", "atclk";
2128 out-ports {
2131 remote-endpoint = <&apss_funnel_in6>;
2138 compatible = "arm,coresight-etm4x", "arm,primecell";
2143 clock-names = "apb_pclk", "atclk";
2147 out-ports {
2150 remote-endpoint = <&apss_funnel_in7>;
2157 compatible = "qcom,rpm-stats";
2162 compatible = "qcom,spmi-pmic-arb";
2168 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2169 interrupt-names = "periph_irq";
2171 qcom,ee = <0>;
2172 qcom,channel = <0>;
2173 #address-cells = <2>;
2174 #size-cells = <0>;
2175 interrupt-controller;
2176 #interrupt-cells = <4>;
2180 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2183 #address-cells = <1>;
2184 #size-cells = <1>;
2192 clock-names = "cfg_noc",
2198 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2200 assigned-clock-rates = <19200000>, <120000000>;
2205 interrupt-names = "pwr_event",
2209 power-domains = <&gcc USB_30_GDSC>;
2219 snps,parkmode-disable-ss-quirk;
2221 phy-names = "usb2-phy", "usb3-phy";
2222 snps,has-lpm-erratum;
2223 snps,hird-threshold = /bits/ 8 <0x10>;
2227 usb3phy: phy@c010000 {
2228 compatible = "qcom,msm8998-qmp-usb3-phy";
2235 clock-names = "aux",
2239 clock-output-names = "usb3_phy_pipe_clk_src";
2240 #clock-cells = <0>;
2241 #phy-cells = <0>;
2245 reset-names = "phy",
2248 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2253 qusb2phy: phy@c012000 {
2254 compatible = "qcom,msm8998-qusb2-phy";
2257 #phy-cells = <0>;
2261 clock-names = "cfg_ahb", "ref";
2265 nvmem-cells = <&qusb2_hstx_trim>;
2269 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2271 reg-names = "hc", "core";
2275 interrupt-names = "hc_irq", "pwr_irq";
2277 clock-names = "iface", "core", "xo";
2281 bus-width = <4>;
2285 blsp1_dma: dma-controller@c144000 {
2286 compatible = "qcom,bam-v1.7.0";
2290 clock-names = "bam_clk";
2291 #dma-cells = <1>;
2292 qcom,ee = <0>;
2293 qcom,controlled-remotely;
2294 num-channels = <18>;
2295 qcom,num-ees = <4>;
2299 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2304 clock-names = "core", "iface";
2306 dma-names = "tx", "rx";
2307 pinctrl-names = "default";
2308 pinctrl-0 = <&blsp1_uart3_on>;
2313 compatible = "qcom,i2c-qup-v2.2.1";
2319 clock-names = "core", "iface";
2321 dma-names = "tx", "rx";
2322 pinctrl-names = "default", "sleep";
2323 pinctrl-0 = <&blsp1_i2c1_default>;
2324 pinctrl-1 = <&blsp1_i2c1_sleep>;
2325 clock-frequency = <400000>;
2328 #address-cells = <1>;
2329 #size-cells = <0>;
2333 compatible = "qcom,i2c-qup-v2.2.1";
2339 clock-names = "core", "iface";
2341 dma-names = "tx", "rx";
2342 pinctrl-names = "default", "sleep";
2343 pinctrl-0 = <&blsp1_i2c2_default>;
2344 pinctrl-1 = <&blsp1_i2c2_sleep>;
2345 clock-frequency = <400000>;
2348 #address-cells = <1>;
2349 #size-cells = <0>;
2353 compatible = "qcom,i2c-qup-v2.2.1";
2359 clock-names = "core", "iface";
2361 dma-names = "tx", "rx";
2362 pinctrl-names = "default", "sleep";
2363 pinctrl-0 = <&blsp1_i2c3_default>;
2364 pinctrl-1 = <&blsp1_i2c3_sleep>;
2365 clock-frequency = <400000>;
2368 #address-cells = <1>;
2369 #size-cells = <0>;
2373 compatible = "qcom,i2c-qup-v2.2.1";
2379 clock-names = "core", "iface";
2381 dma-names = "tx", "rx";
2382 pinctrl-names = "default", "sleep";
2383 pinctrl-0 = <&blsp1_i2c4_default>;
2384 pinctrl-1 = <&blsp1_i2c4_sleep>;
2385 clock-frequency = <400000>;
2388 #address-cells = <1>;
2389 #size-cells = <0>;
2393 compatible = "qcom,i2c-qup-v2.2.1";
2399 clock-names = "core", "iface";
2401 dma-names = "tx", "rx";
2402 pinctrl-names = "default", "sleep";
2403 pinctrl-0 = <&blsp1_i2c5_default>;
2404 pinctrl-1 = <&blsp1_i2c5_sleep>;
2405 clock-frequency = <400000>;
2408 #address-cells = <1>;
2409 #size-cells = <0>;
2413 compatible = "qcom,i2c-qup-v2.2.1";
2419 clock-names = "core", "iface";
2421 dma-names = "tx", "rx";
2422 pinctrl-names = "default", "sleep";
2423 pinctrl-0 = <&blsp1_i2c6_default>;
2424 pinctrl-1 = <&blsp1_i2c6_sleep>;
2425 clock-frequency = <400000>;
2428 #address-cells = <1>;
2429 #size-cells = <0>;
2433 compatible = "qcom,spi-qup-v2.2.1";
2439 clock-names = "core", "iface";
2441 dma-names = "tx", "rx";
2442 pinctrl-names = "default";
2443 pinctrl-0 = <&blsp1_spi1_default>;
2446 #address-cells = <1>;
2447 #size-cells = <0>;
2451 compatible = "qcom,spi-qup-v2.2.1";
2457 clock-names = "core", "iface";
2459 dma-names = "tx", "rx";
2460 pinctrl-names = "default";
2461 pinctrl-0 = <&blsp1_spi2_default>;
2464 #address-cells = <1>;
2465 #size-cells = <0>;
2469 compatible = "qcom,spi-qup-v2.2.1";
2475 clock-names = "core", "iface";
2477 dma-names = "tx", "rx";
2478 pinctrl-names = "default";
2479 pinctrl-0 = <&blsp1_spi3_default>;
2482 #address-cells = <1>;
2483 #size-cells = <0>;
2487 compatible = "qcom,spi-qup-v2.2.1";
2493 clock-names = "core", "iface";
2495 dma-names = "tx", "rx";
2496 pinctrl-names = "default";
2497 pinctrl-0 = <&blsp1_spi4_default>;
2500 #address-cells = <1>;
2501 #size-cells = <0>;
2505 compatible = "qcom,spi-qup-v2.2.1";
2511 clock-names = "core", "iface";
2513 dma-names = "tx", "rx";
2514 pinctrl-names = "default";
2515 pinctrl-0 = <&blsp1_spi5_default>;
2518 #address-cells = <1>;
2519 #size-cells = <0>;
2523 compatible = "qcom,spi-qup-v2.2.1";
2529 clock-names = "core", "iface";
2531 dma-names = "tx", "rx";
2532 pinctrl-names = "default";
2533 pinctrl-0 = <&blsp1_spi6_default>;
2536 #address-cells = <1>;
2537 #size-cells = <0>;
2540 blsp2_dma: dma-controller@c184000 {
2541 compatible = "qcom,bam-v1.7.0";
2545 clock-names = "bam_clk";
2546 #dma-cells = <1>;
2547 qcom,ee = <0>;
2548 qcom,controlled-remotely;
2549 num-channels = <18>;
2550 qcom,num-ees = <4>;
2554 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2559 clock-names = "core", "iface";
2564 compatible = "qcom,i2c-qup-v2.2.1";
2570 clock-names = "core", "iface";
2572 dma-names = "tx", "rx";
2573 pinctrl-names = "default", "sleep";
2574 pinctrl-0 = <&blsp2_i2c1_default>;
2575 pinctrl-1 = <&blsp2_i2c1_sleep>;
2576 clock-frequency = <400000>;
2579 #address-cells = <1>;
2580 #size-cells = <0>;
2584 compatible = "qcom,i2c-qup-v2.2.1";
2590 clock-names = "core", "iface";
2592 dma-names = "tx", "rx";
2593 pinctrl-names = "default", "sleep";
2594 pinctrl-0 = <&blsp2_i2c2_default>;
2595 pinctrl-1 = <&blsp2_i2c2_sleep>;
2596 clock-frequency = <400000>;
2599 #address-cells = <1>;
2600 #size-cells = <0>;
2604 compatible = "qcom,i2c-qup-v2.2.1";
2610 clock-names = "core", "iface";
2612 dma-names = "tx", "rx";
2613 pinctrl-names = "default", "sleep";
2614 pinctrl-0 = <&blsp2_i2c3_default>;
2615 pinctrl-1 = <&blsp2_i2c3_sleep>;
2616 clock-frequency = <400000>;
2619 #address-cells = <1>;
2620 #size-cells = <0>;
2624 compatible = "qcom,i2c-qup-v2.2.1";
2630 clock-names = "core", "iface";
2632 dma-names = "tx", "rx";
2633 pinctrl-names = "default", "sleep";
2634 pinctrl-0 = <&blsp2_i2c4_default>;
2635 pinctrl-1 = <&blsp2_i2c4_sleep>;
2636 clock-frequency = <400000>;
2639 #address-cells = <1>;
2640 #size-cells = <0>;
2644 compatible = "qcom,i2c-qup-v2.2.1";
2650 clock-names = "core", "iface";
2652 dma-names = "tx", "rx";
2653 pinctrl-names = "default", "sleep";
2654 pinctrl-0 = <&blsp2_i2c5_default>;
2655 pinctrl-1 = <&blsp2_i2c5_sleep>;
2656 clock-frequency = <400000>;
2659 #address-cells = <1>;
2660 #size-cells = <0>;
2664 compatible = "qcom,i2c-qup-v2.2.1";
2670 clock-names = "core", "iface";
2672 dma-names = "tx", "rx";
2673 pinctrl-names = "default", "sleep";
2674 pinctrl-0 = <&blsp2_i2c6_default>;
2675 pinctrl-1 = <&blsp2_i2c6_sleep>;
2676 clock-frequency = <400000>;
2679 #address-cells = <1>;
2680 #size-cells = <0>;
2684 compatible = "qcom,spi-qup-v2.2.1";
2690 clock-names = "core", "iface";
2692 dma-names = "tx", "rx";
2693 pinctrl-names = "default";
2694 pinctrl-0 = <&blsp2_spi1_default>;
2697 #address-cells = <1>;
2698 #size-cells = <0>;
2702 compatible = "qcom,spi-qup-v2.2.1";
2708 clock-names = "core", "iface";
2710 dma-names = "tx", "rx";
2711 pinctrl-names = "default";
2712 pinctrl-0 = <&blsp2_spi2_default>;
2715 #address-cells = <1>;
2716 #size-cells = <0>;
2720 compatible = "qcom,spi-qup-v2.2.1";
2726 clock-names = "core", "iface";
2728 dma-names = "tx", "rx";
2729 pinctrl-names = "default";
2730 pinctrl-0 = <&blsp2_spi3_default>;
2733 #address-cells = <1>;
2734 #size-cells = <0>;
2738 compatible = "qcom,spi-qup-v2.2.1";
2744 clock-names = "core", "iface";
2746 dma-names = "tx", "rx";
2747 pinctrl-names = "default";
2748 pinctrl-0 = <&blsp2_spi4_default>;
2751 #address-cells = <1>;
2752 #size-cells = <0>;
2756 compatible = "qcom,spi-qup-v2.2.1";
2762 clock-names = "core", "iface";
2764 dma-names = "tx", "rx";
2765 pinctrl-names = "default";
2766 pinctrl-0 = <&blsp2_spi5_default>;
2769 #address-cells = <1>;
2770 #size-cells = <0>;
2774 compatible = "qcom,spi-qup-v2.2.1";
2780 clock-names = "core", "iface";
2782 dma-names = "tx", "rx";
2783 pinctrl-names = "default";
2784 pinctrl-0 = <&blsp2_spi6_default>;
2787 #address-cells = <1>;
2788 #size-cells = <0>;
2791 mmcc: clock-controller@c8c0000 {
2792 compatible = "qcom,mmcc-msm8998";
2793 #clock-cells = <1>;
2794 #reset-cells = <1>;
2795 #power-domain-cells = <1>;
2798 clock-names = "xo",
2820 mdss: display-subsystem@c900000 {
2821 compatible = "qcom,msm8998-mdss";
2823 reg-names = "mdss";
2826 interrupt-controller;
2827 #interrupt-cells = <1>;
2832 clock-names = "iface",
2836 power-domains = <&mmcc MDSS_GDSC>;
2839 #address-cells = <1>;
2840 #size-cells = <1>;
2845 mdss_mdp: display-controller@c901000 {
2846 compatible = "qcom,msm8998-dpu";
2851 reg-names = "mdp",
2856 interrupt-parent = <&mdss>;
2864 clock-names = "iface",
2870 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2871 assigned-clock-rates = <19200000>;
2873 operating-points-v2 = <&mdp_opp_table>;
2874 power-domains = <&rpmpd MSM8998_VDDMX>;
2876 mdp_opp_table: opp-table {
2877 compatible = "operating-points-v2";
2879 opp-171430000 {
2880 opp-hz = /bits/ 64 <171430000>;
2881 required-opps = <&rpmpd_opp_low_svs>;
2884 opp-275000000 {
2885 opp-hz = /bits/ 64 <275000000>;
2886 required-opps = <&rpmpd_opp_svs>;
2889 opp-330000000 {
2890 opp-hz = /bits/ 64 <330000000>;
2891 required-opps = <&rpmpd_opp_nom>;
2894 opp-412500000 {
2895 opp-hz = /bits/ 64 <412500000>;
2896 required-opps = <&rpmpd_opp_turbo>;
2901 #address-cells = <1>;
2902 #size-cells = <0>;
2908 remote-endpoint = <&mdss_dsi0_in>;
2916 remote-endpoint = <&mdss_dsi1_in>;
2924 remote-endpoint = <&hdmi_in>;
2931 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2933 reg-names = "dsi_ctrl";
2935 interrupt-parent = <&mdss>;
2944 clock-names = "byte",
2950 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2952 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
2955 operating-points-v2 = <&dsi_opp_table>;
2956 power-domains = <&rpmpd MSM8998_VDDCX>;
2959 phy-names = "dsi";
2961 #address-cells = <1>;
2962 #size-cells = <0>;
2967 #address-cells = <1>;
2968 #size-cells = <0>;
2974 remote-endpoint = <&dpu_intf1_out>;
2987 mdss_dsi0_phy: phy@c994400 {
2988 compatible = "qcom,dsi-phy-10nm-8998";
2992 reg-names = "dsi_phy",
2998 clock-names = "iface", "ref";
3000 #clock-cells = <1>;
3001 #phy-cells = <0>;
3007 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3009 reg-names = "dsi_ctrl";
3011 interrupt-parent = <&mdss>;
3020 clock-names = "byte",
3026 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
3028 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
3031 operating-points-v2 = <&dsi_opp_table>;
3032 power-domains = <&rpmpd MSM8998_VDDCX>;
3035 phy-names = "dsi";
3037 #address-cells = <1>;
3038 #size-cells = <0>;
3043 #address-cells = <1>;
3044 #size-cells = <0>;
3050 remote-endpoint = <&dpu_intf2_out>;
3063 mdss_dsi1_phy: phy@c996400 {
3064 compatible = "qcom,dsi-phy-10nm-8998";
3068 reg-names = "dsi_phy",
3074 clock-names = "iface",
3077 #clock-cells = <1>;
3078 #phy-cells = <0>;
3083 mdss_hdmi: hdmi-tx@c9a0000 {
3084 compatible = "qcom,hdmi-tx-8998";
3088 reg-names = "core_physical",
3092 interrupt-parent = <&mdss>;
3103 clock-names =
3114 #sound-dai-cells = <1>;
3116 pinctrl-0 = <&hdmi_hpd_default>,
3119 pinctrl-1 = <&hdmi_hpd_sleep>,
3122 pinctrl-names = "default", "sleep";
3127 #address-cells = <1>;
3128 #size-cells = <0>;
3133 remote-endpoint = <&dpu_intf3_out>;
3145 mdss_hdmi_phy: hdmi-phy@c9a0600 {
3146 compatible = "qcom,hdmi-phy-8998";
3153 reg-names = "hdmi_pll",
3160 #clock-cells = <0>;
3161 #phy-cells = <0>;
3166 clock-names = "iface",
3174 venus: video-codec@cc00000 {
3175 compatible = "qcom,msm8998-venus";
3178 power-domains = <&mmcc VIDEO_TOP_GDSC>;
3183 clock-names = "core", "iface", "bus", "mbus";
3204 memory-region = <&venus_mem>;
3207 video-decoder {
3208 compatible = "venus-decoder";
3210 clock-names = "core";
3211 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3214 video-encoder {
3215 compatible = "venus-encoder";
3217 clock-names = "core";
3218 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3223 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3225 #iommu-cells = <1>;
3230 clock-names = "iface-mm",
3231 "iface-smmu",
3232 "bus-smmu";
3234 #global-interrupts = <0>;
3257 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3261 compatible = "qcom,msm8998-adsp-pas";
3264 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3269 interrupt-names = "wdog", "fatal", "ready",
3270 "handover", "stop-ack";
3273 clock-names = "xo";
3275 memory-region = <&adsp_mem>;
3277 qcom,smem-states = <&adsp_smp2p_out 0>;
3278 qcom,smem-state-names = "stop";
3280 power-domains = <&rpmpd MSM8998_VDDCX>;
3281 power-domain-names = "cx";
3285 glink-edge {
3288 qcom,remote-pid = <2>;
3294 compatible = "qcom,msm8998-apcs-hmss-global",
3295 "qcom,msm8994-apcs-kpss-global";
3298 #mbox-cells = <1>;
3302 #address-cells = <1>;
3303 #size-cells = <1>;
3305 compatible = "arm,armv7-timer-mem";
3309 frame-number = <0>;
3317 frame-number = <1>;
3324 frame-number = <2>;
3331 frame-number = <3>;
3338 frame-number = <4>;
3345 frame-number = <5>;
3352 frame-number = <6>;
3359 intc: interrupt-controller@17a00000 {
3360 compatible = "arm,gic-v3";
3363 #interrupt-cells = <3>;
3364 #address-cells = <1>;
3365 #size-cells = <1>;
3367 interrupt-controller;
3368 #redistributor-regions = <1>;
3369 redistributor-stride = <0x0 0x20000>;
3374 compatible = "qcom,wcn3990-wifi";
3377 reg-names = "membase";
3378 memory-region = <&wlan_msa_mem>;
3380 clock-names = "cxo_ref_clk_pin";
3396 qcom,snoc-host-cap-8bit-quirk;
3397 qcom,no-msa-ready-indicator;