Lines Matching full:gcc
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
818 gcc: clock-controller@100000 { label
819 compatible = "qcom,gcc-msm8998";
946 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCIE_0_AUX_CLK>,
948 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
953 power-domains = <&gcc PCIE_0_GDSC>;
973 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCIE_CLKREF_CLK>,
976 <&gcc GCC_PCIE_0_PIPE_CLK>;
987 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
1001 power-domains = <&gcc UFS_GDSC>;
1015 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1020 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1033 resets = <&gcc GCC_UFS_BCR>;
1042 <&gcc GCC_UFS_PHY_AUX_CLK>,
1043 <&gcc GCC_UFS_CLKREF_CLK>;
1464 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1465 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1466 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1467 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1468 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1469 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1478 resets = <&gcc GCC_MSS_RESTART>;
1514 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1516 <&gcc GCC_BIMC_GFX_CLK>,
1517 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1582 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1583 <&gcc GCC_BIMC_GFX_CLK>,
1584 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1612 <&gcc GCC_GPU_GPLL0_CLK>;
1620 clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1640 power-domains = <&gcc LPASS_ADSP_GDSC>;
2170 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2171 <&gcc GCC_USB30_MASTER_CLK>,
2172 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2173 <&gcc GCC_USB30_SLEEP_CLK>,
2174 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2181 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2182 <&gcc GCC_USB30_MASTER_CLK>;
2192 power-domains = <&gcc USB_30_GDSC>;
2194 resets = <&gcc GCC_USB_30_BCR>;
2214 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2215 <&gcc GCC_USB3_CLKREF_CLK>,
2216 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2217 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2226 resets = <&gcc GCC_USB3_PHY_BCR>,
2227 <&gcc GCC_USB3PHY_PHY_BCR>;
2242 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2243 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2246 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2261 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2262 <&gcc GCC_SDCC2_APPS_CLK>,
2272 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2285 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2286 <&gcc GCC_BLSP1_AHB_CLK>;
2300 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2301 <&gcc GCC_BLSP1_AHB_CLK>;
2320 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2321 <&gcc GCC_BLSP1_AHB_CLK>;
2340 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2341 <&gcc GCC_BLSP1_AHB_CLK>;
2360 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2361 <&gcc GCC_BLSP1_AHB_CLK>;
2380 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2381 <&gcc GCC_BLSP1_AHB_CLK>;
2400 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2401 <&gcc GCC_BLSP1_AHB_CLK>;
2420 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2421 <&gcc GCC_BLSP1_AHB_CLK>;
2438 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2439 <&gcc GCC_BLSP1_AHB_CLK>;
2456 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2457 <&gcc GCC_BLSP1_AHB_CLK>;
2474 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2475 <&gcc GCC_BLSP1_AHB_CLK>;
2492 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2493 <&gcc GCC_BLSP1_AHB_CLK>;
2510 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2511 <&gcc GCC_BLSP1_AHB_CLK>;
2527 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2540 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2541 <&gcc GCC_BLSP2_AHB_CLK>;
2551 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2552 <&gcc GCC_BLSP2_AHB_CLK>;
2571 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2572 <&gcc GCC_BLSP2_AHB_CLK>;
2591 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2592 <&gcc GCC_BLSP2_AHB_CLK>;
2611 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2612 <&gcc GCC_BLSP2_AHB_CLK>;
2631 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2632 <&gcc GCC_BLSP2_AHB_CLK>;
2651 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2652 <&gcc GCC_BLSP2_AHB_CLK>;
2671 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2672 <&gcc GCC_BLSP2_AHB_CLK>;
2689 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2690 <&gcc GCC_BLSP2_AHB_CLK>;
2707 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2708 <&gcc GCC_BLSP2_AHB_CLK>;
2725 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2726 <&gcc GCC_BLSP2_AHB_CLK>;
2743 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2744 <&gcc GCC_BLSP2_AHB_CLK>;
2761 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2762 <&gcc GCC_BLSP2_AHB_CLK>;
2792 <&gcc GCC_MMSS_GPLL0_CLK>,
2800 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
3147 <&gcc GCC_HDMI_CLKREF_CLK>,