Lines Matching +full:0 +full:xf1d
17 qcom,msm-id = <292 0x0>;
27 reg = <0x0 0x80000000 0x0 0x0>;
36 reg = <0x0 0x85800000 0x0 0x600000>;
41 reg = <0x0 0x85e00000 0x0 0x100000>;
46 reg = <0x0 0x86000000 0x0 0x200000>;
51 reg = <0x0 0x86200000 0x0 0x2d00000>;
57 reg = <0x0 0x88f00000 0x0 0x200000>;
65 reg = <0x0 0x8ab00000 0x0 0x700000>;
70 reg = <0x0 0x8b200000 0x0 0x1a00000>;
75 reg = <0x0 0x8cc00000 0x0 0x7000000>;
80 reg = <0x0 0x93c00000 0x0 0x500000>;
85 reg = <0x0 0x94100000 0x0 0x200000>;
90 reg = <0x0 0x94300000 0x0 0xf00000>;
95 reg = <0x0 0x95200000 0x0 0x10000>;
100 reg = <0x0 0x95210000 0x0 0x5000>;
105 reg = <0x0 0x95600000 0x0 0x100000>;
110 reg = <0x0 0x95700000 0x0 0x100000>;
115 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
116 size = <0x0 0x4000>;
124 #clock-cells = <0>;
131 #clock-cells = <0>;
138 #size-cells = <0>;
140 cpu0: cpu@0 {
143 reg = <0x0 0x0>;
158 reg = <0x0 0x1>;
168 reg = <0x0 0x2>;
178 reg = <0x0 0x3>;
188 reg = <0x0 0x100>;
203 reg = <0x0 0x101>;
213 reg = <0x0 0x102>;
223 reg = <0x0 0x103>;
271 little_cpu_sleep_0: cpu-sleep-0-0 {
275 arm,psci-suspend-param = <0x00000002>;
281 little_cpu_sleep_1: cpu-sleep-0-1 {
285 arm,psci-suspend-param = <0x40000003>;
292 big_cpu_sleep_0: cpu-sleep-1-0 {
296 arm,psci-suspend-param = <0x00000002>;
306 arm,psci-suspend-param = <0x40000003>;
353 mboxes = <&apcs_glb 0>;
433 qcom,local-pid = <0>;
454 qcom,local-pid = <0>;
474 qcom,local-pid = <0>;
810 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
813 soc: soc@0 {
816 ranges = <0 0 0 0xffffffff>;
824 reg = <0x00100000 0xb0000>;
847 reg = <0x00778000 0x7000>;
852 reg = <0x00784000 0x621c>;
857 reg = <0x23a 0x1>;
858 bits = <0 4>;
864 reg = <0x010ab000 0x1000>, /* TM */
865 <0x010aa000 0x1000>; /* SROT */
875 reg = <0x010ae000 0x1000>, /* TM */
876 <0x010ad000 0x1000>; /* SROT */
886 reg = <0x01680000 0x10000>;
889 #global-interrupts = <0>;
901 reg = <0x016c0000 0x40000>;
904 #global-interrupts = <0>;
920 reg = <0x01c00000 0x2000>,
921 <0x1b000000 0xf1d>,
922 <0x1b000f20 0xa8>,
923 <0x1b100000 0x100000>;
926 linux,pci-domain = <0>;
927 bus-range = <0x00 0xff>;
935 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
936 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
957 interrupt-map-mask = <0 0 0 0x7>;
958 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
959 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
960 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
961 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
971 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
974 pcie@0 {
976 reg = <0x0 0x0 0x0 0x0 0x0>;
977 bus-range = <0x01 0xff>;
987 reg = <0x01c06000 0x1000>;
1000 #clock-cells = <0>;
1002 #phy-cells = <0>;
1013 reg = <0x01da4000 0x2500>;
1042 <0 0>,
1043 <0 0>,
1045 <0 0>,
1046 <0 0>,
1047 <0 0>,
1048 <0 0>;
1056 reg = <0x01da7000 0x1000>;
1066 resets = <&ufshc 0>;
1068 #phy-cells = <0>;
1074 reg = <0x01f40000 0x20000>;
1080 reg = <0x01f60000 0x20000>;
1085 reg = <0x01fc0000 0x26000>;
1090 reg = <0x03400000 0xc00000>;
1092 gpio-ranges = <&tlmm 0 0 150>;
1467 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1472 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1492 qcom,smem-states = <&modem_smp2p_out 0>;
1498 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1528 reg = <0x05000000 0x40000>;
1545 iommus = <&adreno_smmu 0>;
1555 opp-supported-hw = <0xff>;
1561 opp-supported-hw = <0xff>;
1567 opp-supported-hw = <0xff>;
1573 opp-supported-hw = <0xff>;
1579 opp-supported-hw = <0xff>;
1585 opp-supported-hw = <0xff>;
1591 opp-supported-hw = <0xff>;
1598 reg = <0x05040000 0x10000>;
1604 #global-interrupts = <0>;
1626 reg = <0x05065000 0x9000>;
1636 reg = <0x05100000 0x40000>;
1640 #global-interrupts = <0>;
1663 reg = <0x05800000 0x4040>;
1666 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1680 qcom,smem-states = <&slpi_smp2p_out 0>;
1698 reg = <0x06002000 0x1000>,
1699 <0x16280000 0x180000>;
1717 reg = <0x06041000 0x1000>;
1734 #size-cells = <0>;
1747 reg = <0x06042000 0x1000>;
1764 #size-cells = <0>;
1778 reg = <0x06045000 0x1000>;
1795 #size-cells = <0>;
1797 port@0 {
1798 reg = <0>;
1817 reg = <0x06046000 0x1000>;
1842 reg = <0x06047000 0x1000>;
1869 reg = <0x06048000 0x1000>;
1888 reg = <0x07840000 0x1000>;
1908 reg = <0x07940000 0x1000>;
1928 reg = <0x07a40000 0x1000>;
1948 reg = <0x07b40000 0x1000>;
1968 reg = <0x07b60000 0x1000>;
1985 #size-cells = <0>;
1987 port@0 {
1988 reg = <0>;
2055 reg = <0x07b70000 0x1000>;
2082 reg = <0x07c40000 0x1000>;
2101 reg = <0x07d40000 0x1000>;
2120 reg = <0x07e40000 0x1000>;
2139 reg = <0x07f40000 0x1000>;
2158 reg = <0x00290000 0x10000>;
2163 reg = <0x0800f000 0x1000>,
2164 <0x08400000 0x1000000>,
2165 <0x09400000 0x1000000>,
2166 <0x0a400000 0x220000>,
2167 <0x0800a000 0x3000>;
2171 qcom,ee = <0>;
2172 qcom,channel = <0>;
2174 #size-cells = <0>;
2181 reg = <0x0a8f8800 0x400>;
2215 reg = <0x0a800000 0xcd00>;
2223 snps,hird-threshold = /bits/ 8 <0x10>;
2229 reg = <0x0c010000 0x1000>;
2240 #clock-cells = <0>;
2241 #phy-cells = <0>;
2248 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2255 reg = <0x0c012000 0x2a8>;
2257 #phy-cells = <0>;
2270 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2287 reg = <0x0c144000 0x25000>;
2292 qcom,ee = <0>;
2300 reg = <0x0c171000 0x1000>;
2308 pinctrl-0 = <&blsp1_uart3_on>;
2314 reg = <0x0c175000 0x600>;
2323 pinctrl-0 = <&blsp1_i2c1_default>;
2329 #size-cells = <0>;
2334 reg = <0x0c176000 0x600>;
2343 pinctrl-0 = <&blsp1_i2c2_default>;
2349 #size-cells = <0>;
2354 reg = <0x0c177000 0x600>;
2363 pinctrl-0 = <&blsp1_i2c3_default>;
2369 #size-cells = <0>;
2374 reg = <0x0c178000 0x600>;
2383 pinctrl-0 = <&blsp1_i2c4_default>;
2389 #size-cells = <0>;
2394 reg = <0x0c179000 0x600>;
2403 pinctrl-0 = <&blsp1_i2c5_default>;
2409 #size-cells = <0>;
2414 reg = <0x0c17a000 0x600>;
2423 pinctrl-0 = <&blsp1_i2c6_default>;
2429 #size-cells = <0>;
2434 reg = <0x0c175000 0x600>;
2443 pinctrl-0 = <&blsp1_spi1_default>;
2447 #size-cells = <0>;
2452 reg = <0x0c176000 0x600>;
2461 pinctrl-0 = <&blsp1_spi2_default>;
2465 #size-cells = <0>;
2470 reg = <0x0c177000 0x600>;
2479 pinctrl-0 = <&blsp1_spi3_default>;
2483 #size-cells = <0>;
2488 reg = <0x0c178000 0x600>;
2497 pinctrl-0 = <&blsp1_spi4_default>;
2501 #size-cells = <0>;
2506 reg = <0x0c179000 0x600>;
2515 pinctrl-0 = <&blsp1_spi5_default>;
2519 #size-cells = <0>;
2524 reg = <0x0c17a000 0x600>;
2533 pinctrl-0 = <&blsp1_spi6_default>;
2537 #size-cells = <0>;
2542 reg = <0x0c184000 0x25000>;
2547 qcom,ee = <0>;
2555 reg = <0x0c1b0000 0x1000>;
2565 reg = <0x0c1b5000 0x600>;
2574 pinctrl-0 = <&blsp2_i2c1_default>;
2580 #size-cells = <0>;
2585 reg = <0x0c1b6000 0x600>;
2594 pinctrl-0 = <&blsp2_i2c2_default>;
2600 #size-cells = <0>;
2605 reg = <0x0c1b7000 0x600>;
2614 pinctrl-0 = <&blsp2_i2c3_default>;
2620 #size-cells = <0>;
2625 reg = <0x0c1b8000 0x600>;
2634 pinctrl-0 = <&blsp2_i2c4_default>;
2640 #size-cells = <0>;
2645 reg = <0x0c1b9000 0x600>;
2654 pinctrl-0 = <&blsp2_i2c5_default>;
2660 #size-cells = <0>;
2665 reg = <0x0c1ba000 0x600>;
2674 pinctrl-0 = <&blsp2_i2c6_default>;
2680 #size-cells = <0>;
2685 reg = <0x0c1b5000 0x600>;
2694 pinctrl-0 = <&blsp2_spi1_default>;
2698 #size-cells = <0>;
2703 reg = <0x0c1b6000 0x600>;
2712 pinctrl-0 = <&blsp2_spi2_default>;
2716 #size-cells = <0>;
2721 reg = <0x0c1b7000 0x600>;
2730 pinctrl-0 = <&blsp2_spi3_default>;
2734 #size-cells = <0>;
2739 reg = <0x0c1b8000 0x600>;
2748 pinctrl-0 = <&blsp2_spi4_default>;
2752 #size-cells = <0>;
2757 reg = <0x0c1b9000 0x600>;
2766 pinctrl-0 = <&blsp2_spi5_default>;
2770 #size-cells = <0>;
2775 reg = <0x0c1ba000 0x600>;
2784 pinctrl-0 = <&blsp2_spi6_default>;
2788 #size-cells = <0>;
2796 reg = <0xc8c0000 0x40000>;
2815 <0>,
2816 <0>,
2822 reg = <0x0c900000 0x1000>;
2837 iommus = <&mmss_smmu 0>;
2847 reg = <0x0c901000 0x8f000>,
2848 <0x0c9a8e00 0xf0>,
2849 <0x0c9b0000 0x3000>,
2850 <0x0c9b8000 0x3000>;
2857 interrupts = <0>;
2902 #size-cells = <0>;
2904 port@0 {
2905 reg = <0>;
2932 reg = <0x0c994000 0x400>;
2962 #size-cells = <0>;
2968 #size-cells = <0>;
2970 port@0 {
2971 reg = <0>;
2989 reg = <0x0c994400 0x200>,
2990 <0x0c994600 0x280>,
2991 <0x0c994a00 0x1e0>;
3001 #phy-cells = <0>;
3008 reg = <0x0c996000 0x400>;
3038 #size-cells = <0>;
3044 #size-cells = <0>;
3046 port@0 {
3047 reg = <0>;
3065 reg = <0x0c996400 0x200>,
3066 <0x0c996600 0x280>,
3067 <0x0c996a00 0x10e>;
3078 #phy-cells = <0>;
3085 reg = <0x0c9a0000 0x50c>,
3086 <0x00780000 0x6220>,
3087 <0x0c9e0000 0x2c>;
3116 pinctrl-0 = <&hdmi_hpd_default>,
3128 #size-cells = <0>;
3130 port@0 {
3131 reg = <0>;
3147 reg = <0x0c9a0600 0x18b>,
3148 <0x0c9a0a00 0x38>,
3149 <0x0c9a0c00 0x38>,
3150 <0x0c9a0e00 0x38>,
3151 <0x0c9a1000 0x38>,
3152 <0x0c9a1200 0x0e8>;
3160 #clock-cells = <0>;
3161 #phy-cells = <0>;
3176 reg = <0x0cc00000 0xff000>;
3184 iommus = <&mmss_smmu 0x400>,
3185 <&mmss_smmu 0x401>,
3186 <&mmss_smmu 0x40a>,
3187 <&mmss_smmu 0x407>,
3188 <&mmss_smmu 0x40e>,
3189 <&mmss_smmu 0x40f>,
3190 <&mmss_smmu 0x408>,
3191 <&mmss_smmu 0x409>,
3192 <&mmss_smmu 0x40b>,
3193 <&mmss_smmu 0x40c>,
3194 <&mmss_smmu 0x40d>,
3195 <&mmss_smmu 0x410>,
3196 <&mmss_smmu 0x421>,
3197 <&mmss_smmu 0x428>,
3198 <&mmss_smmu 0x429>,
3199 <&mmss_smmu 0x42b>,
3200 <&mmss_smmu 0x42c>,
3201 <&mmss_smmu 0x42d>,
3202 <&mmss_smmu 0x411>,
3203 <&mmss_smmu 0x431>;
3224 reg = <0x0cd00000 0x40000>;
3234 #global-interrupts = <0>;
3262 reg = <0x17300000 0x4040>;
3265 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3277 qcom,smem-states = <&adsp_smp2p_out 0>;
3296 reg = <0x17911000 0x1000>;
3306 reg = <0x17920000 0x1000>;
3309 frame-number = <0>;
3312 reg = <0x17921000 0x1000>,
3313 <0x17922000 0x1000>;
3319 reg = <0x17923000 0x1000>;
3326 reg = <0x17924000 0x1000>;
3333 reg = <0x17925000 0x1000>;
3340 reg = <0x17926000 0x1000>;
3347 reg = <0x17927000 0x1000>;
3354 reg = <0x17928000 0x1000>;
3361 reg = <0x17a00000 0x10000>, /* GICD */
3362 <0x17b00000 0x100000>; /* GICR * 8 */
3369 redistributor-stride = <0x0 0x20000>;
3376 reg = <0x18800000 0x800000>;
3394 iommus = <&anoc2_smmu 0x1900>,
3395 <&anoc2_smmu 0x1901>;