Lines Matching +full:0 +full:x429
16 qcom,msm-id = <292 0x0>;
26 reg = <0x0 0x80000000 0x0 0x0>;
35 reg = <0x0 0x85800000 0x0 0x600000>;
40 reg = <0x0 0x85e00000 0x0 0x100000>;
45 reg = <0x0 0x86000000 0x0 0x200000>;
50 reg = <0x0 0x86200000 0x0 0x2d00000>;
56 reg = <0x0 0x88f00000 0x0 0x200000>;
64 reg = <0x0 0x8ab00000 0x0 0x700000>;
69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
79 reg = <0x0 0x93c00000 0x0 0x500000>;
84 reg = <0x0 0x94100000 0x0 0x200000>;
89 reg = <0x0 0x94300000 0x0 0xf00000>;
94 reg = <0x0 0x95200000 0x0 0x10000>;
99 reg = <0x0 0x95210000 0x0 0x5000>;
104 reg = <0x0 0x95600000 0x0 0x100000>;
109 reg = <0x0 0x95700000 0x0 0x100000>;
114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 size = <0x0 0x4000>;
123 #clock-cells = <0>;
130 #clock-cells = <0>;
137 #size-cells = <0>;
139 CPU0: cpu@0 {
142 reg = <0x0 0x0>;
157 reg = <0x0 0x1>;
167 reg = <0x0 0x2>;
177 reg = <0x0 0x3>;
187 reg = <0x0 0x100>;
202 reg = <0x0 0x101>;
212 reg = <0x0 0x102>;
222 reg = <0x0 0x103>;
270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
274 arm,psci-suspend-param = <0x00000002>;
280 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
284 arm,psci-suspend-param = <0x40000003>;
291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
295 arm,psci-suspend-param = <0x00000002>;
305 arm,psci-suspend-param = <0x40000003>;
352 mboxes = <&apcs_glb 0>;
432 qcom,local-pid = <0>;
453 qcom,local-pid = <0>;
473 qcom,local-pid = <0>;
809 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
812 soc: soc@0 {
815 ranges = <0 0 0 0xffffffff>;
823 reg = <0x00100000 0xb0000>;
846 reg = <0x00778000 0x7000>;
851 reg = <0x00784000 0x621c>;
856 reg = <0x23a 0x1>;
857 bits = <0 4>;
863 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x1000>; /* SROT */
874 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x1000>; /* SROT */
885 reg = <0x01680000 0x10000>;
888 #global-interrupts = <0>;
900 reg = <0x016c0000 0x40000>;
903 #global-interrupts = <0>;
919 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8>,
922 <0x1b100000 0x100000>;
925 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff>;
934 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
940 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
954 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
957 pcie@0 {
959 reg = <0x0 0x0 0x0 0x0 0x0>;
960 bus-range = <0x01 0xff>;
970 reg = <0x01c06000 0x1000>;
983 #clock-cells = <0>;
985 #phy-cells = <0>;
996 reg = <0x01da4000 0x2500>;
1025 <0 0>,
1026 <0 0>,
1028 <0 0>,
1029 <0 0>,
1030 <0 0>,
1031 <0 0>;
1039 reg = <0x01da7000 0x1000>;
1049 resets = <&ufshc 0>;
1051 #phy-cells = <0>;
1057 reg = <0x01f40000 0x20000>;
1063 reg = <0x01f60000 0x20000>;
1068 reg = <0x01fc0000 0x26000>;
1073 reg = <0x03400000 0xc00000>;
1075 gpio-ranges = <&tlmm 0 0 150>;
1422 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1427 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1447 qcom,smem-states = <&modem_smp2p_out 0>;
1453 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1483 reg = <0x05000000 0x40000>;
1500 iommus = <&adreno_smmu 0>;
1510 opp-supported-hw = <0xff>;
1516 opp-supported-hw = <0xff>;
1522 opp-supported-hw = <0xff>;
1528 opp-supported-hw = <0xff>;
1534 opp-supported-hw = <0xff>;
1540 opp-supported-hw = <0xff>;
1546 opp-supported-hw = <0xff>;
1553 reg = <0x05040000 0x10000>;
1559 #global-interrupts = <0>;
1581 reg = <0x05065000 0x9000>;
1591 reg = <0x05100000 0x40000>;
1595 #global-interrupts = <0>;
1618 reg = <0x05800000 0x4040>;
1621 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1635 qcom,smem-states = <&slpi_smp2p_out 0>;
1653 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x180000>;
1672 reg = <0x06041000 0x1000>;
1689 #size-cells = <0>;
1702 reg = <0x06042000 0x1000>;
1719 #size-cells = <0>;
1733 reg = <0x06045000 0x1000>;
1750 #size-cells = <0>;
1752 port@0 {
1753 reg = <0>;
1772 reg = <0x06046000 0x1000>;
1797 reg = <0x06047000 0x1000>;
1824 reg = <0x06048000 0x1000>;
1843 reg = <0x07840000 0x1000>;
1863 reg = <0x07940000 0x1000>;
1883 reg = <0x07a40000 0x1000>;
1903 reg = <0x07b40000 0x1000>;
1923 reg = <0x07b60000 0x1000>;
1940 #size-cells = <0>;
1942 port@0 {
1943 reg = <0>;
2010 reg = <0x07b70000 0x1000>;
2037 reg = <0x07c40000 0x1000>;
2056 reg = <0x07d40000 0x1000>;
2075 reg = <0x07e40000 0x1000>;
2094 reg = <0x07f40000 0x1000>;
2113 reg = <0x00290000 0x10000>;
2118 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1000000>,
2120 <0x09400000 0x1000000>,
2121 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3000>;
2126 qcom,ee = <0>;
2127 qcom,channel = <0>;
2129 #size-cells = <0>;
2136 reg = <0x0a8f8800 0x400>;
2170 reg = <0x0a800000 0xcd00>;
2178 snps,hird-threshold = /bits/ 8 <0x10>;
2184 reg = <0x0c010000 0x1000>;
2195 #clock-cells = <0>;
2196 #phy-cells = <0>;
2203 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2210 reg = <0x0c012000 0x2a8>;
2212 #phy-cells = <0>;
2225 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2242 reg = <0x0c144000 0x25000>;
2247 qcom,ee = <0>;
2255 reg = <0x0c171000 0x1000>;
2263 pinctrl-0 = <&blsp1_uart3_on>;
2269 reg = <0x0c175000 0x600>;
2278 pinctrl-0 = <&blsp1_i2c1_default>;
2284 #size-cells = <0>;
2289 reg = <0x0c176000 0x600>;
2298 pinctrl-0 = <&blsp1_i2c2_default>;
2304 #size-cells = <0>;
2309 reg = <0x0c177000 0x600>;
2318 pinctrl-0 = <&blsp1_i2c3_default>;
2324 #size-cells = <0>;
2329 reg = <0x0c178000 0x600>;
2338 pinctrl-0 = <&blsp1_i2c4_default>;
2344 #size-cells = <0>;
2349 reg = <0x0c179000 0x600>;
2358 pinctrl-0 = <&blsp1_i2c5_default>;
2364 #size-cells = <0>;
2369 reg = <0x0c17a000 0x600>;
2378 pinctrl-0 = <&blsp1_i2c6_default>;
2384 #size-cells = <0>;
2389 reg = <0x0c175000 0x600>;
2398 pinctrl-0 = <&blsp1_spi1_default>;
2402 #size-cells = <0>;
2407 reg = <0x0c176000 0x600>;
2416 pinctrl-0 = <&blsp1_spi2_default>;
2420 #size-cells = <0>;
2425 reg = <0x0c177000 0x600>;
2434 pinctrl-0 = <&blsp1_spi3_default>;
2438 #size-cells = <0>;
2443 reg = <0x0c178000 0x600>;
2452 pinctrl-0 = <&blsp1_spi4_default>;
2456 #size-cells = <0>;
2461 reg = <0x0c179000 0x600>;
2470 pinctrl-0 = <&blsp1_spi5_default>;
2474 #size-cells = <0>;
2479 reg = <0x0c17a000 0x600>;
2488 pinctrl-0 = <&blsp1_spi6_default>;
2492 #size-cells = <0>;
2497 reg = <0x0c184000 0x25000>;
2502 qcom,ee = <0>;
2510 reg = <0x0c1b0000 0x1000>;
2520 reg = <0x0c1b5000 0x600>;
2529 pinctrl-0 = <&blsp2_i2c1_default>;
2535 #size-cells = <0>;
2540 reg = <0x0c1b6000 0x600>;
2549 pinctrl-0 = <&blsp2_i2c2_default>;
2555 #size-cells = <0>;
2560 reg = <0x0c1b7000 0x600>;
2569 pinctrl-0 = <&blsp2_i2c3_default>;
2575 #size-cells = <0>;
2580 reg = <0x0c1b8000 0x600>;
2589 pinctrl-0 = <&blsp2_i2c4_default>;
2595 #size-cells = <0>;
2600 reg = <0x0c1b9000 0x600>;
2609 pinctrl-0 = <&blsp2_i2c5_default>;
2615 #size-cells = <0>;
2620 reg = <0x0c1ba000 0x600>;
2629 pinctrl-0 = <&blsp2_i2c6_default>;
2635 #size-cells = <0>;
2640 reg = <0x0c1b5000 0x600>;
2649 pinctrl-0 = <&blsp2_spi1_default>;
2653 #size-cells = <0>;
2658 reg = <0x0c1b6000 0x600>;
2667 pinctrl-0 = <&blsp2_spi2_default>;
2671 #size-cells = <0>;
2676 reg = <0x0c1b7000 0x600>;
2685 pinctrl-0 = <&blsp2_spi3_default>;
2689 #size-cells = <0>;
2694 reg = <0x0c1b8000 0x600>;
2703 pinctrl-0 = <&blsp2_spi4_default>;
2707 #size-cells = <0>;
2712 reg = <0x0c1b9000 0x600>;
2721 pinctrl-0 = <&blsp2_spi5_default>;
2725 #size-cells = <0>;
2730 reg = <0x0c1ba000 0x600>;
2739 pinctrl-0 = <&blsp2_spi6_default>;
2743 #size-cells = <0>;
2751 reg = <0xc8c0000 0x40000>;
2766 <&mdss_dsi0_phy 0>,
2768 <&mdss_dsi1_phy 0>,
2769 <0>,
2770 <0>,
2771 <0>,
2777 reg = <0x0c900000 0x1000>;
2792 iommus = <&mmss_smmu 0>;
2802 reg = <0x0c901000 0x8f000>,
2803 <0x0c9a8e00 0xf0>,
2804 <0x0c9b0000 0x2008>,
2805 <0x0c9b8000 0x1040>;
2812 interrupts = <0>;
2857 #size-cells = <0>;
2859 port@0 {
2860 reg = <0>;
2879 reg = <0x0c994000 0x400>;
2899 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2909 #size-cells = <0>;
2915 #size-cells = <0>;
2917 port@0 {
2918 reg = <0>;
2936 reg = <0x0c994400 0x200>,
2937 <0x0c994600 0x280>,
2938 <0x0c994a00 0x1e0>;
2948 #phy-cells = <0>;
2955 reg = <0x0c996000 0x400>;
2975 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2985 #size-cells = <0>;
2991 #size-cells = <0>;
2993 port@0 {
2994 reg = <0>;
3012 reg = <0x0c996400 0x200>,
3013 <0x0c996600 0x280>,
3014 <0x0c996a00 0x10e>;
3025 #phy-cells = <0>;
3033 reg = <0x0cc00000 0xff000>;
3041 iommus = <&mmss_smmu 0x400>,
3042 <&mmss_smmu 0x401>,
3043 <&mmss_smmu 0x40a>,
3044 <&mmss_smmu 0x407>,
3045 <&mmss_smmu 0x40e>,
3046 <&mmss_smmu 0x40f>,
3047 <&mmss_smmu 0x408>,
3048 <&mmss_smmu 0x409>,
3049 <&mmss_smmu 0x40b>,
3050 <&mmss_smmu 0x40c>,
3051 <&mmss_smmu 0x40d>,
3052 <&mmss_smmu 0x410>,
3053 <&mmss_smmu 0x421>,
3054 <&mmss_smmu 0x428>,
3055 <&mmss_smmu 0x429>,
3056 <&mmss_smmu 0x42b>,
3057 <&mmss_smmu 0x42c>,
3058 <&mmss_smmu 0x42d>,
3059 <&mmss_smmu 0x411>,
3060 <&mmss_smmu 0x431>;
3081 reg = <0x0cd00000 0x40000>;
3091 #global-interrupts = <0>;
3119 reg = <0x17300000 0x4040>;
3122 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3134 qcom,smem-states = <&adsp_smp2p_out 0>;
3153 reg = <0x17911000 0x1000>;
3163 reg = <0x17920000 0x1000>;
3166 frame-number = <0>;
3169 reg = <0x17921000 0x1000>,
3170 <0x17922000 0x1000>;
3176 reg = <0x17923000 0x1000>;
3183 reg = <0x17924000 0x1000>;
3190 reg = <0x17925000 0x1000>;
3197 reg = <0x17926000 0x1000>;
3204 reg = <0x17927000 0x1000>;
3211 reg = <0x17928000 0x1000>;
3218 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x100000>; /* GICR * 8 */
3226 redistributor-stride = <0x0 0x20000>;
3233 reg = <0x18800000 0x800000>;
3251 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 0x1901>;