Lines Matching +full:0 +full:x0c175000
16 qcom,msm-id = <292 0x0>;
26 reg = <0x0 0x80000000 0x0 0x0>;
35 reg = <0x0 0x85800000 0x0 0x600000>;
40 reg = <0x0 0x85e00000 0x0 0x100000>;
45 reg = <0x0 0x86000000 0x0 0x200000>;
50 reg = <0x0 0x86200000 0x0 0x2d00000>;
56 reg = <0x0 0x88f00000 0x0 0x200000>;
64 reg = <0x0 0x8ab00000 0x0 0x700000>;
69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
79 reg = <0x0 0x93c00000 0x0 0x500000>;
84 reg = <0x0 0x94100000 0x0 0x200000>;
89 reg = <0x0 0x94300000 0x0 0xf00000>;
94 reg = <0x0 0x95200000 0x0 0x10000>;
99 reg = <0x0 0x95210000 0x0 0x5000>;
104 reg = <0x0 0x95600000 0x0 0x100000>;
109 reg = <0x0 0x95700000 0x0 0x100000>;
114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 size = <0x0 0x4000>;
123 #clock-cells = <0>;
130 #clock-cells = <0>;
137 #size-cells = <0>;
139 cpu0: cpu@0 {
142 reg = <0x0 0x0>;
157 reg = <0x0 0x1>;
167 reg = <0x0 0x2>;
177 reg = <0x0 0x3>;
187 reg = <0x0 0x100>;
202 reg = <0x0 0x101>;
212 reg = <0x0 0x102>;
222 reg = <0x0 0x103>;
270 little_cpu_sleep_0: cpu-sleep-0-0 {
274 arm,psci-suspend-param = <0x00000002>;
280 little_cpu_sleep_1: cpu-sleep-0-1 {
284 arm,psci-suspend-param = <0x40000003>;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
295 arm,psci-suspend-param = <0x00000002>;
305 arm,psci-suspend-param = <0x40000003>;
352 mboxes = <&apcs_glb 0>;
432 qcom,local-pid = <0>;
453 qcom,local-pid = <0>;
473 qcom,local-pid = <0>;
809 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
812 soc: soc@0 {
815 ranges = <0 0 0 0xffffffff>;
823 reg = <0x00100000 0xb0000>;
846 reg = <0x00778000 0x7000>;
851 reg = <0x00784000 0x621c>;
856 reg = <0x23a 0x1>;
857 bits = <0 4>;
863 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x1000>; /* SROT */
874 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x1000>; /* SROT */
885 reg = <0x01680000 0x10000>;
888 #global-interrupts = <0>;
900 reg = <0x016c0000 0x40000>;
903 #global-interrupts = <0>;
919 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8>,
922 <0x1b100000 0x100000>;
925 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff>;
934 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
940 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
954 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
957 pcie@0 {
959 reg = <0x0 0x0 0x0 0x0 0x0>;
960 bus-range = <0x01 0xff>;
970 reg = <0x01c06000 0x1000>;
983 #clock-cells = <0>;
985 #phy-cells = <0>;
996 reg = <0x01da4000 0x2500>;
1025 <0 0>,
1026 <0 0>,
1028 <0 0>,
1029 <0 0>,
1030 <0 0>,
1031 <0 0>;
1039 reg = <0x01da7000 0x1000>;
1049 resets = <&ufshc 0>;
1051 #phy-cells = <0>;
1057 reg = <0x01f40000 0x20000>;
1063 reg = <0x01f60000 0x20000>;
1068 reg = <0x01fc0000 0x26000>;
1073 reg = <0x03400000 0xc00000>;
1075 gpio-ranges = <&tlmm 0 0 150>;
1450 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1455 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1475 qcom,smem-states = <&modem_smp2p_out 0>;
1481 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1511 reg = <0x05000000 0x40000>;
1528 iommus = <&adreno_smmu 0>;
1538 opp-supported-hw = <0xff>;
1544 opp-supported-hw = <0xff>;
1550 opp-supported-hw = <0xff>;
1556 opp-supported-hw = <0xff>;
1562 opp-supported-hw = <0xff>;
1568 opp-supported-hw = <0xff>;
1574 opp-supported-hw = <0xff>;
1581 reg = <0x05040000 0x10000>;
1587 #global-interrupts = <0>;
1609 reg = <0x05065000 0x9000>;
1619 reg = <0x05100000 0x40000>;
1623 #global-interrupts = <0>;
1646 reg = <0x05800000 0x4040>;
1649 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1663 qcom,smem-states = <&slpi_smp2p_out 0>;
1681 reg = <0x06002000 0x1000>,
1682 <0x16280000 0x180000>;
1700 reg = <0x06041000 0x1000>;
1717 #size-cells = <0>;
1730 reg = <0x06042000 0x1000>;
1747 #size-cells = <0>;
1761 reg = <0x06045000 0x1000>;
1778 #size-cells = <0>;
1780 port@0 {
1781 reg = <0>;
1800 reg = <0x06046000 0x1000>;
1825 reg = <0x06047000 0x1000>;
1852 reg = <0x06048000 0x1000>;
1871 reg = <0x07840000 0x1000>;
1891 reg = <0x07940000 0x1000>;
1911 reg = <0x07a40000 0x1000>;
1931 reg = <0x07b40000 0x1000>;
1951 reg = <0x07b60000 0x1000>;
1968 #size-cells = <0>;
1970 port@0 {
1971 reg = <0>;
2038 reg = <0x07b70000 0x1000>;
2065 reg = <0x07c40000 0x1000>;
2084 reg = <0x07d40000 0x1000>;
2103 reg = <0x07e40000 0x1000>;
2122 reg = <0x07f40000 0x1000>;
2141 reg = <0x00290000 0x10000>;
2146 reg = <0x0800f000 0x1000>,
2147 <0x08400000 0x1000000>,
2148 <0x09400000 0x1000000>,
2149 <0x0a400000 0x220000>,
2150 <0x0800a000 0x3000>;
2154 qcom,ee = <0>;
2155 qcom,channel = <0>;
2157 #size-cells = <0>;
2164 reg = <0x0a8f8800 0x400>;
2198 reg = <0x0a800000 0xcd00>;
2206 snps,hird-threshold = /bits/ 8 <0x10>;
2212 reg = <0x0c010000 0x1000>;
2223 #clock-cells = <0>;
2224 #phy-cells = <0>;
2231 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2238 reg = <0x0c012000 0x2a8>;
2240 #phy-cells = <0>;
2253 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2270 reg = <0x0c144000 0x25000>;
2275 qcom,ee = <0>;
2283 reg = <0x0c171000 0x1000>;
2291 pinctrl-0 = <&blsp1_uart3_on>;
2297 reg = <0x0c175000 0x600>;
2306 pinctrl-0 = <&blsp1_i2c1_default>;
2312 #size-cells = <0>;
2317 reg = <0x0c176000 0x600>;
2326 pinctrl-0 = <&blsp1_i2c2_default>;
2332 #size-cells = <0>;
2337 reg = <0x0c177000 0x600>;
2346 pinctrl-0 = <&blsp1_i2c3_default>;
2352 #size-cells = <0>;
2357 reg = <0x0c178000 0x600>;
2366 pinctrl-0 = <&blsp1_i2c4_default>;
2372 #size-cells = <0>;
2377 reg = <0x0c179000 0x600>;
2386 pinctrl-0 = <&blsp1_i2c5_default>;
2392 #size-cells = <0>;
2397 reg = <0x0c17a000 0x600>;
2406 pinctrl-0 = <&blsp1_i2c6_default>;
2412 #size-cells = <0>;
2417 reg = <0x0c175000 0x600>;
2426 pinctrl-0 = <&blsp1_spi1_default>;
2430 #size-cells = <0>;
2435 reg = <0x0c176000 0x600>;
2444 pinctrl-0 = <&blsp1_spi2_default>;
2448 #size-cells = <0>;
2453 reg = <0x0c177000 0x600>;
2462 pinctrl-0 = <&blsp1_spi3_default>;
2466 #size-cells = <0>;
2471 reg = <0x0c178000 0x600>;
2480 pinctrl-0 = <&blsp1_spi4_default>;
2484 #size-cells = <0>;
2489 reg = <0x0c179000 0x600>;
2498 pinctrl-0 = <&blsp1_spi5_default>;
2502 #size-cells = <0>;
2507 reg = <0x0c17a000 0x600>;
2516 pinctrl-0 = <&blsp1_spi6_default>;
2520 #size-cells = <0>;
2525 reg = <0x0c184000 0x25000>;
2530 qcom,ee = <0>;
2538 reg = <0x0c1b0000 0x1000>;
2548 reg = <0x0c1b5000 0x600>;
2557 pinctrl-0 = <&blsp2_i2c1_default>;
2563 #size-cells = <0>;
2568 reg = <0x0c1b6000 0x600>;
2577 pinctrl-0 = <&blsp2_i2c2_default>;
2583 #size-cells = <0>;
2588 reg = <0x0c1b7000 0x600>;
2597 pinctrl-0 = <&blsp2_i2c3_default>;
2603 #size-cells = <0>;
2608 reg = <0x0c1b8000 0x600>;
2617 pinctrl-0 = <&blsp2_i2c4_default>;
2623 #size-cells = <0>;
2628 reg = <0x0c1b9000 0x600>;
2637 pinctrl-0 = <&blsp2_i2c5_default>;
2643 #size-cells = <0>;
2648 reg = <0x0c1ba000 0x600>;
2657 pinctrl-0 = <&blsp2_i2c6_default>;
2663 #size-cells = <0>;
2668 reg = <0x0c1b5000 0x600>;
2677 pinctrl-0 = <&blsp2_spi1_default>;
2681 #size-cells = <0>;
2686 reg = <0x0c1b6000 0x600>;
2695 pinctrl-0 = <&blsp2_spi2_default>;
2699 #size-cells = <0>;
2704 reg = <0x0c1b7000 0x600>;
2713 pinctrl-0 = <&blsp2_spi3_default>;
2717 #size-cells = <0>;
2722 reg = <0x0c1b8000 0x600>;
2731 pinctrl-0 = <&blsp2_spi4_default>;
2735 #size-cells = <0>;
2740 reg = <0x0c1b9000 0x600>;
2749 pinctrl-0 = <&blsp2_spi5_default>;
2753 #size-cells = <0>;
2758 reg = <0x0c1ba000 0x600>;
2767 pinctrl-0 = <&blsp2_spi6_default>;
2771 #size-cells = <0>;
2779 reg = <0xc8c0000 0x40000>;
2794 <&mdss_dsi0_phy 0>,
2796 <&mdss_dsi1_phy 0>,
2797 <&mdss_hdmi_phy 0>,
2798 <0>,
2799 <0>,
2805 reg = <0x0c900000 0x1000>;
2820 iommus = <&mmss_smmu 0>;
2830 reg = <0x0c901000 0x8f000>,
2831 <0x0c9a8e00 0xf0>,
2832 <0x0c9b0000 0x2008>,
2833 <0x0c9b8000 0x1040>;
2840 interrupts = <0>;
2885 #size-cells = <0>;
2887 port@0 {
2888 reg = <0>;
2915 reg = <0x0c994000 0x400>;
2935 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2945 #size-cells = <0>;
2951 #size-cells = <0>;
2953 port@0 {
2954 reg = <0>;
2972 reg = <0x0c994400 0x200>,
2973 <0x0c994600 0x280>,
2974 <0x0c994a00 0x1e0>;
2984 #phy-cells = <0>;
2991 reg = <0x0c996000 0x400>;
3011 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3021 #size-cells = <0>;
3027 #size-cells = <0>;
3029 port@0 {
3030 reg = <0>;
3048 reg = <0x0c996400 0x200>,
3049 <0x0c996600 0x280>,
3050 <0x0c996a00 0x10e>;
3061 #phy-cells = <0>;
3068 reg = <0x0c9a0000 0x50c>,
3069 <0x00780000 0x6220>,
3070 <0x0c9e0000 0x2c>;
3099 pinctrl-0 = <&hdmi_hpd_default>,
3111 #size-cells = <0>;
3113 port@0 {
3114 reg = <0>;
3130 reg = <0x0c9a0600 0x18b>,
3131 <0x0c9a0a00 0x38>,
3132 <0x0c9a0c00 0x38>,
3133 <0x0c9a0e00 0x38>,
3134 <0x0c9a1000 0x38>,
3135 <0x0c9a1200 0x0e8>;
3143 #clock-cells = <0>;
3144 #phy-cells = <0>;
3159 reg = <0x0cc00000 0xff000>;
3167 iommus = <&mmss_smmu 0x400>,
3168 <&mmss_smmu 0x401>,
3169 <&mmss_smmu 0x40a>,
3170 <&mmss_smmu 0x407>,
3171 <&mmss_smmu 0x40e>,
3172 <&mmss_smmu 0x40f>,
3173 <&mmss_smmu 0x408>,
3174 <&mmss_smmu 0x409>,
3175 <&mmss_smmu 0x40b>,
3176 <&mmss_smmu 0x40c>,
3177 <&mmss_smmu 0x40d>,
3178 <&mmss_smmu 0x410>,
3179 <&mmss_smmu 0x421>,
3180 <&mmss_smmu 0x428>,
3181 <&mmss_smmu 0x429>,
3182 <&mmss_smmu 0x42b>,
3183 <&mmss_smmu 0x42c>,
3184 <&mmss_smmu 0x42d>,
3185 <&mmss_smmu 0x411>,
3186 <&mmss_smmu 0x431>;
3207 reg = <0x0cd00000 0x40000>;
3217 #global-interrupts = <0>;
3245 reg = <0x17300000 0x4040>;
3248 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3260 qcom,smem-states = <&adsp_smp2p_out 0>;
3279 reg = <0x17911000 0x1000>;
3289 reg = <0x17920000 0x1000>;
3292 frame-number = <0>;
3295 reg = <0x17921000 0x1000>,
3296 <0x17922000 0x1000>;
3302 reg = <0x17923000 0x1000>;
3309 reg = <0x17924000 0x1000>;
3316 reg = <0x17925000 0x1000>;
3323 reg = <0x17926000 0x1000>;
3330 reg = <0x17927000 0x1000>;
3337 reg = <0x17928000 0x1000>;
3344 reg = <0x17a00000 0x10000>, /* GICD */
3345 <0x17b00000 0x100000>; /* GICR * 8 */
3352 redistributor-stride = <0x0 0x20000>;
3359 reg = <0x18800000 0x800000>;
3377 iommus = <&anoc2_smmu 0x1900>,
3378 <&anoc2_smmu 0x1901>;