Lines Matching refs:mmcc
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
906 clocks = <&mmcc AHB_CLK_SRC>;
931 mmcc: clock-controller@8c0000 { label
932 compatible = "qcom,mmcc-msm8996";
953 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mmcc MMPLL1_PLL>,
955 <&mmcc MMPLL3_PLL>,
956 <&mmcc MMPLL4_PLL>,
957 <&mmcc MMPLL5_PLL>;
975 power-domains = <&mmcc MDSS_GDSC>;
981 clocks = <&mmcc MDSS_AHB_CLK>,
982 <&mmcc MDSS_MDP_CLK>;
985 resets = <&mmcc MDSS_BCR>;
1001 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mmcc MDSS_AXI_CLK>,
1003 <&mmcc MDSS_MDP_CLK>,
1004 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mmcc MDSS_VSYNC_CLK>;
1014 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mmcc MDSS_VSYNC_CLK>;
1060 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mmcc MDSS_AHB_CLK>,
1063 <&mmcc MDSS_AXI_CLK>,
1064 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mmcc MDSS_ESC0_CLK>;
1074 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1114 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1128 clocks = <&mmcc MDSS_MDP_CLK>,
1129 <&mmcc MDSS_BYTE1_CLK>,
1130 <&mmcc MDSS_AHB_CLK>,
1131 <&mmcc MDSS_AXI_CLK>,
1132 <&mmcc MMSS_MISC_AHB_CLK>,
1133 <&mmcc MDSS_PCLK1_CLK>,
1134 <&mmcc MDSS_ESC1_CLK>;
1142 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1182 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1199 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mmcc MDSS_AHB_CLK>,
1201 <&mmcc MDSS_HDMI_CLK>,
1202 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mmcc MDSS_EXTPCLK_CLK>;
1245 clocks = <&mmcc MDSS_AHB_CLK>,
1266 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1281 power-domains = <&mmcc GPU_GX_GDSC>;
2187 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_VFE_AXI_CLK>;
2278 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS_AHB_CLK>;
2287 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&mmcc CAMSS_CCI_CLK>;
2320 <&mmcc GPU_AHB_CLK>;
2323 power-domains = <&mmcc GPU_GDSC>;
2330 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO_MAXI_CLK>;
2364 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2366 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2371 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2373 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2386 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2387 <&mmcc SMMU_MDP_AHB_CLK>;
2390 power-domains = <&mmcc MDSS_GDSC>;
2405 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2407 <&mmcc SMMU_VIDEO_AHB_CLK>;
2421 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2423 <&mmcc SMMU_VFE_AHB_CLK>;