Lines Matching refs:gcc
8 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
688 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
689 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
690 <&gcc GCC_PCIE_CLKREF_CLK>;
693 resets = <&gcc GCC_PCIE_PHY_BCR>,
694 <&gcc GCC_PCIE_PHY_COM_BCR>,
695 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
705 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
707 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
721 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
723 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
737 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
739 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
779 clocks = <&gcc GCC_PRNG_AHB_CLK>;
783 gcc: clock-controller@300000 { label
784 compatible = "qcom,gcc-msm8996";
844 clocks = <&gcc GCC_CE1_CLK>;
854 clocks = <&gcc GCC_CE1_AHB_CLK>,
855 <&gcc GCC_CE1_AXI_CLK>,
856 <&gcc GCC_CE1_CLK>;
881 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
882 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
883 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
884 power-domains = <&gcc AGGRE0_NOC_GDSC>;
898 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
899 <&gcc GCC_UFS_AXI_CLK>;
939 <&gcc GPLL0>,
940 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
1251 <&gcc GCC_HDMI_CLKREF_CLK>,
1274 <&gcc GCC_BIMC_GFX_CLK>,
1275 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1884 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1893 power-domains = <&gcc PCIE0_GDSC>;
1942 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1943 <&gcc GCC_PCIE_0_AUX_CLK>,
1944 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1945 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1946 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1967 power-domains = <&gcc PCIE1_GDSC>;
2019 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2020 <&gcc GCC_PCIE_1_AUX_CLK>,
2021 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2022 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2023 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
2044 power-domains = <&gcc PCIE2_GDSC>;
2093 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2094 <&gcc GCC_PCIE_2_AUX_CLK>,
2095 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2096 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2097 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2126 power-domains = <&gcc UFS_GDSC>;
2139 <&gcc GCC_UFS_AXI_CLK>,
2140 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2141 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2142 <&gcc GCC_UFS_AHB_CLK>,
2143 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2144 <&gcc GCC_UFS_ICE_CORE_CLK>,
2146 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2147 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2172 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
2366 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2479 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2496 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2497 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2562 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2563 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2564 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2566 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2567 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2568 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2579 resets = <&gcc GCC_MSS_RESTART>;
3124 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3125 <&gcc GCC_USB30_MASTER_CLK>,
3126 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3127 <&gcc GCC_USB30_SLEEP_CLK>,
3128 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3135 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3136 <&gcc GCC_USB30_MASTER_CLK>;
3143 power-domains = <&gcc USB30_GDSC>;
3165 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3166 <&gcc GCC_USB3_CLKREF_CLK>,
3167 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3168 <&gcc GCC_USB3_PHY_PIPE_CLK>;
3177 resets = <&gcc GCC_USB3_PHY_BCR>,
3178 <&gcc GCC_USB3PHY_PHY_BCR>;
3190 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3191 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3194 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3204 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3205 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3208 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3223 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3224 <&gcc GCC_SDCC1_APPS_CLK>,
3226 resets = <&gcc GCC_SDCC1_BCR>;
3247 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3248 <&gcc GCC_SDCC2_APPS_CLK>,
3250 resets = <&gcc GCC_SDCC2_BCR>;
3264 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3275 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3276 <&gcc GCC_BLSP1_AHB_CLK>;
3290 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3291 <&gcc GCC_BLSP1_AHB_CLK>;
3307 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3308 <&gcc GCC_BLSP1_AHB_CLK>;
3324 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3325 <&gcc GCC_BLSP1_AHB_CLK>;
3341 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3352 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3353 <&gcc GCC_BLSP2_AHB_CLK>;
3362 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3363 <&gcc GCC_BLSP2_AHB_CLK>;
3372 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3373 <&gcc GCC_BLSP2_AHB_CLK>;
3389 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3390 <&gcc GCC_BLSP2_AHB_CLK>;
3406 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3407 <&gcc GCC_BLSP2_AHB_CLK>;
3424 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3425 <&gcc GCC_BLSP2_AHB_CLK>;
3440 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3441 <&gcc GCC_BLSP2_AHB_CLK>;
3457 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3458 <&gcc GCC_BLSP2_AHB_CLK>;
3484 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3485 <&gcc GCC_USB20_MASTER_CLK>,
3486 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3487 <&gcc GCC_USB20_SLEEP_CLK>,
3488 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3495 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3496 <&gcc GCC_USB20_MASTER_CLK>;
3502 power-domains = <&gcc USB30_GDSC>;
3583 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;