Lines Matching +full:smp2p +full:- +full:mpss
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/interconnect/qcom,msm8996.h>
12 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,apr.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <19200000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
44 #address-cells = <2>;
45 #size-cells = <0>;
51 enable-method = "psci";
52 cpu-idle-states = <&cpu_sleep_0>;
53 capacity-dmips-mhz = <1024>;
56 operating-points-v2 = <&cluster0_opp>;
57 #cooling-cells = <2>;
58 next-level-cache = <&l2_0>;
59 l2_0: l2-cache {
61 cache-level = <2>;
62 cache-unified;
70 enable-method = "psci";
71 cpu-idle-states = <&cpu_sleep_0>;
72 capacity-dmips-mhz = <1024>;
75 operating-points-v2 = <&cluster0_opp>;
76 #cooling-cells = <2>;
77 next-level-cache = <&l2_0>;
84 enable-method = "psci";
85 cpu-idle-states = <&cpu_sleep_0>;
86 capacity-dmips-mhz = <1024>;
89 operating-points-v2 = <&cluster1_opp>;
90 #cooling-cells = <2>;
91 next-level-cache = <&l2_1>;
92 l2_1: l2-cache {
94 cache-level = <2>;
95 cache-unified;
103 enable-method = "psci";
104 cpu-idle-states = <&cpu_sleep_0>;
105 capacity-dmips-mhz = <1024>;
108 operating-points-v2 = <&cluster1_opp>;
109 #cooling-cells = <2>;
110 next-level-cache = <&l2_1>;
113 cpu-map {
135 idle-states {
136 entry-method = "psci";
138 cpu_sleep_0: cpu-sleep-0 {
139 compatible = "arm,idle-state";
140 idle-state-name = "standalone-power-collapse";
141 arm,psci-suspend-param = <0x00000004>;
142 entry-latency-us = <130>;
143 exit-latency-us = <80>;
144 min-residency-us = <300>;
149 cluster0_opp: opp-table-cluster0 {
150 compatible = "operating-points-v2-kryo-cpu";
151 nvmem-cells = <&speedbin_efuse>;
152 opp-shared;
155 opp-307200000 {
156 opp-hz = /bits/ 64 <307200000>;
157 opp-supported-hw = <0xf>;
158 clock-latency-ns = <200000>;
159 opp-peak-kBps = <307200>;
161 opp-422400000 {
162 opp-hz = /bits/ 64 <422400000>;
163 opp-supported-hw = <0xf>;
164 clock-latency-ns = <200000>;
165 opp-peak-kBps = <307200>;
167 opp-480000000 {
168 opp-hz = /bits/ 64 <480000000>;
169 opp-supported-hw = <0xf>;
170 clock-latency-ns = <200000>;
171 opp-peak-kBps = <307200>;
173 opp-556800000 {
174 opp-hz = /bits/ 64 <556800000>;
175 opp-supported-hw = <0xf>;
176 clock-latency-ns = <200000>;
177 opp-peak-kBps = <307200>;
179 opp-652800000 {
180 opp-hz = /bits/ 64 <652800000>;
181 opp-supported-hw = <0xf>;
182 clock-latency-ns = <200000>;
183 opp-peak-kBps = <384000>;
185 opp-729600000 {
186 opp-hz = /bits/ 64 <729600000>;
187 opp-supported-hw = <0xf>;
188 clock-latency-ns = <200000>;
189 opp-peak-kBps = <460800>;
191 opp-844800000 {
192 opp-hz = /bits/ 64 <844800000>;
193 opp-supported-hw = <0xf>;
194 clock-latency-ns = <200000>;
195 opp-peak-kBps = <537600>;
197 opp-960000000 {
198 opp-hz = /bits/ 64 <960000000>;
199 opp-supported-hw = <0xf>;
200 clock-latency-ns = <200000>;
201 opp-peak-kBps = <672000>;
203 opp-1036800000 {
204 opp-hz = /bits/ 64 <1036800000>;
205 opp-supported-hw = <0xf>;
206 clock-latency-ns = <200000>;
207 opp-peak-kBps = <672000>;
209 opp-1113600000 {
210 opp-hz = /bits/ 64 <1113600000>;
211 opp-supported-hw = <0xf>;
212 clock-latency-ns = <200000>;
213 opp-peak-kBps = <825600>;
215 opp-1190400000 {
216 opp-hz = /bits/ 64 <1190400000>;
217 opp-supported-hw = <0xf>;
218 clock-latency-ns = <200000>;
219 opp-peak-kBps = <825600>;
221 opp-1228800000 {
222 opp-hz = /bits/ 64 <1228800000>;
223 opp-supported-hw = <0xf>;
224 clock-latency-ns = <200000>;
225 opp-peak-kBps = <902400>;
227 opp-1324800000 {
228 opp-hz = /bits/ 64 <1324800000>;
229 opp-supported-hw = <0xd>;
230 clock-latency-ns = <200000>;
231 opp-peak-kBps = <1056000>;
233 opp-1363200000 {
234 opp-hz = /bits/ 64 <1363200000>;
235 opp-supported-hw = <0x2>;
236 clock-latency-ns = <200000>;
237 opp-peak-kBps = <1132800>;
239 opp-1401600000 {
240 opp-hz = /bits/ 64 <1401600000>;
241 opp-supported-hw = <0xd>;
242 clock-latency-ns = <200000>;
243 opp-peak-kBps = <1132800>;
245 opp-1478400000 {
246 opp-hz = /bits/ 64 <1478400000>;
247 opp-supported-hw = <0x9>;
248 clock-latency-ns = <200000>;
249 opp-peak-kBps = <1190400>;
251 opp-1497600000 {
252 opp-hz = /bits/ 64 <1497600000>;
253 opp-supported-hw = <0x04>;
254 clock-latency-ns = <200000>;
255 opp-peak-kBps = <1305600>;
257 opp-1593600000 {
258 opp-hz = /bits/ 64 <1593600000>;
259 opp-supported-hw = <0x9>;
260 clock-latency-ns = <200000>;
261 opp-peak-kBps = <1382400>;
265 cluster1_opp: opp-table-cluster1 {
266 compatible = "operating-points-v2-kryo-cpu";
267 nvmem-cells = <&speedbin_efuse>;
268 opp-shared;
271 opp-307200000 {
272 opp-hz = /bits/ 64 <307200000>;
273 opp-supported-hw = <0xf>;
274 clock-latency-ns = <200000>;
275 opp-peak-kBps = <307200>;
277 opp-403200000 {
278 opp-hz = /bits/ 64 <403200000>;
279 opp-supported-hw = <0xf>;
280 clock-latency-ns = <200000>;
281 opp-peak-kBps = <307200>;
283 opp-480000000 {
284 opp-hz = /bits/ 64 <480000000>;
285 opp-supported-hw = <0xf>;
286 clock-latency-ns = <200000>;
287 opp-peak-kBps = <307200>;
289 opp-556800000 {
290 opp-hz = /bits/ 64 <556800000>;
291 opp-supported-hw = <0xf>;
292 clock-latency-ns = <200000>;
293 opp-peak-kBps = <307200>;
295 opp-652800000 {
296 opp-hz = /bits/ 64 <652800000>;
297 opp-supported-hw = <0xf>;
298 clock-latency-ns = <200000>;
299 opp-peak-kBps = <307200>;
301 opp-729600000 {
302 opp-hz = /bits/ 64 <729600000>;
303 opp-supported-hw = <0xf>;
304 clock-latency-ns = <200000>;
305 opp-peak-kBps = <307200>;
307 opp-806400000 {
308 opp-hz = /bits/ 64 <806400000>;
309 opp-supported-hw = <0xf>;
310 clock-latency-ns = <200000>;
311 opp-peak-kBps = <384000>;
313 opp-883200000 {
314 opp-hz = /bits/ 64 <883200000>;
315 opp-supported-hw = <0xf>;
316 clock-latency-ns = <200000>;
317 opp-peak-kBps = <460800>;
319 opp-940800000 {
320 opp-hz = /bits/ 64 <940800000>;
321 opp-supported-hw = <0xf>;
322 clock-latency-ns = <200000>;
323 opp-peak-kBps = <537600>;
325 opp-1036800000 {
326 opp-hz = /bits/ 64 <1036800000>;
327 opp-supported-hw = <0xf>;
328 clock-latency-ns = <200000>;
329 opp-peak-kBps = <595200>;
331 opp-1113600000 {
332 opp-hz = /bits/ 64 <1113600000>;
333 opp-supported-hw = <0xf>;
334 clock-latency-ns = <200000>;
335 opp-peak-kBps = <672000>;
337 opp-1190400000 {
338 opp-hz = /bits/ 64 <1190400000>;
339 opp-supported-hw = <0xf>;
340 clock-latency-ns = <200000>;
341 opp-peak-kBps = <672000>;
343 opp-1248000000 {
344 opp-hz = /bits/ 64 <1248000000>;
345 opp-supported-hw = <0xf>;
346 clock-latency-ns = <200000>;
347 opp-peak-kBps = <748800>;
349 opp-1324800000 {
350 opp-hz = /bits/ 64 <1324800000>;
351 opp-supported-hw = <0xf>;
352 clock-latency-ns = <200000>;
353 opp-peak-kBps = <825600>;
355 opp-1401600000 {
356 opp-hz = /bits/ 64 <1401600000>;
357 opp-supported-hw = <0xf>;
358 clock-latency-ns = <200000>;
359 opp-peak-kBps = <902400>;
361 opp-1478400000 {
362 opp-hz = /bits/ 64 <1478400000>;
363 opp-supported-hw = <0xf>;
364 clock-latency-ns = <200000>;
365 opp-peak-kBps = <979200>;
367 opp-1555200000 {
368 opp-hz = /bits/ 64 <1555200000>;
369 opp-supported-hw = <0xf>;
370 clock-latency-ns = <200000>;
371 opp-peak-kBps = <1056000>;
373 opp-1632000000 {
374 opp-hz = /bits/ 64 <1632000000>;
375 opp-supported-hw = <0xf>;
376 clock-latency-ns = <200000>;
377 opp-peak-kBps = <1190400>;
379 opp-1708800000 {
380 opp-hz = /bits/ 64 <1708800000>;
381 opp-supported-hw = <0xf>;
382 clock-latency-ns = <200000>;
383 opp-peak-kBps = <1228800>;
385 opp-1785600000 {
386 opp-hz = /bits/ 64 <1785600000>;
387 opp-supported-hw = <0xf>;
388 clock-latency-ns = <200000>;
389 opp-peak-kBps = <1305600>;
391 opp-1804800000 {
392 opp-hz = /bits/ 64 <1804800000>;
393 opp-supported-hw = <0xe>;
394 clock-latency-ns = <200000>;
395 opp-peak-kBps = <1305600>;
397 opp-1824000000 {
398 opp-hz = /bits/ 64 <1824000000>;
399 opp-supported-hw = <0x1>;
400 clock-latency-ns = <200000>;
401 opp-peak-kBps = <1382400>;
403 opp-1900800000 {
404 opp-hz = /bits/ 64 <1900800000>;
405 opp-supported-hw = <0x4>;
406 clock-latency-ns = <200000>;
407 opp-peak-kBps = <1305600>;
409 opp-1920000000 {
410 opp-hz = /bits/ 64 <1920000000>;
411 opp-supported-hw = <0x1>;
412 clock-latency-ns = <200000>;
413 opp-peak-kBps = <1459200>;
415 opp-1996800000 {
416 opp-hz = /bits/ 64 <1996800000>;
417 opp-supported-hw = <0x1>;
418 clock-latency-ns = <200000>;
419 opp-peak-kBps = <1593600>;
421 opp-2073600000 {
422 opp-hz = /bits/ 64 <2073600000>;
423 opp-supported-hw = <0x1>;
424 clock-latency-ns = <200000>;
425 opp-peak-kBps = <1593600>;
427 opp-2150400000 {
428 opp-hz = /bits/ 64 <2150400000>;
429 opp-supported-hw = <0x1>;
430 clock-latency-ns = <200000>;
431 opp-peak-kBps = <1593600>;
437 compatible = "qcom,scm-msm8996", "qcom,scm";
438 qcom,dload-mode = <&tcsr_2 0x13000>;
449 compatible = "qcom,coresight-remote-etm";
451 out-ports {
454 remote-endpoint =
462 compatible = "arm,psci-1.0";
467 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
469 glink-edge {
470 compatible = "qcom,glink-rpm";
472 qcom,rpm-msg-ram = <&rpm_msg_ram>;
475 rpm_requests: rpm-requests {
476 compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm";
477 qcom,glink-channels = "rpm_requests";
479 rpmcc: clock-controller {
480 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
481 #clock-cells = <1>;
483 clock-names = "xo";
486 rpmpd: power-controller {
487 compatible = "qcom,msm8996-rpmpd";
488 #power-domain-cells = <1>;
489 operating-points-v2 = <&rpmpd_opp_table>;
491 rpmpd_opp_table: opp-table {
492 compatible = "operating-points-v2";
495 opp-level = <1>;
499 opp-level = <2>;
503 opp-level = <3>;
507 opp-level = <4>;
511 opp-level = <5>;
515 opp-level = <6>;
523 reserved-memory {
524 #address-cells = <2>;
525 #size-cells = <2>;
530 no-map;
535 no-map;
538 smem_mem: smem-mem@86000000 {
540 no-map;
545 no-map;
549 compatible = "qcom,rmtfs-mem";
552 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
553 no-map;
555 qcom,client-id = <1>;
559 mpss_mem: mpss@88800000 {
561 no-map;
566 no-map;
571 no-map;
575 compatible = "shared-dma-pool";
577 no-map;
582 no-map;
587 no-map;
590 mdata_mem: mpss-metadata {
591 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
593 no-map;
599 memory-region = <&smem_mem>;
603 smp2p-adsp {
604 compatible = "qcom,smp2p";
611 qcom,local-pid = <0>;
612 qcom,remote-pid = <2>;
614 adsp_smp2p_out: master-kernel {
615 qcom,entry-name = "master-kernel";
616 #qcom,smem-state-cells = <1>;
619 adsp_smp2p_in: slave-kernel {
620 qcom,entry-name = "slave-kernel";
622 interrupt-controller;
623 #interrupt-cells = <2>;
627 smp2p-mpss {
628 compatible = "qcom,smp2p";
635 qcom,local-pid = <0>;
636 qcom,remote-pid = <1>;
638 mpss_smp2p_out: master-kernel {
639 qcom,entry-name = "master-kernel";
640 #qcom,smem-state-cells = <1>;
643 mpss_smp2p_in: slave-kernel {
644 qcom,entry-name = "slave-kernel";
646 interrupt-controller;
647 #interrupt-cells = <2>;
651 smp2p-slpi {
652 compatible = "qcom,smp2p";
659 qcom,local-pid = <0>;
660 qcom,remote-pid = <3>;
662 slpi_smp2p_out: master-kernel {
663 qcom,entry-name = "master-kernel";
664 #qcom,smem-state-cells = <1>;
667 slpi_smp2p_in: slave-kernel {
668 qcom,entry-name = "slave-kernel";
670 interrupt-controller;
671 #interrupt-cells = <2>;
676 #address-cells = <1>;
677 #size-cells = <1>;
679 compatible = "simple-bus";
681 pcie_phy: phy-wrapper@34000 {
682 compatible = "qcom,msm8996-qmp-pcie-phy";
684 #address-cells = <1>;
685 #size-cells = <1>;
691 clock-names = "aux", "cfg_ahb", "ref";
696 reset-names = "phy", "common", "cfg";
706 clock-names = "pipe0";
708 reset-names = "lane0";
710 #clock-cells = <0>;
711 clock-output-names = "pcie_0_pipe_clk_src";
713 #phy-cells = <0>;
722 clock-names = "pipe1";
724 reset-names = "lane1";
726 #clock-cells = <0>;
727 clock-output-names = "pcie_1_pipe_clk_src";
729 #phy-cells = <0>;
738 clock-names = "pipe2";
740 reset-names = "lane2";
742 #clock-cells = <0>;
743 clock-output-names = "pcie_2_pipe_clk_src";
745 #phy-cells = <0>;
750 compatible = "qcom,rpm-msg-ram";
755 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
757 #address-cells = <1>;
758 #size-cells = <1>;
760 qusb2p_hstx_trim: hstx-trim@24e {
765 qusb2s_hstx_trim: hstx-trim@24f {
777 compatible = "qcom,prng-ee";
780 clock-names = "core";
783 gcc: clock-controller@300000 {
784 compatible = "qcom,gcc-msm8996";
785 #clock-cells = <1>;
786 #reset-cells = <1>;
787 #power-domain-cells = <1>;
800 clock-names = "cxo",
813 compatible = "qcom,msm8996-bimc";
815 #interconnect-cells = <1>;
818 tsens0: thermal-sensor@4a9000 {
819 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
825 interrupt-names = "uplow", "critical";
826 #thermal-sensor-cells = <1>;
829 tsens1: thermal-sensor@4ad000 {
830 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
836 interrupt-names = "uplow", "critical";
837 #thermal-sensor-cells = <1>;
840 cryptobam: dma-controller@644000 {
841 compatible = "qcom,bam-v1.7.0";
845 clock-names = "bam_clk";
846 #dma-cells = <1>;
848 qcom,controlled-remotely;
852 compatible = "qcom,crypto-v5.4";
857 clock-names = "iface", "bus", "core";
859 dma-names = "rx", "tx";
863 compatible = "qcom,msm8996-cnoc";
865 #interconnect-cells = <1>;
869 compatible = "qcom,msm8996-snoc";
871 #interconnect-cells = <1>;
875 compatible = "qcom,msm8996-a0noc";
877 #interconnect-cells = <1>;
878 clock-names = "aggre0_snoc_axi",
884 power-domains = <&gcc AGGRE0_NOC_GDSC>;
888 compatible = "qcom,msm8996-a1noc";
890 #interconnect-cells = <1>;
894 compatible = "qcom,msm8996-a2noc";
896 #interconnect-cells = <1>;
897 clock-names = "aggre2_ufs_axi", "ufs_axi";
903 compatible = "qcom,msm8996-mnoc";
905 #interconnect-cells = <1>;
906 clock-names = "iface";
911 compatible = "qcom,msm8996-pnoc";
913 #interconnect-cells = <1>;
917 compatible = "qcom,tcsr-mutex";
919 #hwlock-cells = <1>;
923 compatible = "qcom,tcsr-msm8996", "syscon";
928 compatible = "qcom,tcsr-msm8996", "syscon";
932 mmcc: clock-controller@8c0000 {
933 compatible = "qcom,mmcc-msm8996";
934 #clock-cells = <1>;
935 #reset-cells = <1>;
936 #power-domain-cells = <1>;
946 clock-names = "xo",
954 assigned-clocks = <&mmcc MMPLL9_PLL>,
959 assigned-clock-rates = <624000000>,
966 mdss: display-subsystem@900000 {
972 reg-names = "mdss_phys",
976 power-domains = <&mmcc MDSS_GDSC>;
979 interrupt-controller;
980 #interrupt-cells = <1>;
984 clock-names = "iface", "core";
988 #address-cells = <1>;
989 #size-cells = <1>;
994 mdp: display-controller@901000 {
995 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
997 reg-names = "mdp_phys";
999 interrupt-parent = <&mdss>;
1007 clock-names = "iface",
1015 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1017 assigned-clock-rates = <300000000>,
1023 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1032 remote-endpoint = <&mdss_hdmi_in>;
1039 remote-endpoint = <&mdss_dsi0_in>;
1046 remote-endpoint = <&mdss_dsi1_in>;
1053 compatible = "qcom,msm8996-dsi-ctrl",
1054 "qcom,mdss-dsi-ctrl";
1056 reg-names = "dsi_ctrl";
1058 interrupt-parent = <&mdss>;
1068 clock-names = "mdp_core",
1075 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1077 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 remote-endpoint = <&mdp5_intf1_out>;
1106 compatible = "qcom,dsi-phy-14nm";
1110 reg-names = "dsi_phy",
1114 #clock-cells = <1>;
1115 #phy-cells = <0>;
1118 clock-names = "iface", "ref";
1123 compatible = "qcom,msm8996-dsi-ctrl",
1124 "qcom,mdss-dsi-ctrl";
1126 reg-names = "dsi_ctrl";
1128 interrupt-parent = <&mdss>;
1138 clock-names = "mdp_core",
1145 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
1147 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1163 remote-endpoint = <&mdp5_intf2_out>;
1176 compatible = "qcom,dsi-phy-14nm";
1180 reg-names = "dsi_phy",
1184 #clock-cells = <1>;
1185 #phy-cells = <0>;
1188 clock-names = "iface", "ref";
1192 mdss_hdmi: hdmi-tx@9a0000 {
1193 compatible = "qcom,hdmi-tx-8996";
1197 reg-names = "core_physical",
1201 interrupt-parent = <&mdss>;
1209 clock-names =
1217 #sound-dai-cells = <1>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1228 remote-endpoint = <&mdp5_intf3_out>;
1235 #phy-cells = <0>;
1236 compatible = "qcom,hdmi-phy-8996";
1243 reg-names = "hdmi_pll",
1253 clock-names = "iface",
1257 #clock-cells = <0>;
1264 compatible = "qcom,adreno-530.2", "qcom,adreno";
1267 reg-names = "kgsl_3d0_reg_memory";
1277 clock-names = "core",
1284 interconnect-names = "gfx-mem";
1286 power-domains = <&mmcc GPU_GX_GDSC>;
1289 nvmem-cells = <&speedbin_efuse>;
1290 nvmem-cell-names = "speed_bin";
1292 operating-points-v2 = <&gpu_opp_table>;
1296 #cooling-cells = <2>;
1298 gpu_opp_table: opp-table {
1299 compatible = "operating-points-v2";
1306 opp-624000000 {
1307 opp-hz = /bits/ 64 <624000000>;
1308 opp-supported-hw = <0x09>;
1310 opp-560000000 {
1311 opp-hz = /bits/ 64 <560000000>;
1312 opp-supported-hw = <0x0d>;
1314 opp-510000000 {
1315 opp-hz = /bits/ 64 <510000000>;
1316 opp-supported-hw = <0xff>;
1318 opp-401800000 {
1319 opp-hz = /bits/ 64 <401800000>;
1320 opp-supported-hw = <0xff>;
1322 opp-315000000 {
1323 opp-hz = /bits/ 64 <315000000>;
1324 opp-supported-hw = <0xff>;
1326 opp-214000000 {
1327 opp-hz = /bits/ 64 <214000000>;
1328 opp-supported-hw = <0xff>;
1330 opp-133000000 {
1331 opp-hz = /bits/ 64 <133000000>;
1332 opp-supported-hw = <0xff>;
1336 zap-shader {
1337 memory-region = <&gpu_mem>;
1342 compatible = "qcom,msm8996-pinctrl";
1345 gpio-controller;
1346 gpio-ranges = <&tlmm 0 0 150>;
1347 #gpio-cells = <2>;
1348 interrupt-controller;
1349 #interrupt-cells = <2>;
1351 blsp1_spi1_default: blsp1-spi1-default-state {
1352 spi-pins {
1355 drive-strength = <12>;
1356 bias-disable;
1359 cs-pins {
1362 drive-strength = <16>;
1363 bias-disable;
1364 output-high;
1368 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1371 drive-strength = <2>;
1372 bias-pull-down;
1375 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1378 drive-strength = <16>;
1379 bias-disable;
1382 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1385 drive-strength = <2>;
1386 bias-disable;
1389 blsp2_i2c2_default: blsp2-i2c2-state {
1392 drive-strength = <16>;
1393 bias-disable;
1396 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1399 drive-strength = <2>;
1400 bias-disable;
1403 blsp1_i2c6_default: blsp1-i2c6-state {
1406 drive-strength = <16>;
1407 bias-disable;
1410 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1413 drive-strength = <2>;
1414 bias-pull-up;
1417 cci0_default: cci0-default-state {
1420 drive-strength = <16>;
1421 bias-disable;
1425 camera_rear_default: camera-rear-default-state {
1426 camera0_mclk: mclk0-pins {
1429 drive-strength = <16>;
1430 bias-disable;
1433 camera0_rst: rst-pins {
1436 drive-strength = <16>;
1437 bias-disable;
1440 camera0_pwdn: pwdn-pins {
1443 drive-strength = <16>;
1444 bias-disable;
1448 cci1_default: cci1-default-state {
1451 drive-strength = <16>;
1452 bias-disable;
1456 camera_board_default: camera-board-default-state {
1457 mclk1-pins {
1460 drive-strength = <16>;
1461 bias-disable;
1464 pwdn-pins {
1467 drive-strength = <16>;
1468 bias-disable;
1471 rst-pins {
1474 drive-strength = <16>;
1475 bias-disable;
1480 camera_front_default: camera-front-default-state {
1481 camera2_mclk: mclk2-pins {
1484 drive-strength = <16>;
1485 bias-disable;
1488 camera2_rst: rst-pins {
1491 drive-strength = <16>;
1492 bias-disable;
1495 pwdn-pins {
1498 drive-strength = <16>;
1499 bias-disable;
1503 pcie0_state_on: pcie0-state-on-state {
1504 perst-pins {
1507 drive-strength = <2>;
1508 bias-pull-down;
1511 clkreq-pins {
1514 drive-strength = <2>;
1515 bias-pull-up;
1518 wake-pins {
1521 drive-strength = <2>;
1522 bias-pull-up;
1526 pcie0_state_off: pcie0-state-off-state {
1527 perst-pins {
1530 drive-strength = <2>;
1531 bias-pull-down;
1534 clkreq-pins {
1537 drive-strength = <2>;
1538 bias-disable;
1541 wake-pins {
1544 drive-strength = <2>;
1545 bias-disable;
1549 blsp1_uart2_default: blsp1-uart2-default-state {
1552 drive-strength = <16>;
1553 bias-disable;
1556 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1559 drive-strength = <2>;
1560 bias-disable;
1563 blsp1_i2c3_default: blsp1-i2c3-default-state {
1566 drive-strength = <16>;
1567 bias-disable;
1570 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1573 drive-strength = <2>;
1574 bias-disable;
1577 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1580 drive-strength = <16>;
1581 bias-disable;
1584 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1587 drive-strength = <2>;
1588 bias-disable;
1591 blsp2_i2c3_default: blsp2-i2c3-state-state {
1594 drive-strength = <16>;
1595 bias-disable;
1598 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1601 drive-strength = <2>;
1602 bias-disable;
1605 wcd_intr_default: wcd-intr-default-state {
1608 drive-strength = <2>;
1609 bias-pull-down;
1612 blsp2_i2c1_default: blsp2-i2c1-state {
1615 drive-strength = <16>;
1616 bias-disable;
1619 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1622 drive-strength = <2>;
1623 bias-disable;
1626 blsp2_i2c5_default: blsp2-i2c5-state {
1629 drive-strength = <2>;
1630 bias-disable;
1635 cdc_reset_active: cdc-reset-active-state {
1638 drive-strength = <16>;
1639 bias-pull-down;
1640 output-high;
1643 cdc_reset_sleep: cdc-reset-sleep-state {
1646 drive-strength = <16>;
1647 bias-disable;
1648 output-low;
1651 blsp2_spi6_default: blsp2-spi6-default-state {
1652 spi-pins {
1655 drive-strength = <12>;
1656 bias-disable;
1659 cs-pins {
1662 drive-strength = <16>;
1663 bias-disable;
1664 output-high;
1668 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1671 drive-strength = <2>;
1672 bias-pull-down;
1675 blsp2_i2c6_default: blsp2-i2c6-state {
1678 drive-strength = <16>;
1679 bias-disable;
1682 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1685 drive-strength = <2>;
1686 bias-disable;
1689 pcie1_state_on: pcie1-on-state {
1690 perst-pins {
1693 drive-strength = <2>;
1694 bias-pull-down;
1697 clkreq-pins {
1700 drive-strength = <2>;
1701 bias-pull-up;
1704 wake-pins {
1707 drive-strength = <2>;
1708 bias-pull-down;
1712 pcie1_state_off: pcie1-off-state {
1714 clkreq-pins {
1717 drive-strength = <2>;
1718 bias-disable;
1721 wake-pins {
1724 drive-strength = <2>;
1725 bias-disable;
1729 pcie2_state_on: pcie2-on-state {
1730 perst-pins {
1733 drive-strength = <2>;
1734 bias-pull-down;
1737 clkreq-pins {
1740 drive-strength = <2>;
1741 bias-pull-up;
1744 wake-pins {
1747 drive-strength = <2>;
1748 bias-pull-down;
1752 pcie2_state_off: pcie2-off-state {
1754 clkreq-pins {
1757 drive-strength = <2>;
1758 bias-disable;
1761 wake-pins {
1764 drive-strength = <2>;
1765 bias-disable;
1769 sdc1_state_on: sdc1-on-state {
1770 clk-pins {
1772 bias-disable;
1773 drive-strength = <16>;
1776 cmd-pins {
1778 bias-pull-up;
1779 drive-strength = <10>;
1782 data-pins {
1784 bias-pull-up;
1785 drive-strength = <10>;
1788 rclk-pins {
1790 bias-pull-down;
1794 sdc1_state_off: sdc1-off-state {
1795 clk-pins {
1797 bias-disable;
1798 drive-strength = <2>;
1801 cmd-pins {
1803 bias-pull-up;
1804 drive-strength = <2>;
1807 data-pins {
1809 bias-pull-up;
1810 drive-strength = <2>;
1813 rclk-pins {
1815 bias-pull-down;
1819 sdc2_state_on: sdc2-on-state {
1820 clk-pins {
1822 bias-disable;
1823 drive-strength = <16>;
1826 cmd-pins {
1828 bias-pull-up;
1829 drive-strength = <10>;
1832 data-pins {
1834 bias-pull-up;
1835 drive-strength = <10>;
1839 sdc2_state_off: sdc2-off-state {
1840 clk-pins {
1842 bias-disable;
1843 drive-strength = <2>;
1846 cmd-pins {
1848 bias-pull-up;
1849 drive-strength = <2>;
1852 data-pins {
1854 bias-pull-up;
1855 drive-strength = <2>;
1861 compatible = "qcom,rpm-stats";
1866 compatible = "qcom,spmi-pmic-arb";
1872 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1873 interrupt-names = "periph_irq";
1877 #address-cells = <2>;
1878 #size-cells = <0>;
1879 interrupt-controller;
1880 #interrupt-cells = <4>;
1884 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1885 compatible = "simple-pm-bus";
1886 #address-cells = <1>;
1887 #size-cells = <1>;
1891 compatible = "qcom,pcie-msm8996";
1893 power-domains = <&gcc PCIE0_GDSC>;
1894 bus-range = <0x00 0xff>;
1895 num-lanes = <1>;
1901 reg-names = "parf", "dbi", "elbi","config";
1904 phy-names = "pciephy";
1906 #address-cells = <3>;
1907 #size-cells = <2>;
1921 interrupt-names = "msi0",
1929 #interrupt-cells = <1>;
1930 interrupt-map-mask = <0 0 0 0x7>;
1931 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1936 pinctrl-names = "default", "sleep";
1937 pinctrl-0 = <&pcie0_state_on>;
1938 pinctrl-1 = <&pcie0_state_off>;
1940 linux,pci-domain = <0>;
1948 clock-names = "pipe",
1957 bus-range = <0x01 0xff>;
1959 #address-cells = <3>;
1960 #size-cells = <2>;
1966 compatible = "qcom,pcie-msm8996";
1967 power-domains = <&gcc PCIE1_GDSC>;
1968 bus-range = <0x00 0xff>;
1969 num-lanes = <1>;
1978 reg-names = "parf", "dbi", "elbi","config";
1981 phy-names = "pciephy";
1983 #address-cells = <3>;
1984 #size-cells = <2>;
1998 interrupt-names = "msi0",
2006 #interrupt-cells = <1>;
2007 interrupt-map-mask = <0 0 0 0x7>;
2008 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2013 pinctrl-names = "default", "sleep";
2014 pinctrl-0 = <&pcie1_state_on>;
2015 pinctrl-1 = <&pcie1_state_off>;
2017 linux,pci-domain = <1>;
2025 clock-names = "pipe",
2034 bus-range = <0x01 0xff>;
2036 #address-cells = <3>;
2037 #size-cells = <2>;
2043 compatible = "qcom,pcie-msm8996";
2044 power-domains = <&gcc PCIE2_GDSC>;
2045 bus-range = <0x00 0xff>;
2046 num-lanes = <1>;
2053 reg-names = "parf", "dbi", "elbi","config";
2056 phy-names = "pciephy";
2058 #address-cells = <3>;
2059 #size-cells = <2>;
2073 interrupt-names = "msi0",
2081 #interrupt-cells = <1>;
2082 interrupt-map-mask = <0 0 0 0x7>;
2083 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2088 pinctrl-names = "default", "sleep";
2089 pinctrl-0 = <&pcie2_state_on>;
2090 pinctrl-1 = <&pcie2_state_off>;
2092 linux,pci-domain = <2>;
2099 clock-names = "pipe",
2108 bus-range = <0x01 0xff>;
2110 #address-cells = <3>;
2111 #size-cells = <2>;
2118 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2119 "jedec,ufs-2.0";
2124 phy-names = "ufsphy";
2126 power-domains = <&gcc UFS_GDSC>;
2128 clock-names =
2148 freq-table-hz =
2161 interconnect-names = "ufs-ddr", "cpu-ufs";
2163 lanes-per-direction = <1>;
2164 #reset-cells = <1>;
2169 compatible = "qcom,msm8996-qmp-ufs-phy";
2173 clock-names = "ref", "qref";
2176 reset-names = "ufsphy";
2178 #clock-cells = <1>;
2179 #phy-cells = <0>;
2185 compatible = "qcom,msm8996-camss";
2200 reg-names = "csiphy0",
2224 interrupt-names = "csiphy0",
2234 power-domains = <&mmcc VFE0_GDSC>,
2272 clock-names = "top_ahb",
2314 #address-cells = <1>;
2315 #size-cells = <0>;
2320 compatible = "qcom,msm8996-cci";
2321 #address-cells = <1>;
2322 #size-cells = <0>;
2325 power-domains = <&mmcc CAMSS_GDSC>;
2330 clock-names = "camss_top_ahb",
2334 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2336 assigned-clock-rates = <80000000>, <37500000>;
2337 pinctrl-names = "default";
2338 pinctrl-0 = <&cci0_default &cci1_default>;
2341 cci_i2c0: i2c-bus@0 {
2343 clock-frequency = <400000>;
2344 #address-cells = <1>;
2345 #size-cells = <0>;
2348 cci_i2c1: i2c-bus@1 {
2350 clock-frequency = <400000>;
2351 #address-cells = <1>;
2352 #size-cells = <0>;
2357 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2360 #global-interrupts = <1>;
2364 #iommu-cells = <1>;
2368 clock-names = "bus", "iface";
2370 power-domains = <&mmcc GPU_GDSC>;
2373 venus: video-codec@c00000 {
2374 compatible = "qcom,msm8996-venus";
2377 power-domains = <&mmcc VENUS_GDSC>;
2382 clock-names = "core", "iface", "bus", "mbus";
2385 interconnect-names = "video-mem", "cpu-cfg";
2406 memory-region = <&venus_mem>;
2409 video-decoder {
2410 compatible = "venus-decoder";
2412 clock-names = "core";
2413 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2416 video-encoder {
2417 compatible = "venus-encoder";
2419 clock-names = "core";
2420 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2425 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2428 #global-interrupts = <1>;
2432 #iommu-cells = <1>;
2435 clock-names = "bus", "iface";
2437 power-domains = <&mmcc MDSS_GDSC>;
2441 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2443 #global-interrupts = <1>;
2452 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2455 clock-names = "bus", "iface";
2456 #iommu-cells = <1>;
2461 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2464 #global-interrupts = <1>;
2468 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2471 clock-names = "bus", "iface";
2472 #iommu-cells = <1>;
2476 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2478 #iommu-cells = <1>;
2479 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2481 #global-interrupts = <1>;
2498 clock-names = "bus", "iface";
2502 compatible = "qcom,msm8996-slpi-pil";
2505 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2510 interrupt-names = "wdog",
2514 "stop-ack";
2517 clock-names = "xo";
2519 memory-region = <&slpi_mem>;
2521 qcom,smem-states = <&slpi_smp2p_out 0>;
2522 qcom,smem-state-names = "stop";
2524 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2525 power-domain-names = "ssc_cx";
2529 glink-edge {
2532 qcom,remote-pid = <3>;
2536 smd-edge {
2541 qcom,smd-edge = <3>;
2542 qcom,remote-pid = <3>;
2547 compatible = "qcom,msm8996-mss-pil";
2550 reg-names = "qdsp6", "rmb";
2552 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2558 interrupt-names = "wdog", "fatal", "ready",
2559 "handover", "stop-ack",
2560 "shutdown-ack";
2570 clock-names = "iface",
2580 reset-names = "mss_restart";
2582 power-domains = <&rpmpd MSM8996_VDDCX>,
2584 power-domain-names = "cx", "mx";
2586 qcom,smem-states = <&mpss_smp2p_out 0>;
2587 qcom,smem-state-names = "stop";
2589 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2594 memory-region = <&mba_mem>;
2597 mpss {
2598 memory-region = <&mpss_mem>;
2602 memory-region = <&mdata_mem>;
2605 glink-edge {
2608 qcom,remote-pid = <1>;
2612 smd-edge {
2615 label = "mpss";
2617 qcom,smd-edge = <0>;
2618 qcom,remote-pid = <1>;
2623 compatible = "arm,coresight-stm", "arm,primecell";
2626 reg-names = "stm-base", "stm-stimulus-base";
2629 clock-names = "apb_pclk", "atclk";
2631 out-ports {
2634 remote-endpoint =
2642 compatible = "arm,coresight-tpiu", "arm,primecell";
2646 clock-names = "apb_pclk", "atclk";
2648 in-ports {
2651 remote-endpoint =
2659 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2663 clock-names = "apb_pclk", "atclk";
2665 in-ports {
2666 #address-cells = <1>;
2667 #size-cells = <0>;
2672 remote-endpoint =
2678 out-ports {
2681 remote-endpoint =
2689 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2693 clock-names = "apb_pclk", "atclk";
2695 in-ports {
2696 #address-cells = <1>;
2697 #size-cells = <0>;
2702 remote-endpoint =
2708 out-ports {
2711 remote-endpoint =
2719 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2723 clock-names = "apb_pclk", "atclk";
2725 in-ports {
2728 remote-endpoint =
2734 out-ports {
2737 remote-endpoint =
2745 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2749 clock-names = "apb_pclk", "atclk";
2751 in-ports {
2752 #address-cells = <1>;
2753 #size-cells = <0>;
2758 remote-endpoint =
2766 remote-endpoint =
2774 remote-endpoint =
2780 out-ports {
2783 remote-endpoint =
2791 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2795 clock-names = "apb_pclk", "atclk";
2797 in-ports {
2800 remote-endpoint =
2806 out-ports {
2807 #address-cells = <1>;
2808 #size-cells = <0>;
2813 remote-endpoint =
2821 remote-endpoint =
2829 compatible = "arm,coresight-tmc", "arm,primecell";
2833 clock-names = "apb_pclk", "atclk";
2835 in-ports {
2838 remote-endpoint =
2844 out-ports {
2847 remote-endpoint =
2855 compatible = "arm,coresight-tmc", "arm,primecell";
2859 clock-names = "apb_pclk", "atclk";
2860 arm,scatter-gather;
2862 in-ports {
2865 remote-endpoint =
2873 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2877 clock-names = "apb_pclk";
2883 compatible = "arm,coresight-etm4x", "arm,primecell";
2887 clock-names = "apb_pclk", "atclk";
2891 out-ports {
2894 remote-endpoint =
2902 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2906 clock-names = "apb_pclk";
2912 compatible = "arm,coresight-etm4x", "arm,primecell";
2916 clock-names = "apb_pclk", "atclk";
2920 out-ports {
2923 remote-endpoint =
2931 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2935 clock-names = "apb_pclk", "atclk";
2937 in-ports {
2938 #address-cells = <1>;
2939 #size-cells = <0>;
2944 remote-endpoint = <&etm0_out>;
2951 remote-endpoint = <&etm1_out>;
2956 out-ports {
2959 remote-endpoint =
2967 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2971 clock-names = "apb_pclk";
2977 compatible = "arm,coresight-etm4x", "arm,primecell";
2981 clock-names = "apb_pclk", "atclk";
2985 out-ports {
2988 remote-endpoint =
2996 compatible = "arm,coresight-cpu-debug", "arm,primecell";
3000 clock-names = "apb_pclk";
3006 compatible = "arm,coresight-etm4x", "arm,primecell";
3010 clock-names = "apb_pclk", "atclk";
3014 out-ports {
3017 remote-endpoint =
3025 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3029 clock-names = "apb_pclk", "atclk";
3031 in-ports {
3032 #address-cells = <1>;
3033 #size-cells = <0>;
3038 remote-endpoint = <&etm2_out>;
3045 remote-endpoint = <&etm3_out>;
3050 out-ports {
3053 remote-endpoint =
3061 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3065 clock-names = "apb_pclk", "atclk";
3067 in-ports {
3068 #address-cells = <1>;
3069 #size-cells = <0>;
3074 remote-endpoint =
3082 remote-endpoint =
3088 out-ports {
3091 remote-endpoint =
3098 kryocc: clock-controller@6400000 {
3099 compatible = "qcom,msm8996-apcc";
3102 clock-names = "xo", "sys_apcs_aux";
3105 #clock-cells = <1>;
3109 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3111 #address-cells = <1>;
3112 #size-cells = <1>;
3119 interrupt-names = "pwr_event",
3129 clock-names = "cfg_noc",
3135 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3137 assigned-clock-rates = <19200000>, <120000000>;
3141 interconnect-names = "usb-ddr", "apps-usb";
3143 power-domains = <&gcc USB30_GDSC>;
3151 phy-names = "usb2-phy", "usb3-phy";
3152 snps,hird-threshold = /bits/ 8 <0>;
3155 snps,is-utmi-l1-suspend;
3156 snps,parkmode-disable-ss-quirk;
3157 tx-fifo-resize;
3162 compatible = "qcom,msm8996-qmp-usb3-phy";
3169 clock-names = "aux",
3173 clock-output-names = "usb3_phy_pipe_clk_src";
3174 #clock-cells = <0>;
3175 #phy-cells = <0>;
3179 reset-names = "phy",
3186 compatible = "qcom,msm8996-qusb2-phy";
3188 #phy-cells = <0>;
3192 clock-names = "cfg_ahb", "ref";
3195 nvmem-cells = <&qusb2p_hstx_trim>;
3200 compatible = "qcom,msm8996-qusb2-phy";
3202 #phy-cells = <0>;
3206 clock-names = "cfg_ahb", "ref";
3209 nvmem-cells = <&qusb2s_hstx_trim>;
3214 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3216 reg-names = "hc", "core";
3220 interrupt-names = "hc_irq", "pwr_irq";
3222 clock-names = "iface", "core", "xo";
3228 pinctrl-names = "default", "sleep";
3229 pinctrl-0 = <&sdc1_state_on>;
3230 pinctrl-1 = <&sdc1_state_off>;
3232 bus-width = <8>;
3233 non-removable;
3238 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3240 reg-names = "hc", "core";
3244 interrupt-names = "hc_irq", "pwr_irq";
3246 clock-names = "iface", "core", "xo";
3252 pinctrl-names = "default", "sleep";
3253 pinctrl-0 = <&sdc2_state_on>;
3254 pinctrl-1 = <&sdc2_state_off>;
3256 bus-width = <4>;
3260 blsp1_dma: dma-controller@7544000 {
3261 compatible = "qcom,bam-v1.7.0";
3265 clock-names = "bam_clk";
3266 qcom,controlled-remotely;
3267 #dma-cells = <1>;
3272 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3277 clock-names = "core", "iface";
3278 pinctrl-names = "default", "sleep";
3279 pinctrl-0 = <&blsp1_uart2_default>;
3280 pinctrl-1 = <&blsp1_uart2_sleep>;
3282 dma-names = "tx", "rx";
3287 compatible = "qcom,spi-qup-v2.2.1";
3292 clock-names = "core", "iface";
3293 pinctrl-names = "default", "sleep";
3294 pinctrl-0 = <&blsp1_spi1_default>;
3295 pinctrl-1 = <&blsp1_spi1_sleep>;
3297 dma-names = "tx", "rx";
3298 #address-cells = <1>;
3299 #size-cells = <0>;
3304 compatible = "qcom,i2c-qup-v2.2.1";
3309 clock-names = "core", "iface";
3310 pinctrl-names = "default", "sleep";
3311 pinctrl-0 = <&blsp1_i2c3_default>;
3312 pinctrl-1 = <&blsp1_i2c3_sleep>;
3314 dma-names = "tx", "rx";
3315 #address-cells = <1>;
3316 #size-cells = <0>;
3321 compatible = "qcom,i2c-qup-v2.2.1";
3326 clock-names = "core", "iface";
3327 pinctrl-names = "default", "sleep";
3328 pinctrl-0 = <&blsp1_i2c6_default>;
3329 pinctrl-1 = <&blsp1_i2c6_sleep>;
3331 dma-names = "tx", "rx";
3332 #address-cells = <1>;
3333 #size-cells = <0>;
3337 blsp2_dma: dma-controller@7584000 {
3338 compatible = "qcom,bam-v1.7.0";
3342 clock-names = "bam_clk";
3343 qcom,controlled-remotely;
3344 #dma-cells = <1>;
3349 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3354 clock-names = "core", "iface";
3359 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3364 clock-names = "core", "iface";
3369 compatible = "qcom,i2c-qup-v2.2.1";
3374 clock-names = "core", "iface";
3375 pinctrl-names = "default", "sleep";
3376 pinctrl-0 = <&blsp2_i2c1_default>;
3377 pinctrl-1 = <&blsp2_i2c1_sleep>;
3379 dma-names = "tx", "rx";
3380 #address-cells = <1>;
3381 #size-cells = <0>;
3386 compatible = "qcom,i2c-qup-v2.2.1";
3391 clock-names = "core", "iface";
3392 pinctrl-names = "default", "sleep";
3393 pinctrl-0 = <&blsp2_i2c2_default>;
3394 pinctrl-1 = <&blsp2_i2c2_sleep>;
3396 dma-names = "tx", "rx";
3397 #address-cells = <1>;
3398 #size-cells = <0>;
3403 compatible = "qcom,i2c-qup-v2.2.1";
3408 clock-names = "core", "iface";
3409 clock-frequency = <400000>;
3410 pinctrl-names = "default", "sleep";
3411 pinctrl-0 = <&blsp2_i2c3_default>;
3412 pinctrl-1 = <&blsp2_i2c3_sleep>;
3414 dma-names = "tx", "rx";
3415 #address-cells = <1>;
3416 #size-cells = <0>;
3421 compatible = "qcom,i2c-qup-v2.2.1";
3426 clock-names = "core", "iface";
3427 pinctrl-names = "default";
3428 pinctrl-0 = <&blsp2_i2c5_default>;
3430 dma-names = "tx", "rx";
3431 #address-cells = <1>;
3432 #size-cells = <0>;
3437 compatible = "qcom,i2c-qup-v2.2.1";
3442 clock-names = "core", "iface";
3443 pinctrl-names = "default", "sleep";
3444 pinctrl-0 = <&blsp2_i2c6_default>;
3445 pinctrl-1 = <&blsp2_i2c6_sleep>;
3447 dma-names = "tx", "rx";
3448 #address-cells = <1>;
3449 #size-cells = <0>;
3454 compatible = "qcom,spi-qup-v2.2.1";
3459 clock-names = "core", "iface";
3460 pinctrl-names = "default", "sleep";
3461 pinctrl-0 = <&blsp2_spi6_default>;
3462 pinctrl-1 = <&blsp2_spi6_sleep>;
3464 dma-names = "tx", "rx";
3465 #address-cells = <1>;
3466 #size-cells = <0>;
3471 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3473 #address-cells = <1>;
3474 #size-cells = <1>;
3480 interrupt-names = "pwr_event",
3489 clock-names = "cfg_noc",
3495 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3497 assigned-clock-rates = <19200000>, <60000000>;
3499 power-domains = <&gcc USB30_GDSC>;
3500 qcom,select-utmi-as-pipe-clk;
3508 phy-names = "usb2-phy";
3509 maximum-speed = "high-speed";
3515 slimbam: dma-controller@9184000 {
3516 compatible = "qcom,bam-v1.7.0";
3517 qcom,controlled-remotely;
3519 num-channels = <31>;
3521 #dma-cells = <1>;
3523 qcom,num-ees = <2>;
3526 slim_msm: slim-ngd@91c0000 {
3527 compatible = "qcom,slim-ngd-v1.5.0";
3531 dma-names = "rx", "tx";
3532 #address-cells = <1>;
3533 #size-cells = <0>;
3539 compatible = "qcom,msm8996-adsp-pil";
3542 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3547 interrupt-names = "wdog", "fatal", "ready",
3548 "handover", "stop-ack";
3551 clock-names = "xo";
3553 memory-region = <&adsp_mem>;
3555 qcom,smem-states = <&adsp_smp2p_out 0>;
3556 qcom,smem-state-names = "stop";
3558 power-domains = <&rpmpd MSM8996_VDDCX>;
3559 power-domain-names = "cx";
3563 glink-edge {
3566 qcom,remote-pid = <2>;
3571 smd-edge {
3576 qcom,smd-edge = <1>;
3577 qcom,remote-pid = <2>;
3580 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3581 compatible = "qcom,apr-v2";
3582 qcom,smd-channels = "apr_audio_svc";
3584 #address-cells = <1>;
3585 #size-cells = <0>;
3596 compatible = "qcom,q6afe-dais";
3597 #address-cells = <1>;
3598 #size-cells = <0>;
3599 #sound-dai-cells = <1>;
3610 compatible = "qcom,q6asm-dais";
3611 #address-cells = <1>;
3612 #size-cells = <0>;
3613 #sound-dai-cells = <1>;
3622 compatible = "qcom,q6adm-routing";
3623 #sound-dai-cells = <0>;
3630 qcom,smd-channels = "fastrpcsmd-apps-dsp";
3632 qcom,non-secure-domain;
3633 #address-cells = <1>;
3634 #size-cells = <0>;
3637 compatible = "qcom,fastrpc-compute-cb";
3643 compatible = "qcom,fastrpc-compute-cb";
3649 compatible = "qcom,fastrpc-compute-cb";
3655 compatible = "qcom,fastrpc-compute-cb";
3661 compatible = "qcom,fastrpc-compute-cb";
3667 compatible = "qcom,fastrpc-compute-cb";
3673 compatible = "qcom,fastrpc-compute-cb";
3679 compatible = "qcom,fastrpc-compute-cb";
3688 compatible = "qcom,msm8996-apcs-hmss-global";
3691 #mbox-cells = <1>;
3692 #clock-cells = <0>;
3696 #address-cells = <1>;
3697 #size-cells = <1>;
3699 compatible = "arm,armv7-timer-mem";
3701 clock-frequency = <19200000>;
3704 frame-number = <0>;
3712 frame-number = <1>;
3719 frame-number = <2>;
3726 frame-number = <3>;
3733 frame-number = <4>;
3740 frame-number = <5>;
3747 frame-number = <6>;
3759 cbf: clock-controller@9a11000 {
3760 compatible = "qcom,msm8996-cbf";
3763 #clock-cells = <0>;
3764 #interconnect-cells = <1>;
3767 intc: interrupt-controller@9bc0000 {
3768 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3769 #interrupt-cells = <3>;
3770 interrupt-controller;
3771 #redistributor-regions = <1>;
3772 redistributor-stride = <0x0 0x40000>;
3782 thermal-zones {
3783 cpu0-thermal {
3784 polling-delay-passive = <250>;
3786 thermal-sensors = <&tsens0 3>;
3789 cpu0_alert0: trip-point0 {
3795 cpu0_crit: cpu-crit {
3803 cpu1-thermal {
3804 polling-delay-passive = <250>;
3806 thermal-sensors = <&tsens0 5>;
3809 cpu1_alert0: trip-point0 {
3815 cpu1_crit: cpu-crit {
3823 cpu2-thermal {
3824 polling-delay-passive = <250>;
3826 thermal-sensors = <&tsens0 8>;
3829 cpu2_alert0: trip-point0 {
3835 cpu2_crit: cpu-crit {
3843 cpu3-thermal {
3844 polling-delay-passive = <250>;
3846 thermal-sensors = <&tsens0 10>;
3849 cpu3_alert0: trip-point0 {
3855 cpu3_crit: cpu-crit {
3863 gpu-top-thermal {
3864 polling-delay-passive = <250>;
3866 thermal-sensors = <&tsens1 6>;
3869 gpu1_alert0: trip-point0 {
3876 cooling-maps {
3879 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3884 gpu-bottom-thermal {
3885 polling-delay-passive = <250>;
3887 thermal-sensors = <&tsens1 7>;
3890 gpu2_alert0: trip-point0 {
3897 cooling-maps {
3900 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3905 m4m-thermal {
3906 polling-delay-passive = <250>;
3908 thermal-sensors = <&tsens0 1>;
3911 m4m_alert0: trip-point0 {
3919 l3-or-venus-thermal {
3920 polling-delay-passive = <250>;
3922 thermal-sensors = <&tsens0 2>;
3925 l3_or_venus_alert0: trip-point0 {
3933 cluster0-l2-thermal {
3934 polling-delay-passive = <250>;
3936 thermal-sensors = <&tsens0 7>;
3939 cluster0_l2_alert0: trip-point0 {
3947 cluster1-l2-thermal {
3948 polling-delay-passive = <250>;
3950 thermal-sensors = <&tsens0 12>;
3953 cluster1_l2_alert0: trip-point0 {
3961 camera-thermal {
3962 polling-delay-passive = <250>;
3964 thermal-sensors = <&tsens1 1>;
3967 camera_alert0: trip-point0 {
3975 q6-dsp-thermal {
3976 polling-delay-passive = <250>;
3978 thermal-sensors = <&tsens1 2>;
3981 q6_dsp_alert0: trip-point0 {
3989 mem-thermal {
3990 polling-delay-passive = <250>;
3992 thermal-sensors = <&tsens1 3>;
3995 mem_alert0: trip-point0 {
4003 modemtx-thermal {
4004 polling-delay-passive = <250>;
4006 thermal-sensors = <&tsens1 4>;
4009 modemtx_alert0: trip-point0 {
4019 compatible = "arm,armv8-timer";