Lines Matching +full:dsp +full:- +full:gpio4
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
43 #address-cells = <2>;
44 #size-cells = <0>;
50 enable-method = "psci";
51 cpu-idle-states = <&cpu_sleep_0>;
52 capacity-dmips-mhz = <1024>;
55 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>;
57 next-level-cache = <&l2_0>;
58 l2_0: l2-cache {
60 cache-level = <2>;
61 cache-unified;
69 enable-method = "psci";
70 cpu-idle-states = <&cpu_sleep_0>;
71 capacity-dmips-mhz = <1024>;
74 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>;
76 next-level-cache = <&l2_0>;
83 enable-method = "psci";
84 cpu-idle-states = <&cpu_sleep_0>;
85 capacity-dmips-mhz = <1024>;
88 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>;
90 next-level-cache = <&l2_1>;
91 l2_1: l2-cache {
93 cache-level = <2>;
94 cache-unified;
102 enable-method = "psci";
103 cpu-idle-states = <&cpu_sleep_0>;
104 capacity-dmips-mhz = <1024>;
107 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>;
109 next-level-cache = <&l2_1>;
112 cpu-map {
134 idle-states {
135 entry-method = "psci";
137 cpu_sleep_0: cpu-sleep-0 {
138 compatible = "arm,idle-state";
139 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspend-param = <0x00000004>;
141 entry-latency-us = <130>;
142 exit-latency-us = <80>;
143 min-residency-us = <300>;
148 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse>;
151 opp-shared;
154 opp-307200000 {
155 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0xf>;
157 clock-latency-ns = <200000>;
158 opp-peak-kBps = <307200>;
160 opp-422400000 {
161 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0xf>;
163 clock-latency-ns = <200000>;
164 opp-peak-kBps = <307200>;
166 opp-480000000 {
167 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0xf>;
169 clock-latency-ns = <200000>;
170 opp-peak-kBps = <307200>;
172 opp-556800000 {
173 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0xf>;
175 clock-latency-ns = <200000>;
176 opp-peak-kBps = <307200>;
178 opp-652800000 {
179 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0xf>;
181 clock-latency-ns = <200000>;
182 opp-peak-kBps = <384000>;
184 opp-729600000 {
185 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0xf>;
187 clock-latency-ns = <200000>;
188 opp-peak-kBps = <460800>;
190 opp-844800000 {
191 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0xf>;
193 clock-latency-ns = <200000>;
194 opp-peak-kBps = <537600>;
196 opp-960000000 {
197 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0xf>;
199 clock-latency-ns = <200000>;
200 opp-peak-kBps = <672000>;
202 opp-1036800000 {
203 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0xf>;
205 clock-latency-ns = <200000>;
206 opp-peak-kBps = <672000>;
208 opp-1113600000 {
209 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0xf>;
211 clock-latency-ns = <200000>;
212 opp-peak-kBps = <825600>;
214 opp-1190400000 {
215 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0xf>;
217 clock-latency-ns = <200000>;
218 opp-peak-kBps = <825600>;
220 opp-1228800000 {
221 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0xf>;
223 clock-latency-ns = <200000>;
224 opp-peak-kBps = <902400>;
226 opp-1324800000 {
227 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0xd>;
229 clock-latency-ns = <200000>;
230 opp-peak-kBps = <1056000>;
232 opp-1363200000 {
233 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x2>;
235 clock-latency-ns = <200000>;
236 opp-peak-kBps = <1132800>;
238 opp-1401600000 {
239 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0xd>;
241 clock-latency-ns = <200000>;
242 opp-peak-kBps = <1132800>;
244 opp-1478400000 {
245 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x9>;
247 clock-latency-ns = <200000>;
248 opp-peak-kBps = <1190400>;
250 opp-1497600000 {
251 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x04>;
253 clock-latency-ns = <200000>;
254 opp-peak-kBps = <1305600>;
256 opp-1593600000 {
257 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x9>;
259 clock-latency-ns = <200000>;
260 opp-peak-kBps = <1382400>;
264 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse>;
267 opp-shared;
270 opp-307200000 {
271 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0xf>;
273 clock-latency-ns = <200000>;
274 opp-peak-kBps = <307200>;
276 opp-403200000 {
277 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0xf>;
279 clock-latency-ns = <200000>;
280 opp-peak-kBps = <307200>;
282 opp-480000000 {
283 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0xf>;
285 clock-latency-ns = <200000>;
286 opp-peak-kBps = <307200>;
288 opp-556800000 {
289 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0xf>;
291 clock-latency-ns = <200000>;
292 opp-peak-kBps = <307200>;
294 opp-652800000 {
295 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0xf>;
297 clock-latency-ns = <200000>;
298 opp-peak-kBps = <307200>;
300 opp-729600000 {
301 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0xf>;
303 clock-latency-ns = <200000>;
304 opp-peak-kBps = <307200>;
306 opp-806400000 {
307 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0xf>;
309 clock-latency-ns = <200000>;
310 opp-peak-kBps = <384000>;
312 opp-883200000 {
313 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0xf>;
315 clock-latency-ns = <200000>;
316 opp-peak-kBps = <460800>;
318 opp-940800000 {
319 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0xf>;
321 clock-latency-ns = <200000>;
322 opp-peak-kBps = <537600>;
324 opp-1036800000 {
325 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0xf>;
327 clock-latency-ns = <200000>;
328 opp-peak-kBps = <595200>;
330 opp-1113600000 {
331 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0xf>;
333 clock-latency-ns = <200000>;
334 opp-peak-kBps = <672000>;
336 opp-1190400000 {
337 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0xf>;
339 clock-latency-ns = <200000>;
340 opp-peak-kBps = <672000>;
342 opp-1248000000 {
343 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0xf>;
345 clock-latency-ns = <200000>;
346 opp-peak-kBps = <748800>;
348 opp-1324800000 {
349 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0xf>;
351 clock-latency-ns = <200000>;
352 opp-peak-kBps = <825600>;
354 opp-1401600000 {
355 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0xf>;
357 clock-latency-ns = <200000>;
358 opp-peak-kBps = <902400>;
360 opp-1478400000 {
361 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0xf>;
363 clock-latency-ns = <200000>;
364 opp-peak-kBps = <979200>;
366 opp-1555200000 {
367 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0xf>;
369 clock-latency-ns = <200000>;
370 opp-peak-kBps = <1056000>;
372 opp-1632000000 {
373 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0xf>;
375 clock-latency-ns = <200000>;
376 opp-peak-kBps = <1190400>;
378 opp-1708800000 {
379 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0xf>;
381 clock-latency-ns = <200000>;
382 opp-peak-kBps = <1228800>;
384 opp-1785600000 {
385 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0xf>;
387 clock-latency-ns = <200000>;
388 opp-peak-kBps = <1305600>;
390 opp-1804800000 {
391 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0xe>;
393 clock-latency-ns = <200000>;
394 opp-peak-kBps = <1305600>;
396 opp-1824000000 {
397 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x1>;
399 clock-latency-ns = <200000>;
400 opp-peak-kBps = <1382400>;
402 opp-1900800000 {
403 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x4>;
405 clock-latency-ns = <200000>;
406 opp-peak-kBps = <1305600>;
408 opp-1920000000 {
409 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x1>;
411 clock-latency-ns = <200000>;
412 opp-peak-kBps = <1459200>;
414 opp-1996800000 {
415 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x1>;
417 clock-latency-ns = <200000>;
418 opp-peak-kBps = <1593600>;
420 opp-2073600000 {
421 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x1>;
423 clock-latency-ns = <200000>;
424 opp-peak-kBps = <1593600>;
426 opp-2150400000 {
427 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x1>;
429 clock-latency-ns = <200000>;
430 opp-peak-kBps = <1593600>;
436 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tcsr_2 0x13000>;
448 compatible = "qcom,coresight-remote-etm";
450 out-ports {
453 remote-endpoint =
461 compatible = "arm,psci-1.0";
466 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
468 glink-edge {
469 compatible = "qcom,glink-rpm";
471 qcom,rpm-msg-ram = <&rpm_msg_ram>;
474 rpm_requests: rpm-requests {
475 compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm";
476 qcom,glink-channels = "rpm_requests";
478 rpmcc: clock-controller {
479 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
480 #clock-cells = <1>;
482 clock-names = "xo";
485 rpmpd: power-controller {
486 compatible = "qcom,msm8996-rpmpd";
487 #power-domain-cells = <1>;
488 operating-points-v2 = <&rpmpd_opp_table>;
490 rpmpd_opp_table: opp-table {
491 compatible = "operating-points-v2";
494 opp-level = <1>;
498 opp-level = <2>;
502 opp-level = <3>;
506 opp-level = <4>;
510 opp-level = <5>;
514 opp-level = <6>;
522 reserved-memory {
523 #address-cells = <2>;
524 #size-cells = <2>;
529 no-map;
534 no-map;
537 smem_mem: smem-mem@86000000 {
539 no-map;
544 no-map;
548 compatible = "qcom,rmtfs-mem";
551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map;
554 qcom,client-id = <1>;
560 no-map;
565 no-map;
570 no-map;
574 compatible = "shared-dma-pool";
576 no-map;
581 no-map;
586 no-map;
589 mdata_mem: mpss-metadata {
590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
592 no-map;
598 memory-region = <&smem_mem>;
602 smp2p-adsp {
610 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>;
613 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells = <1>;
618 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "slave-kernel";
621 interrupt-controller;
622 #interrupt-cells = <2>;
626 smp2p-mpss {
634 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>;
637 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells = <1>;
642 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "slave-kernel";
645 interrupt-controller;
646 #interrupt-cells = <2>;
650 smp2p-slpi {
658 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>;
661 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells = <1>;
666 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "slave-kernel";
669 interrupt-controller;
670 #interrupt-cells = <2>;
675 #address-cells = <1>;
676 #size-cells = <1>;
678 compatible = "simple-bus";
680 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm8996-qmp-pcie-phy";
683 #address-cells = <1>;
684 #size-cells = <1>;
690 clock-names = "aux", "cfg_ahb", "ref";
695 reset-names = "phy", "common", "cfg";
705 clock-names = "pipe0";
707 reset-names = "lane0";
709 #clock-cells = <0>;
710 clock-output-names = "pcie_0_pipe_clk_src";
712 #phy-cells = <0>;
721 clock-names = "pipe1";
723 reset-names = "lane1";
725 #clock-cells = <0>;
726 clock-output-names = "pcie_1_pipe_clk_src";
728 #phy-cells = <0>;
737 clock-names = "pipe2";
739 reset-names = "lane2";
741 #clock-cells = <0>;
742 clock-output-names = "pcie_2_pipe_clk_src";
744 #phy-cells = <0>;
749 compatible = "qcom,rpm-msg-ram";
754 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
756 #address-cells = <1>;
757 #size-cells = <1>;
759 qusb2p_hstx_trim: hstx-trim@24e {
764 qusb2s_hstx_trim: hstx-trim@24f {
776 compatible = "qcom,prng-ee";
779 clock-names = "core";
782 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
799 clock-names = "cxo",
812 compatible = "qcom,msm8996-bimc";
814 #interconnect-cells = <1>;
817 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
824 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells = <1>;
828 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
835 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells = <1>;
839 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam-v1.7.0";
844 clock-names = "bam_clk";
845 #dma-cells = <1>;
847 qcom,controlled-remotely;
851 compatible = "qcom,crypto-v5.4";
856 clock-names = "iface", "bus", "core";
858 dma-names = "rx", "tx";
862 compatible = "qcom,msm8996-cnoc";
864 #interconnect-cells = <1>;
868 compatible = "qcom,msm8996-snoc";
870 #interconnect-cells = <1>;
874 compatible = "qcom,msm8996-a0noc";
876 #interconnect-cells = <1>;
877 clock-names = "aggre0_snoc_axi",
883 power-domains = <&gcc AGGRE0_NOC_GDSC>;
887 compatible = "qcom,msm8996-a1noc";
889 #interconnect-cells = <1>;
893 compatible = "qcom,msm8996-a2noc";
895 #interconnect-cells = <1>;
896 clock-names = "aggre2_ufs_axi", "ufs_axi";
902 compatible = "qcom,msm8996-mnoc";
904 #interconnect-cells = <1>;
905 clock-names = "iface";
910 compatible = "qcom,msm8996-pnoc";
912 #interconnect-cells = <1>;
916 compatible = "qcom,tcsr-mutex";
918 #hwlock-cells = <1>;
922 compatible = "qcom,tcsr-msm8996", "syscon";
927 compatible = "qcom,tcsr-msm8996", "syscon";
931 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>;
934 #reset-cells = <1>;
935 #power-domain-cells = <1>;
945 clock-names = "xo",
953 assigned-clocks = <&mmcc MMPLL9_PLL>,
958 assigned-clock-rates = <624000000>,
965 mdss: display-subsystem@900000 {
971 reg-names = "mdss_phys",
975 power-domains = <&mmcc MDSS_GDSC>;
978 interrupt-controller;
979 #interrupt-cells = <1>;
983 clock-names = "iface", "core";
987 #address-cells = <1>;
988 #size-cells = <1>;
993 mdp: display-controller@901000 {
994 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
996 reg-names = "mdp_phys";
998 interrupt-parent = <&mdss>;
1006 clock-names = "iface",
1014 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1016 assigned-clock-rates = <300000000>,
1022 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1031 remote-endpoint = <&mdss_hdmi_in>;
1038 remote-endpoint = <&mdss_dsi0_in>;
1045 remote-endpoint = <&mdss_dsi1_in>;
1052 compatible = "qcom,msm8996-dsi-ctrl",
1053 "qcom,mdss-dsi-ctrl";
1055 reg-names = "dsi_ctrl";
1057 interrupt-parent = <&mdss>;
1067 clock-names = "mdp_core",
1074 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1075 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1090 remote-endpoint = <&mdp5_intf1_out>;
1103 compatible = "qcom,dsi-phy-14nm";
1107 reg-names = "dsi_phy",
1111 #clock-cells = <1>;
1112 #phy-cells = <0>;
1115 clock-names = "iface", "ref";
1120 compatible = "qcom,msm8996-dsi-ctrl",
1121 "qcom,mdss-dsi-ctrl";
1123 reg-names = "dsi_ctrl";
1125 interrupt-parent = <&mdss>;
1135 clock-names = "mdp_core",
1142 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1143 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1158 remote-endpoint = <&mdp5_intf2_out>;
1171 compatible = "qcom,dsi-phy-14nm";
1175 reg-names = "dsi_phy",
1179 #clock-cells = <1>;
1180 #phy-cells = <0>;
1183 clock-names = "iface", "ref";
1187 mdss_hdmi: hdmi-tx@9a0000 {
1188 compatible = "qcom,hdmi-tx-8996";
1192 reg-names = "core_physical",
1196 interrupt-parent = <&mdss>;
1204 clock-names =
1212 #sound-dai-cells = <1>;
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1223 remote-endpoint = <&mdp5_intf3_out>;
1230 #phy-cells = <0>;
1231 compatible = "qcom,hdmi-phy-8996";
1238 reg-names = "hdmi_pll",
1248 clock-names = "iface",
1252 #clock-cells = <0>;
1259 compatible = "qcom,adreno-530.2", "qcom,adreno";
1262 reg-names = "kgsl_3d0_reg_memory";
1272 clock-names = "core",
1279 interconnect-names = "gfx-mem";
1281 power-domains = <&mmcc GPU_GX_GDSC>;
1284 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "speed_bin";
1287 operating-points-v2 = <&gpu_opp_table>;
1291 #cooling-cells = <2>;
1293 gpu_opp_table: opp-table {
1294 compatible = "operating-points-v2";
1301 opp-624000000 {
1302 opp-hz = /bits/ 64 <624000000>;
1303 opp-supported-hw = <0x09>;
1305 opp-560000000 {
1306 opp-hz = /bits/ 64 <560000000>;
1307 opp-supported-hw = <0x0d>;
1309 opp-510000000 {
1310 opp-hz = /bits/ 64 <510000000>;
1311 opp-supported-hw = <0xff>;
1313 opp-401800000 {
1314 opp-hz = /bits/ 64 <401800000>;
1315 opp-supported-hw = <0xff>;
1317 opp-315000000 {
1318 opp-hz = /bits/ 64 <315000000>;
1319 opp-supported-hw = <0xff>;
1321 opp-214000000 {
1322 opp-hz = /bits/ 64 <214000000>;
1323 opp-supported-hw = <0xff>;
1325 opp-133000000 {
1326 opp-hz = /bits/ 64 <133000000>;
1327 opp-supported-hw = <0xff>;
1331 zap-shader {
1332 memory-region = <&gpu_mem>;
1337 compatible = "qcom,msm8996-pinctrl";
1340 gpio-controller;
1341 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>;
1343 interrupt-controller;
1344 #interrupt-cells = <2>;
1346 blsp1_spi1_default: blsp1-spi1-default-state {
1347 spi-pins {
1350 drive-strength = <12>;
1351 bias-disable;
1354 cs-pins {
1357 drive-strength = <16>;
1358 bias-disable;
1359 output-high;
1363 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1366 drive-strength = <2>;
1367 bias-pull-down;
1370 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1371 pins = "gpio4", "gpio5";
1373 drive-strength = <16>;
1374 bias-disable;
1377 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1378 pins = "gpio4", "gpio5";
1380 drive-strength = <2>;
1381 bias-disable;
1384 blsp2_i2c2_default: blsp2-i2c2-state {
1387 drive-strength = <16>;
1388 bias-disable;
1391 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1394 drive-strength = <2>;
1395 bias-disable;
1398 blsp1_i2c6_default: blsp1-i2c6-state {
1401 drive-strength = <16>;
1402 bias-disable;
1405 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1408 drive-strength = <2>;
1409 bias-pull-up;
1412 cci0_default: cci0-default-state {
1415 drive-strength = <16>;
1416 bias-disable;
1420 camera_rear_default: camera-rear-default-state {
1421 camera0_mclk: mclk0-pins {
1424 drive-strength = <16>;
1425 bias-disable;
1428 camera0_rst: rst-pins {
1431 drive-strength = <16>;
1432 bias-disable;
1435 camera0_pwdn: pwdn-pins {
1438 drive-strength = <16>;
1439 bias-disable;
1443 cci1_default: cci1-default-state {
1446 drive-strength = <16>;
1447 bias-disable;
1451 camera_board_default: camera-board-default-state {
1452 mclk1-pins {
1455 drive-strength = <16>;
1456 bias-disable;
1459 pwdn-pins {
1462 drive-strength = <16>;
1463 bias-disable;
1466 rst-pins {
1469 drive-strength = <16>;
1470 bias-disable;
1475 camera_front_default: camera-front-default-state {
1476 camera2_mclk: mclk2-pins {
1479 drive-strength = <16>;
1480 bias-disable;
1483 camera2_rst: rst-pins {
1486 drive-strength = <16>;
1487 bias-disable;
1490 pwdn-pins {
1493 drive-strength = <16>;
1494 bias-disable;
1498 pcie0_state_on: pcie0-state-on-state {
1499 perst-pins {
1502 drive-strength = <2>;
1503 bias-pull-down;
1506 clkreq-pins {
1509 drive-strength = <2>;
1510 bias-pull-up;
1513 wake-pins {
1516 drive-strength = <2>;
1517 bias-pull-up;
1521 pcie0_state_off: pcie0-state-off-state {
1522 perst-pins {
1525 drive-strength = <2>;
1526 bias-pull-down;
1529 clkreq-pins {
1532 drive-strength = <2>;
1533 bias-disable;
1536 wake-pins {
1539 drive-strength = <2>;
1540 bias-disable;
1544 blsp1_uart2_default: blsp1-uart2-default-state {
1547 drive-strength = <16>;
1548 bias-disable;
1551 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1554 drive-strength = <2>;
1555 bias-disable;
1558 blsp1_i2c3_default: blsp1-i2c3-default-state {
1561 drive-strength = <16>;
1562 bias-disable;
1565 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1568 drive-strength = <2>;
1569 bias-disable;
1572 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1575 drive-strength = <16>;
1576 bias-disable;
1579 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1582 drive-strength = <2>;
1583 bias-disable;
1586 blsp2_i2c3_default: blsp2-i2c3-state-state {
1589 drive-strength = <16>;
1590 bias-disable;
1593 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1596 drive-strength = <2>;
1597 bias-disable;
1600 wcd_intr_default: wcd-intr-default-state {
1603 drive-strength = <2>;
1604 bias-pull-down;
1607 blsp2_i2c1_default: blsp2-i2c1-state {
1610 drive-strength = <16>;
1611 bias-disable;
1614 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1617 drive-strength = <2>;
1618 bias-disable;
1621 blsp2_i2c5_default: blsp2-i2c5-state {
1624 drive-strength = <2>;
1625 bias-disable;
1630 cdc_reset_active: cdc-reset-active-state {
1633 drive-strength = <16>;
1634 bias-pull-down;
1635 output-high;
1638 cdc_reset_sleep: cdc-reset-sleep-state {
1641 drive-strength = <16>;
1642 bias-disable;
1643 output-low;
1646 blsp2_spi6_default: blsp2-spi6-default-state {
1647 spi-pins {
1650 drive-strength = <12>;
1651 bias-disable;
1654 cs-pins {
1657 drive-strength = <16>;
1658 bias-disable;
1659 output-high;
1663 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1666 drive-strength = <2>;
1667 bias-pull-down;
1670 blsp2_i2c6_default: blsp2-i2c6-state {
1673 drive-strength = <16>;
1674 bias-disable;
1677 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1680 drive-strength = <2>;
1681 bias-disable;
1684 pcie1_state_on: pcie1-on-state {
1685 perst-pins {
1688 drive-strength = <2>;
1689 bias-pull-down;
1692 clkreq-pins {
1695 drive-strength = <2>;
1696 bias-pull-up;
1699 wake-pins {
1702 drive-strength = <2>;
1703 bias-pull-down;
1707 pcie1_state_off: pcie1-off-state {
1709 clkreq-pins {
1712 drive-strength = <2>;
1713 bias-disable;
1716 wake-pins {
1719 drive-strength = <2>;
1720 bias-disable;
1724 pcie2_state_on: pcie2-on-state {
1725 perst-pins {
1728 drive-strength = <2>;
1729 bias-pull-down;
1732 clkreq-pins {
1735 drive-strength = <2>;
1736 bias-pull-up;
1739 wake-pins {
1742 drive-strength = <2>;
1743 bias-pull-down;
1747 pcie2_state_off: pcie2-off-state {
1749 clkreq-pins {
1752 drive-strength = <2>;
1753 bias-disable;
1756 wake-pins {
1759 drive-strength = <2>;
1760 bias-disable;
1764 sdc1_state_on: sdc1-on-state {
1765 clk-pins {
1767 bias-disable;
1768 drive-strength = <16>;
1771 cmd-pins {
1773 bias-pull-up;
1774 drive-strength = <10>;
1777 data-pins {
1779 bias-pull-up;
1780 drive-strength = <10>;
1783 rclk-pins {
1785 bias-pull-down;
1789 sdc1_state_off: sdc1-off-state {
1790 clk-pins {
1792 bias-disable;
1793 drive-strength = <2>;
1796 cmd-pins {
1798 bias-pull-up;
1799 drive-strength = <2>;
1802 data-pins {
1804 bias-pull-up;
1805 drive-strength = <2>;
1808 rclk-pins {
1810 bias-pull-down;
1814 sdc2_state_on: sdc2-on-state {
1815 clk-pins {
1817 bias-disable;
1818 drive-strength = <16>;
1821 cmd-pins {
1823 bias-pull-up;
1824 drive-strength = <10>;
1827 data-pins {
1829 bias-pull-up;
1830 drive-strength = <10>;
1834 sdc2_state_off: sdc2-off-state {
1835 clk-pins {
1837 bias-disable;
1838 drive-strength = <2>;
1841 cmd-pins {
1843 bias-pull-up;
1844 drive-strength = <2>;
1847 data-pins {
1849 bias-pull-up;
1850 drive-strength = <2>;
1856 compatible = "qcom,rpm-stats";
1861 compatible = "qcom,spmi-pmic-arb";
1867 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "periph_irq";
1872 #address-cells = <2>;
1873 #size-cells = <0>;
1874 interrupt-controller;
1875 #interrupt-cells = <4>;
1879 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple-pm-bus";
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1886 compatible = "qcom,pcie-msm8996";
1888 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = <0x00 0xff>;
1890 num-lanes = <1>;
1896 reg-names = "parf", "dbi", "elbi","config";
1899 phy-names = "pciephy";
1901 #address-cells = <3>;
1902 #size-cells = <2>;
1909 interrupt-names = "msi";
1910 #interrupt-cells = <1>;
1911 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1917 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = <&pcie0_state_off>;
1921 linux,pci-domain = <0>;
1929 clock-names = "pipe",
1938 bus-range = <0x01 0xff>;
1940 #address-cells = <3>;
1941 #size-cells = <2>;
1947 compatible = "qcom,pcie-msm8996";
1948 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = <0x00 0xff>;
1950 num-lanes = <1>;
1959 reg-names = "parf", "dbi", "elbi","config";
1962 phy-names = "pciephy";
1964 #address-cells = <3>;
1965 #size-cells = <2>;
1972 interrupt-names = "msi";
1973 #interrupt-cells = <1>;
1974 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1980 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = <&pcie1_state_off>;
1984 linux,pci-domain = <1>;
1992 clock-names = "pipe",
2001 bus-range = <0x01 0xff>;
2003 #address-cells = <3>;
2004 #size-cells = <2>;
2010 compatible = "qcom,pcie-msm8996";
2011 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = <0x00 0xff>;
2013 num-lanes = <1>;
2020 reg-names = "parf", "dbi", "elbi","config";
2023 phy-names = "pciephy";
2025 #address-cells = <3>;
2026 #size-cells = <2>;
2033 interrupt-names = "msi";
2034 #interrupt-cells = <1>;
2035 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2041 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = <&pcie2_state_off>;
2045 linux,pci-domain = <2>;
2052 clock-names = "pipe",
2061 bus-range = <0x01 0xff>;
2063 #address-cells = <3>;
2064 #size-cells = <2>;
2071 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2072 "jedec,ufs-2.0";
2077 phy-names = "ufsphy";
2079 power-domains = <&gcc UFS_GDSC>;
2081 clock-names =
2101 freq-table-hz =
2114 interconnect-names = "ufs-ddr", "cpu-ufs";
2116 lanes-per-direction = <1>;
2117 #reset-cells = <1>;
2122 compatible = "qcom,msm8996-qmp-ufs-phy";
2126 clock-names = "ref", "qref";
2129 reset-names = "ufsphy";
2131 #clock-cells = <1>;
2132 #phy-cells = <0>;
2138 compatible = "qcom,msm8996-camss";
2153 reg-names = "csiphy0",
2177 interrupt-names = "csiphy0",
2187 power-domains = <&mmcc VFE0_GDSC>,
2225 clock-names = "top_ahb",
2267 #address-cells = <1>;
2268 #size-cells = <0>;
2273 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>;
2275 #size-cells = <0>;
2278 power-domains = <&mmcc CAMSS_GDSC>;
2283 clock-names = "camss_top_ahb",
2287 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2289 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_default &cci1_default>;
2294 cci_i2c0: i2c-bus@0 {
2296 clock-frequency = <400000>;
2297 #address-cells = <1>;
2298 #size-cells = <0>;
2301 cci_i2c1: i2c-bus@1 {
2303 clock-frequency = <400000>;
2304 #address-cells = <1>;
2305 #size-cells = <0>;
2310 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2313 #global-interrupts = <1>;
2317 #iommu-cells = <1>;
2321 clock-names = "bus", "iface";
2323 power-domains = <&mmcc GPU_GDSC>;
2326 venus: video-codec@c00000 {
2327 compatible = "qcom,msm8996-venus";
2330 power-domains = <&mmcc VENUS_GDSC>;
2335 clock-names = "core", "iface", "bus", "mbus";
2338 interconnect-names = "video-mem", "cpu-cfg";
2359 memory-region = <&venus_mem>;
2362 video-decoder {
2363 compatible = "venus-decoder";
2365 clock-names = "core";
2366 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2369 video-encoder {
2370 compatible = "venus-encoder";
2372 clock-names = "core";
2373 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2378 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2381 #global-interrupts = <1>;
2385 #iommu-cells = <1>;
2388 clock-names = "bus", "iface";
2390 power-domains = <&mmcc MDSS_GDSC>;
2394 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2396 #global-interrupts = <1>;
2405 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2408 clock-names = "bus", "iface";
2409 #iommu-cells = <1>;
2414 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2417 #global-interrupts = <1>;
2421 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2424 clock-names = "bus", "iface";
2425 #iommu-cells = <1>;
2429 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2431 #iommu-cells = <1>;
2432 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2434 #global-interrupts = <1>;
2451 clock-names = "bus", "iface";
2455 compatible = "qcom,msm8996-slpi-pil";
2458 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2463 interrupt-names = "wdog",
2467 "stop-ack";
2470 clock-names = "xo";
2472 memory-region = <&slpi_mem>;
2474 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names = "stop";
2477 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = "ssc_cx";
2482 glink-edge {
2485 qcom,remote-pid = <3>;
2489 smd-edge {
2494 qcom,smd-edge = <3>;
2495 qcom,remote-pid = <3>;
2500 compatible = "qcom,msm8996-mss-pil";
2503 reg-names = "qdsp6", "rmb";
2505 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2511 interrupt-names = "wdog", "fatal", "ready",
2512 "handover", "stop-ack",
2513 "shutdown-ack";
2523 clock-names = "iface",
2533 reset-names = "mss_restart";
2535 power-domains = <&rpmpd MSM8996_VDDCX>,
2537 power-domain-names = "cx", "mx";
2539 qcom,smem-states = <&mpss_smp2p_out 0>;
2540 qcom,smem-state-names = "stop";
2542 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2547 memory-region = <&mba_mem>;
2551 memory-region = <&mpss_mem>;
2555 memory-region = <&mdata_mem>;
2558 glink-edge {
2561 qcom,remote-pid = <1>;
2565 smd-edge {
2570 qcom,smd-edge = <0>;
2571 qcom,remote-pid = <1>;
2576 compatible = "arm,coresight-stm", "arm,primecell";
2579 reg-names = "stm-base", "stm-stimulus-base";
2582 clock-names = "apb_pclk", "atclk";
2584 out-ports {
2587 remote-endpoint =
2595 compatible = "arm,coresight-tpiu", "arm,primecell";
2599 clock-names = "apb_pclk", "atclk";
2601 in-ports {
2604 remote-endpoint =
2612 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2616 clock-names = "apb_pclk", "atclk";
2618 in-ports {
2619 #address-cells = <1>;
2620 #size-cells = <0>;
2625 remote-endpoint =
2631 out-ports {
2634 remote-endpoint =
2642 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2646 clock-names = "apb_pclk", "atclk";
2648 in-ports {
2649 #address-cells = <1>;
2650 #size-cells = <0>;
2655 remote-endpoint =
2661 out-ports {
2664 remote-endpoint =
2672 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2676 clock-names = "apb_pclk", "atclk";
2678 in-ports {
2681 remote-endpoint =
2687 out-ports {
2690 remote-endpoint =
2698 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2702 clock-names = "apb_pclk", "atclk";
2704 in-ports {
2705 #address-cells = <1>;
2706 #size-cells = <0>;
2711 remote-endpoint =
2719 remote-endpoint =
2727 remote-endpoint =
2733 out-ports {
2736 remote-endpoint =
2744 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2748 clock-names = "apb_pclk", "atclk";
2750 in-ports {
2753 remote-endpoint =
2759 out-ports {
2760 #address-cells = <1>;
2761 #size-cells = <0>;
2766 remote-endpoint =
2774 remote-endpoint =
2782 compatible = "arm,coresight-tmc", "arm,primecell";
2786 clock-names = "apb_pclk", "atclk";
2788 in-ports {
2791 remote-endpoint =
2797 out-ports {
2800 remote-endpoint =
2808 compatible = "arm,coresight-tmc", "arm,primecell";
2812 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather;
2815 in-ports {
2818 remote-endpoint =
2826 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2830 clock-names = "apb_pclk";
2836 compatible = "arm,coresight-etm4x", "arm,primecell";
2840 clock-names = "apb_pclk", "atclk";
2844 out-ports {
2847 remote-endpoint =
2855 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2859 clock-names = "apb_pclk";
2865 compatible = "arm,coresight-etm4x", "arm,primecell";
2869 clock-names = "apb_pclk", "atclk";
2873 out-ports {
2876 remote-endpoint =
2884 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2888 clock-names = "apb_pclk", "atclk";
2890 in-ports {
2891 #address-cells = <1>;
2892 #size-cells = <0>;
2897 remote-endpoint = <&etm0_out>;
2904 remote-endpoint = <&etm1_out>;
2909 out-ports {
2912 remote-endpoint =
2920 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2924 clock-names = "apb_pclk";
2930 compatible = "arm,coresight-etm4x", "arm,primecell";
2934 clock-names = "apb_pclk", "atclk";
2938 out-ports {
2941 remote-endpoint =
2949 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2953 clock-names = "apb_pclk";
2959 compatible = "arm,coresight-etm4x", "arm,primecell";
2963 clock-names = "apb_pclk", "atclk";
2967 out-ports {
2970 remote-endpoint =
2978 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2982 clock-names = "apb_pclk", "atclk";
2984 in-ports {
2985 #address-cells = <1>;
2986 #size-cells = <0>;
2991 remote-endpoint = <&etm2_out>;
2998 remote-endpoint = <&etm3_out>;
3003 out-ports {
3006 remote-endpoint =
3014 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3018 clock-names = "apb_pclk", "atclk";
3020 in-ports {
3021 #address-cells = <1>;
3022 #size-cells = <0>;
3027 remote-endpoint =
3035 remote-endpoint =
3041 out-ports {
3044 remote-endpoint =
3051 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,msm8996-apcc";
3055 clock-names = "xo", "sys_apcs_aux";
3058 #clock-cells = <1>;
3062 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3064 #address-cells = <1>;
3065 #size-cells = <1>;
3070 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3077 clock-names = "cfg_noc",
3083 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3085 assigned-clock-rates = <19200000>, <120000000>;
3089 interconnect-names = "usb-ddr", "apps-usb";
3091 power-domains = <&gcc USB30_GDSC>;
3099 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-threshold = /bits/ 8 <0>;
3103 snps,is-utmi-l1-suspend;
3104 snps,parkmode-disable-ss-quirk;
3105 tx-fifo-resize;
3110 compatible = "qcom,msm8996-qmp-usb3-phy";
3117 clock-names = "aux",
3121 clock-output-names = "usb3_phy_pipe_clk_src";
3122 #clock-cells = <0>;
3123 #phy-cells = <0>;
3127 reset-names = "phy",
3134 compatible = "qcom,msm8996-qusb2-phy";
3136 #phy-cells = <0>;
3140 clock-names = "cfg_ahb", "ref";
3143 nvmem-cells = <&qusb2p_hstx_trim>;
3148 compatible = "qcom,msm8996-qusb2-phy";
3150 #phy-cells = <0>;
3154 clock-names = "cfg_ahb", "ref";
3157 nvmem-cells = <&qusb2s_hstx_trim>;
3162 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3164 reg-names = "hc", "core";
3168 interrupt-names = "hc_irq", "pwr_irq";
3170 clock-names = "iface", "core", "xo";
3176 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_state_off>;
3180 bus-width = <8>;
3181 non-removable;
3186 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3188 reg-names = "hc", "core";
3192 interrupt-names = "hc_irq", "pwr_irq";
3194 clock-names = "iface", "core", "xo";
3200 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_state_off>;
3204 bus-width = <4>;
3208 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,bam-v1.7.0";
3213 clock-names = "bam_clk";
3214 qcom,controlled-remotely;
3215 #dma-cells = <1>;
3220 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3225 clock-names = "core", "iface";
3226 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_uart2_sleep>;
3230 dma-names = "tx", "rx";
3235 compatible = "qcom,spi-qup-v2.2.1";
3240 clock-names = "core", "iface";
3241 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_spi1_sleep>;
3245 dma-names = "tx", "rx";
3246 #address-cells = <1>;
3247 #size-cells = <0>;
3252 compatible = "qcom,i2c-qup-v2.2.1";
3257 clock-names = "core", "iface";
3258 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i2c3_sleep>;
3262 dma-names = "tx", "rx";
3263 #address-cells = <1>;
3264 #size-cells = <0>;
3269 compatible = "qcom,i2c-qup-v2.2.1";
3274 clock-names = "core", "iface";
3275 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i2c6_default>;
3277 pinctrl-1 = <&blsp1_i2c6_sleep>;
3279 dma-names = "tx", "rx";
3280 #address-cells = <1>;
3281 #size-cells = <0>;
3285 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,bam-v1.7.0";
3290 clock-names = "bam_clk";
3291 qcom,controlled-remotely;
3292 #dma-cells = <1>;
3297 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3302 clock-names = "core", "iface";
3307 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3312 clock-names = "core", "iface";
3317 compatible = "qcom,i2c-qup-v2.2.1";
3322 clock-names = "core", "iface";
3323 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i2c1_sleep>;
3327 dma-names = "tx", "rx";
3328 #address-cells = <1>;
3329 #size-cells = <0>;
3334 compatible = "qcom,i2c-qup-v2.2.1";
3339 clock-names = "core", "iface";
3340 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i2c2_sleep>;
3344 dma-names = "tx", "rx";
3345 #address-cells = <1>;
3346 #size-cells = <0>;
3351 compatible = "qcom,i2c-qup-v2.2.1";
3356 clock-names = "core", "iface";
3357 clock-frequency = <400000>;
3358 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i2c3_sleep>;
3362 dma-names = "tx", "rx";
3363 #address-cells = <1>;
3364 #size-cells = <0>;
3369 compatible = "qcom,i2c-qup-v2.2.1";
3374 clock-names = "core", "iface";
3375 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i2c5_default>;
3378 dma-names = "tx", "rx";
3379 #address-cells = <1>;
3380 #size-cells = <0>;
3385 compatible = "qcom,i2c-qup-v2.2.1";
3390 clock-names = "core", "iface";
3391 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i2c6_sleep>;
3395 dma-names = "tx", "rx";
3396 #address-cells = <1>;
3397 #size-cells = <0>;
3402 compatible = "qcom,spi-qup-v2.2.1";
3407 clock-names = "core", "iface";
3408 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_spi6_sleep>;
3412 dma-names = "tx", "rx";
3413 #address-cells = <1>;
3414 #size-cells = <0>;
3419 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3421 #address-cells = <1>;
3422 #size-cells = <1>;
3428 interrupt-names = "pwr_event",
3437 clock-names = "cfg_noc",
3443 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3445 assigned-clock-rates = <19200000>, <60000000>;
3447 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-pipe-clk;
3456 phy-names = "usb2-phy";
3457 maximum-speed = "high-speed";
3463 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remotely;
3467 num-channels = <31>;
3469 #dma-cells = <1>;
3471 qcom,num-ees = <2>;
3474 slim_msm: slim-ngd@91c0000 {
3475 compatible = "qcom,slim-ngd-v1.5.0";
3479 dma-names = "rx", "tx";
3480 #address-cells = <1>;
3481 #size-cells = <0>;
3487 compatible = "qcom,msm8996-adsp-pil";
3490 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3495 interrupt-names = "wdog", "fatal", "ready",
3496 "handover", "stop-ack";
3499 clock-names = "xo";
3501 memory-region = <&adsp_mem>;
3503 qcom,smem-states = <&adsp_smp2p_out 0>;
3504 qcom,smem-state-names = "stop";
3506 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = "cx";
3511 glink-edge {
3514 qcom,remote-pid = <2>;
3519 smd-edge {
3524 qcom,smd-edge = <1>;
3525 qcom,remote-pid = <2>;
3528 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compatible = "qcom,apr-v2";
3530 qcom,smd-channels = "apr_audio_svc";
3532 #address-cells = <1>;
3533 #size-cells = <0>;
3544 compatible = "qcom,q6afe-dais";
3545 #address-cells = <1>;
3546 #size-cells = <0>;
3547 #sound-dai-cells = <1>;
3558 compatible = "qcom,q6asm-dais";
3559 #address-cells = <1>;
3560 #size-cells = <0>;
3561 #sound-dai-cells = <1>;
3570 compatible = "qcom,q6adm-routing";
3571 #sound-dai-cells = <0>;
3578 qcom,smd-channels = "fastrpcsmd-apps-dsp";
3580 qcom,non-secure-domain;
3581 #address-cells = <1>;
3582 #size-cells = <0>;
3585 compatible = "qcom,fastrpc-compute-cb";
3591 compatible = "qcom,fastrpc-compute-cb";
3597 compatible = "qcom,fastrpc-compute-cb";
3603 compatible = "qcom,fastrpc-compute-cb";
3609 compatible = "qcom,fastrpc-compute-cb";
3615 compatible = "qcom,fastrpc-compute-cb";
3621 compatible = "qcom,fastrpc-compute-cb";
3627 compatible = "qcom,fastrpc-compute-cb";
3636 compatible = "qcom,msm8996-apcs-hmss-global";
3639 #mbox-cells = <1>;
3640 #clock-cells = <0>;
3644 #address-cells = <1>;
3645 #size-cells = <1>;
3647 compatible = "arm,armv7-timer-mem";
3649 clock-frequency = <19200000>;
3652 frame-number = <0>;
3660 frame-number = <1>;
3667 frame-number = <2>;
3674 frame-number = <3>;
3681 frame-number = <4>;
3688 frame-number = <5>;
3695 frame-number = <6>;
3707 cbf: clock-controller@9a11000 {
3708 compatible = "qcom,msm8996-cbf";
3711 #clock-cells = <0>;
3712 #interconnect-cells = <1>;
3715 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3>;
3718 interrupt-controller;
3719 #redistributor-regions = <1>;
3720 redistributor-stride = <0x0 0x40000>;
3730 thermal-zones {
3731 cpu0-thermal {
3732 polling-delay-passive = <250>;
3734 thermal-sensors = <&tsens0 3>;
3737 cpu0_alert0: trip-point0 {
3743 cpu0_crit: cpu-crit {
3751 cpu1-thermal {
3752 polling-delay-passive = <250>;
3754 thermal-sensors = <&tsens0 5>;
3757 cpu1_alert0: trip-point0 {
3763 cpu1_crit: cpu-crit {
3771 cpu2-thermal {
3772 polling-delay-passive = <250>;
3774 thermal-sensors = <&tsens0 8>;
3777 cpu2_alert0: trip-point0 {
3783 cpu2_crit: cpu-crit {
3791 cpu3-thermal {
3792 polling-delay-passive = <250>;
3794 thermal-sensors = <&tsens0 10>;
3797 cpu3_alert0: trip-point0 {
3803 cpu3_crit: cpu-crit {
3811 gpu-top-thermal {
3812 polling-delay-passive = <250>;
3814 thermal-sensors = <&tsens1 6>;
3817 gpu1_alert0: trip-point0 {
3824 cooling-maps {
3827 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3832 gpu-bottom-thermal {
3833 polling-delay-passive = <250>;
3835 thermal-sensors = <&tsens1 7>;
3838 gpu2_alert0: trip-point0 {
3845 cooling-maps {
3848 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3853 m4m-thermal {
3854 polling-delay-passive = <250>;
3856 thermal-sensors = <&tsens0 1>;
3859 m4m_alert0: trip-point0 {
3867 l3-or-venus-thermal {
3868 polling-delay-passive = <250>;
3870 thermal-sensors = <&tsens0 2>;
3873 l3_or_venus_alert0: trip-point0 {
3881 cluster0-l2-thermal {
3882 polling-delay-passive = <250>;
3884 thermal-sensors = <&tsens0 7>;
3887 cluster0_l2_alert0: trip-point0 {
3895 cluster1-l2-thermal {
3896 polling-delay-passive = <250>;
3898 thermal-sensors = <&tsens0 12>;
3901 cluster1_l2_alert0: trip-point0 {
3909 camera-thermal {
3910 polling-delay-passive = <250>;
3912 thermal-sensors = <&tsens1 1>;
3915 camera_alert0: trip-point0 {
3923 q6-dsp-thermal {
3924 polling-delay-passive = <250>;
3926 thermal-sensors = <&tsens1 2>;
3929 q6_dsp_alert0: trip-point0 {
3937 mem-thermal {
3938 polling-delay-passive = <250>;
3940 thermal-sensors = <&tsens1 3>;
3943 mem_alert0: trip-point0 {
3951 modemtx-thermal {
3952 polling-delay-passive = <250>;
3954 thermal-sensors = <&tsens1 4>;
3957 modemtx_alert0: trip-point0 {
3967 compatible = "arm,armv8-timer";