Lines Matching +full:tcsr +full:- +full:mutex
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&l2_0>;
52 l2_0: l2-cache {
54 cache-level = <2>;
55 cache-unified;
61 compatible = "arm,cortex-a53";
63 enable-method = "psci";
64 next-level-cache = <&l2_0>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 next-level-cache = <&l2_0>;
77 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 next-level-cache = <&l2_0>;
85 compatible = "arm,cortex-a57";
87 enable-method = "psci";
88 next-level-cache = <&l2_1>;
89 l2_1: l2-cache {
91 cache-level = <2>;
92 cache-unified;
98 compatible = "arm,cortex-a57";
100 enable-method = "psci";
101 next-level-cache = <&l2_1>;
106 compatible = "arm,cortex-a57";
108 enable-method = "psci";
109 next-level-cache = <&l2_1>;
114 compatible = "arm,cortex-a57";
116 enable-method = "psci";
117 next-level-cache = <&l2_1>;
120 cpu-map {
161 compatible = "qcom,scm-msm8994", "qcom,scm";
172 compatible = "arm,cortex-a53-pmu";
177 compatible = "arm,psci-0.2";
182 compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc";
184 smd-edge {
187 qcom,smd-edge = <15>;
188 qcom,remote-pid = <6>;
190 rpm_requests: rpm-requests {
191 compatible = "qcom,rpm-msm8994", "qcom,smd-rpm";
192 qcom,smd-channels = "rpm_requests";
194 rpmcc: clock-controller {
195 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
196 #clock-cells = <1>;
199 rpmpd: power-controller {
200 compatible = "qcom,msm8994-rpmpd";
201 #power-domain-cells = <1>;
202 operating-points-v2 = <&rpmpd_opp_table>;
204 rpmpd_opp_table: opp-table {
205 compatible = "operating-points-v2";
208 opp-level = <1>;
211 opp-level = <2>;
214 opp-level = <3>;
217 opp-level = <4>;
220 opp-level = <5>;
223 opp-level = <6>;
231 reserved-memory {
232 #address-cells = <2>;
233 #size-cells = <2>;
236 dfps_data_mem: dfps-data@3400000 {
238 no-map;
243 no-map;
248 no-map;
253 no-map;
258 no-map;
262 compatible = "qcom,rmtfs-mem";
264 no-map;
266 qcom,client-id = <1>;
271 no-map;
276 no-map;
281 no-map;
286 no-map;
292 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_ram>;
297 smp2p-lpass {
305 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>;
308 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells = <1>;
313 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "slave-kernel";
316 interrupt-controller;
317 #interrupt-cells = <2>;
321 smp2p-modem {
325 interrupt-parent = <&intc>;
330 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>;
333 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells = <1>;
338 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "slave-kernel";
341 interrupt-controller;
342 #interrupt-cells = <2>;
347 #address-cells = <1>;
348 #size-cells = <1>;
350 compatible = "simple-bus";
352 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm-qgic2";
354 interrupt-controller;
355 #interrupt-cells = <3>;
361 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
363 #mbox-cells = <1>;
367 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
372 timeout-sec = <10>;
376 #address-cells = <1>;
377 #size-cells = <1>;
379 compatible = "arm,armv7-timer-mem";
383 frame-number = <0>;
391 frame-number = <1>;
398 frame-number = <2>;
405 frame-number = <3>;
412 frame-number = <4>;
419 frame-number = <5>;
426 frame-number = <6>;
434 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
436 #address-cells = <1>;
437 #size-cells = <1>;
444 interrupt-names = "pwr_event",
453 clock-names = "core",
458 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
460 assigned-clock-rates = <19200000>, <120000000>;
462 power-domains = <&gcc USB30_GDSC>;
463 qcom,select-utmi-as-pipe-clk;
471 maximum-speed = "high-speed";
477 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
479 reg-names = "hc", "core";
483 interrupt-names = "hc_irq", "pwr_irq";
488 clock-names = "iface", "core", "xo";
490 pinctrl-names = "default", "sleep";
491 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
492 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
494 bus-width = <8>;
495 non-removable;
500 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
502 reg-names = "hc", "core";
506 interrupt-names = "hc_irq", "pwr_irq";
511 clock-names = "iface", "core", "xo";
513 pinctrl-names = "default", "sleep";
514 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
515 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
517 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
518 bus-width = <4>;
522 blsp1_dma: dma-controller@f9904000 {
523 compatible = "qcom,bam-v1.7.0";
527 clock-names = "bam_clk";
528 #dma-cells = <1>;
530 qcom,controlled-remotely;
531 num-channels = <24>;
532 qcom,num-ees = <4>;
536 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
539 clock-names = "core", "iface";
542 pinctrl-names = "default", "sleep";
543 pinctrl-0 = <&blsp1_uart2_default>;
544 pinctrl-1 = <&blsp1_uart2_sleep>;
549 compatible = "qcom,i2c-qup-v2.2.1";
554 clock-names = "core", "iface";
555 clock-frequency = <400000>;
557 dma-names = "tx", "rx";
558 pinctrl-names = "default", "sleep";
559 pinctrl-0 = <&i2c1_default>;
560 pinctrl-1 = <&i2c1_sleep>;
561 #address-cells = <1>;
562 #size-cells = <0>;
567 compatible = "qcom,spi-qup-v2.2.1";
572 clock-names = "core", "iface";
574 dma-names = "tx", "rx";
575 pinctrl-names = "default", "sleep";
576 pinctrl-0 = <&blsp1_spi1_default>;
577 pinctrl-1 = <&blsp1_spi1_sleep>;
578 #address-cells = <1>;
579 #size-cells = <0>;
584 compatible = "qcom,i2c-qup-v2.2.1";
589 clock-names = "core", "iface";
590 clock-frequency = <400000>;
592 dma-names = "tx", "rx";
593 pinctrl-names = "default", "sleep";
594 pinctrl-0 = <&i2c2_default>;
595 pinctrl-1 = <&i2c2_sleep>;
596 #address-cells = <1>;
597 #size-cells = <0>;
604 compatible = "qcom,i2c-qup-v2.2.1";
609 clock-names = "core", "iface";
610 clock-frequency = <400000>;
612 dma-names = "tx", "rx";
613 pinctrl-names = "default", "sleep";
614 pinctrl-0 = <&i2c4_default>;
615 pinctrl-1 = <&i2c4_sleep>;
616 #address-cells = <1>;
617 #size-cells = <0>;
622 compatible = "qcom,i2c-qup-v2.2.1";
627 clock-names = "core", "iface";
628 clock-frequency = <400000>;
630 dma-names = "tx", "rx";
631 pinctrl-names = "default", "sleep";
632 pinctrl-0 = <&i2c5_default>;
633 pinctrl-1 = <&i2c5_sleep>;
634 #address-cells = <1>;
635 #size-cells = <0>;
640 compatible = "qcom,i2c-qup-v2.2.1";
645 clock-names = "core", "iface";
646 clock-frequency = <400000>;
648 dma-names = "tx", "rx";
649 pinctrl-names = "default", "sleep";
650 pinctrl-0 = <&i2c6_default>;
651 pinctrl-1 = <&i2c6_sleep>;
652 #address-cells = <1>;
653 #size-cells = <0>;
657 blsp2_dma: dma-controller@f9944000 {
658 compatible = "qcom,bam-v1.7.0";
662 clock-names = "bam_clk";
663 #dma-cells = <1>;
665 qcom,controlled-remotely;
666 num-channels = <24>;
667 qcom,num-ees = <4>;
671 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
674 clock-names = "core", "iface";
678 dma-names = "tx", "rx";
679 pinctrl-names = "default", "sleep";
680 pinctrl-0 = <&blsp2_uart2_default>;
681 pinctrl-1 = <&blsp2_uart2_sleep>;
686 compatible = "qcom,i2c-qup-v2.2.1";
691 clock-names = "core", "iface";
692 clock-frequency = <400000>;
694 dma-names = "tx", "rx";
695 pinctrl-names = "default", "sleep";
696 pinctrl-0 = <&i2c7_default>;
697 pinctrl-1 = <&i2c7_sleep>;
698 #address-cells = <1>;
699 #size-cells = <0>;
704 compatible = "qcom,spi-qup-v2.2.1";
709 clock-names = "core", "iface";
711 dma-names = "tx", "rx";
712 pinctrl-names = "default", "sleep";
713 pinctrl-0 = <&blsp2_spi10_default>;
714 pinctrl-1 = <&blsp2_spi10_sleep>;
715 #address-cells = <1>;
716 #size-cells = <0>;
721 compatible = "qcom,i2c-qup-v2.2.1";
726 clock-names = "core", "iface";
727 clock-frequency = <355000>;
729 dma-names = "tx", "rx";
730 pinctrl-names = "default", "sleep";
731 pinctrl-0 = <&i2c11_default>;
732 pinctrl-1 = <&i2c11_sleep>;
733 #address-cells = <1>;
734 #size-cells = <0>;
738 gcc: clock-controller@fc400000 {
739 compatible = "qcom,gcc-msm8994";
740 #clock-cells = <1>;
741 #reset-cells = <1>;
742 #power-domain-cells = <1>;
745 clock-names = "xo", "sleep";
750 compatible = "qcom,rpm-msg-ram";
760 compatible = "qcom,spmi-pmic-arb";
764 reg-names = "core", "intr", "cnfg";
765 interrupt-names = "periph_irq";
769 #address-cells = <2>;
770 #size-cells = <0>;
771 interrupt-controller;
772 #interrupt-cells = <4>;
776 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
778 #hwlock-cells = <1>;
782 compatible = "qcom,msm8994-pinctrl";
785 gpio-controller;
786 gpio-ranges = <&tlmm 0 0 146>;
787 #gpio-cells = <2>;
788 interrupt-controller;
789 #interrupt-cells = <2>;
791 blsp1_uart2_default: blsp1-uart2-default-state {
794 drive-strength = <16>;
795 bias-disable;
798 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
801 drive-strength = <2>;
802 bias-pull-down;
805 blsp2_uart2_default: blsp2-uart2-default-state {
808 drive-strength = <16>;
809 bias-disable;
812 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
815 drive-strength = <2>;
816 bias-disable;
819 i2c1_default: i2c1-default-state {
822 drive-strength = <2>;
823 bias-disable;
826 i2c1_sleep: i2c1-sleep-state {
829 drive-strength = <2>;
830 bias-disable;
833 i2c2_default: i2c2-default-state {
836 drive-strength = <2>;
837 bias-disable;
840 i2c2_sleep: i2c2-sleep-state {
843 drive-strength = <2>;
844 bias-disable;
847 i2c4_default: i2c4-default-state {
850 drive-strength = <2>;
851 bias-disable;
854 i2c4_sleep: i2c4-sleep-state {
857 drive-strength = <2>;
858 bias-pull-down;
861 i2c5_default: i2c5-default-state {
864 drive-strength = <2>;
865 bias-disable;
868 i2c5_sleep: i2c5-sleep-state {
871 drive-strength = <2>;
872 bias-disable;
875 i2c6_default: i2c6-default-state {
878 drive-strength = <2>;
879 bias-disable;
882 i2c6_sleep: i2c6-sleep-state {
885 drive-strength = <2>;
886 bias-disable;
889 i2c7_default: i2c7-default-state {
892 drive-strength = <2>;
893 bias-disable;
896 i2c7_sleep: i2c7-sleep-state {
899 drive-strength = <2>;
900 bias-disable;
903 blsp2_spi10_default: blsp2-spi10-default-state {
904 default-pins {
907 drive-strength = <10>;
908 bias-pull-down;
911 cs-pins {
914 drive-strength = <2>;
915 bias-disable;
919 blsp2_spi10_sleep: blsp2-spi10-sleep-state {
922 drive-strength = <2>;
923 bias-disable;
926 i2c11_default: i2c11-default-state {
929 drive-strength = <2>;
930 bias-disable;
933 i2c11_sleep: i2c11-sleep-state {
936 drive-strength = <2>;
937 bias-disable;
940 blsp1_spi1_default: blsp1-spi1-default-state {
941 default-pins {
944 drive-strength = <10>;
945 bias-pull-down;
948 cs-pins {
951 drive-strength = <2>;
952 bias-disable;
956 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
959 drive-strength = <2>;
960 bias-disable;
963 sdc1_clk_on: clk-on-state {
965 bias-disable;
966 drive-strength = <16>;
969 sdc1_clk_off: clk-off-state {
971 bias-disable;
972 drive-strength = <2>;
975 sdc1_cmd_on: cmd-on-state {
977 bias-pull-up;
978 drive-strength = <8>;
981 sdc1_cmd_off: cmd-off-state {
983 bias-pull-up;
984 drive-strength = <2>;
987 sdc1_data_on: data-on-state {
989 bias-pull-up;
990 drive-strength = <8>;
993 sdc1_data_off: data-off-state {
995 bias-pull-up;
996 drive-strength = <2>;
999 sdc1_rclk_on: rclk-on-state {
1001 bias-pull-down;
1004 sdc1_rclk_off: rclk-off-state {
1006 bias-pull-down;
1009 sdc2_clk_on: sdc2-clk-on-state {
1011 bias-disable;
1012 drive-strength = <10>;
1015 sdc2_clk_off: sdc2-clk-off-state {
1017 bias-disable;
1018 drive-strength = <2>;
1021 sdc2_cmd_on: sdc2-cmd-on-state {
1023 bias-pull-up;
1024 drive-strength = <10>;
1027 sdc2_cmd_off: sdc2-cmd-off-state {
1029 bias-pull-up;
1030 drive-strength = <2>;
1033 sdc2_data_on: sdc2-data-on-state {
1035 bias-pull-up;
1036 drive-strength = <10>;
1039 sdc2_data_off: sdc2-data-off-state {
1041 bias-pull-up;
1042 drive-strength = <2>;
1046 mmcc: clock-controller@fd8c0000 {
1047 compatible = "qcom,mmcc-msm8994";
1049 #clock-cells = <1>;
1050 #reset-cells = <1>;
1051 #power-domain-cells = <1>;
1053 clock-names = "xo",
1072 assigned-clocks = <&mmcc MMPLL0_PLL>,
1077 assigned-clock-rates = <800000000>,
1085 compatible = "qcom,msm8974-ocmem";
1088 reg-names = "ctrl", "mem";
1092 clock-names = "core", "iface";
1094 #address-cells = <1>;
1095 #size-cells = <1>;
1097 gmu_sram: gmu-sram@0 {
1104 compatible = "arm,armv8-timer";
1111 vph_pwr: vph-pwr-regulator {
1112 compatible = "regulator-fixed";
1113 regulator-name = "vph_pwr";
1115 regulator-min-microvolt = <3600000>;
1116 regulator-max-microvolt = <3600000>;
1118 regulator-always-on;