Lines Matching refs:gcc
10 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
210 clocks = <&gcc GCC_CRYPTO_CLK>,
211 <&gcc GCC_CRYPTO_AXI_CLK>,
212 <&gcc GCC_CRYPTO_AHB_CLK>;
476 clocks = <&gcc GCC_PRNG_AHB_CLK>;
490 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
491 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
493 resets = <&gcc RST_QUSB2_PHY_BCR>,
494 <&gcc RST_USB2_HS_PHY_ONLY_BCR>;
852 gcc: clock-controller@1800000 { label
853 compatible = "qcom,gcc-msm8976";
859 assigned-clocks = <&gcc GPLL3>;
894 power-domains = <&gcc MDSS_GDSC>;
900 clocks = <&gcc GCC_MDSS_AHB_CLK>,
901 <&gcc GCC_MDSS_AXI_CLK>,
902 <&gcc GCC_MDSS_VSYNC_CLK>,
903 <&gcc GCC_MDSS_MDP_CLK>;
923 clocks = <&gcc GCC_MDSS_AHB_CLK>,
924 <&gcc GCC_MDSS_AXI_CLK>,
925 <&gcc GCC_MDSS_MDP_CLK>,
926 <&gcc GCC_MDSS_VSYNC_CLK>,
927 <&gcc GCC_MDP_TBU_CLK>,
928 <&gcc GCC_MDP_RT_TBU_CLK>;
937 power-domains = <&gcc MDSS_GDSC>;
995 clocks = <&gcc GCC_MDSS_MDP_CLK>,
996 <&gcc GCC_MDSS_AHB_CLK>,
997 <&gcc GCC_MDSS_AXI_CLK>,
998 <&gcc GCC_MDSS_BYTE0_CLK>,
999 <&gcc GCC_MDSS_PCLK0_CLK>,
1000 <&gcc GCC_MDSS_ESC0_CLK>;
1008 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
1009 <&gcc GCC_MDSS_PCLK0_CLK_SRC>;
1016 power-domains = <&gcc MDSS_GDSC>;
1071 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1072 <&gcc GCC_MDSS_AHB_CLK>,
1073 <&gcc GCC_MDSS_AXI_CLK>,
1074 <&gcc GCC_MDSS_BYTE1_CLK>,
1075 <&gcc GCC_MDSS_PCLK1_CLK>,
1076 <&gcc GCC_MDSS_ESC1_CLK>;
1084 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
1085 <&gcc GCC_MDSS_PCLK1_CLK_SRC>;
1092 power-domains = <&gcc MDSS_GDSC>;
1132 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1151 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1168 clocks = <&gcc GCC_GFX3D_OXILI_CLK>,
1169 <&gcc GCC_GFX3D_OXILI_AHB_CLK>,
1170 <&gcc GCC_GFX3D_OXILI_GMEM_CLK>,
1171 <&gcc GCC_GFX3D_BIMC_CLK>,
1172 <&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
1173 <&gcc GCC_GFX3D_OXILI_AON_CLK>;
1181 power-domains = <&gcc OXILI_GX_GDSC>;
1235 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1236 <&gcc GCC_APSS_TCU_CLK>;
1274 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1275 <&gcc GCC_GFX3D_TCU_CLK>;
1278 power-domains = <&gcc OXILI_CX_GDSC>;
1339 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1340 <&gcc GCC_SDCC1_APPS_CLK>,
1355 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1356 <&gcc GCC_SDCC2_APPS_CLK>,
1366 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1377 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1388 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1399 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1415 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1432 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1451 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>;
1453 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1455 resets = <&gcc RST_USB_HS_BCR>;
1475 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
1476 <&gcc GCC_SDCC3_APPS_CLK>,
1487 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1498 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1509 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1526 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;