Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board: xo-board {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 cpu-idle-states = <&little_cpu_sleep_0>;
41 capacity-dmips-mhz = <573>;
42 next-level-cache = <&l2_0>;
43 #cooling-cells = <2>;
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 cpu-idle-states = <&little_cpu_sleep_0>;
52 capacity-dmips-mhz = <573>;
53 next-level-cache = <&l2_0>;
54 #cooling-cells = <2>;
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 cpu-idle-states = <&little_cpu_sleep_0>;
63 capacity-dmips-mhz = <573>;
64 next-level-cache = <&l2_0>;
65 #cooling-cells = <2>;
70 compatible = "arm,cortex-a53";
72 enable-method = "psci";
73 cpu-idle-states = <&little_cpu_sleep_0>;
74 capacity-dmips-mhz = <573>;
75 next-level-cache = <&l2_0>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a72";
83 enable-method = "psci";
84 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
85 capacity-dmips-mhz = <1024>;
86 next-level-cache = <&l2_1>;
87 #cooling-cells = <2>;
92 compatible = "arm,cortex-a72";
94 enable-method = "psci";
95 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
96 capacity-dmips-mhz = <1024>;
97 next-level-cache = <&l2_1>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a72";
105 enable-method = "psci";
106 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
107 capacity-dmips-mhz = <1024>;
108 next-level-cache = <&l2_1>;
109 #cooling-cells = <2>;
114 compatible = "arm,cortex-a72";
116 enable-method = "psci";
117 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
118 capacity-dmips-mhz = <1024>;
119 next-level-cache = <&l2_1>;
120 #cooling-cells = <2>;
123 cpu-map {
161 idle-states {
162 entry-method = "psci";
164 little_cpu_sleep_0: cpu-sleep-0-0 {
165 compatible = "arm,idle-state";
166 idle-state-name = "little-power-collapse";
167 arm,psci-suspend-param = <0x40000003>;
168 entry-latency-us = <181>;
169 exit-latency-us = <149>;
170 min-residency-us = <703>;
171 local-timer-stop;
174 big_cpu_sleep_0: cpu-sleep-1-0 {
175 compatible = "arm,idle-state";
176 idle-state-name = "big-retention";
177 arm,psci-suspend-param = <0x00000002>;
178 entry-latency-us = <142>;
179 exit-latency-us = <99>;
180 min-residency-us = <242>;
183 big_cpu_sleep_1: cpu-sleep-1-1 {
184 compatible = "arm,idle-state";
185 idle-state-name = "big-power-collapse";
186 arm,psci-suspend-param = <0x40000003>;
187 entry-latency-us = <158>;
188 exit-latency-us = <144>;
189 min-residency-us = <863>;
190 local-timer-stop;
194 l2_0: l2-cache0 {
196 cache-level = <2>;
197 cache-unified;
200 l2_1: l2-cache1 {
202 cache-level = <2>;
203 cache-unified;
209 compatible = "qcom,scm-msm8976", "qcom,scm";
213 clock-names = "core", "bus", "iface";
214 #reset-cells = <1>;
216 qcom,dload-mode = <&tcsr 0x6100>;
226 pmu-a53 {
227 compatible = "arm,cortex-a53-pmu";
231 pmu_a72: pmu-a72 {
232 compatible = "arm,cortex-a72-pmu";
237 psci {
238 compatible = "arm,psci-1.0";
243 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
245 smd-edge {
248 qcom,smd-edge = <15>;
250 rpm_requests: rpm-requests {
251 compatible = "qcom,rpm-msm8976", "qcom,smd-rpm";
252 qcom,smd-channels = "rpm_requests";
254 rpmcc: clock-controller {
255 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
257 clock-names = "xo";
258 #clock-cells = <1>;
261 rpmpd: power-controller {
262 compatible = "qcom,msm8976-rpmpd";
263 #power-domain-cells = <1>;
264 operating-points-v2 = <&rpmpd_opp_table>;
266 rpmpd_opp_table: opp-table {
267 compatible = "operating-points-v2";
270 opp-level = <RPM_SMD_LEVEL_RETENTION>;
274 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
278 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
282 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
286 opp-level = <RPM_SMD_LEVEL_SVS>;
290 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
294 opp-level = <RPM_SMD_LEVEL_NOM>;
298 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
302 opp-level = <RPM_SMD_LEVEL_TURBO>;
306 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
310 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
318 reserved-memory {
319 #address-cells = <2>;
320 #size-cells = <2>;
323 ext-region@85b00000 {
325 no-map;
331 no-map;
334 qcom,rpm-msg-ram = <&rpm_msg_ram>;
339 no-map;
344 no-map;
349 no-map;
354 no-map;
359 no-map;
362 tz-apps@8dd00000 {
364 no-map;
368 smp2p-hexagon {
373 qcom,local-pid = <0>;
374 qcom,remote-pid = <2>;
377 adsp_smp2p_out: master-kernel {
378 qcom,entry-name = "master-kernel";
380 #qcom,smem-state-cells = <1>;
383 adsp_smp2p_in: slave-kernel {
384 qcom,entry-name = "slave-kernel";
386 interrupt-controller;
387 #interrupt-cells = <2>;
391 smp2p-modem {
396 qcom,local-pid = <0>;
397 qcom,remote-pid = <1>;
400 modem_smp2p_out: master-kernel {
401 qcom,entry-name = "master-kernel";
403 #qcom,smem-state-cells = <1>;
406 modem_smp2p_in: slave-kernel {
407 qcom,entry-name = "slave-kernel";
409 interrupt-controller;
410 #interrupt-cells = <2>;
414 smp2p-wcnss {
419 qcom,local-pid = <0>;
420 qcom,remote-pid = <4>;
423 wcnss_smp2p_out: master-kernel {
424 qcom,entry-name = "master-kernel";
426 #qcom,smem-state-cells = <1>;
429 wcnss_smp2p_in: slave-kernel {
430 qcom,entry-name = "slave-kernel";
432 interrupt-controller;
433 #interrupt-cells = <2>;
440 #address-cells = <1>;
441 #size-cells = <0>;
447 #qcom,smem-state-cells = <1>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
468 #address-cells = <1>;
469 #size-cells = <1>;
471 compatible = "simple-bus";
477 clock-names = "core";
481 compatible = "qcom,rpm-msg-ram";
486 compatible = "qcom,usb-hs-28nm-femtophy";
488 #phy-cells = <0>;
492 clock-names = "ref", "ahb", "sleep";
495 reset-names = "phy", "por";
500 compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
502 #address-cells = <1>;
503 #size-cells = <1>;
510 tsens_s0_p1: s0-p1@219 {
515 tsens_s0_p2: s0-p2@219 {
520 tsens_s1_p1: s1-p1@21a {
525 tsens_s1_p2: s1-p2@21b {
530 tsens_s2_p1: s2-p1@21c {
535 tsens_s2_p2: s2-p2@21c {
540 tsens_s3_p1: s3-p1@21d {
545 tsens_s3_p2: s3-p2@21e {
555 tsens_s4_p1: s4-p1@221 {
560 tsens_s4_p2: s4-p2@221 {
565 tsens_s5_p1: s5-p1@222 {
570 tsens_s5_p2: s5-p2@223 {
575 tsens_s6_p1: s6-p1@224 {
580 tsens_s6_p2: s6-p2@224 {
585 tsens_s7_p1: s7-p1@225 {
590 tsens_s7_p2: s7-p2@226 {
600 tsens_s8_p1: s8-p1@228 {
605 tsens_s8_p2: s8-p2@229 {
610 tsens_s9_p1: s9-p1@229 {
615 tsens_s9_p2: s9-p2@22a {
620 tsens_s10_p1: s10-p1@22b {
625 tsens_s10_p2: s10-p2@22c {
631 tsens: thermal-sensor@4a9000 {
632 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
636 interrupt-names = "uplow";
637 nvmem-cells = <&tsens_mode>,
650 nvmem-cell-names = "mode",
664 #thermal-sensor-cells = <1>;
673 compatible = "qcom,msm8976-pinctrl";
676 #gpio-cells = <2>;
677 gpio-controller;
678 gpio-ranges = <&tlmm 0 0 145>;
679 interrupt-controller;
680 #interrupt-cells = <2>;
682 spi1_default: spi0-default-state {
683 spi-pins {
686 drive-strength = <12>;
687 bias-disable;
690 cs-pins {
693 drive-strength = <2>;
694 bias-disable;
698 spi1_sleep: spi0-sleep-state {
699 spi-pins {
702 drive-strength = <2>;
703 bias-pull-down;
706 cs-pins {
709 drive-strength = <2>;
710 bias-disable;
714 blsp1_i2c2_default: blsp1-i2c2-default-state {
717 drive-strength = <2>;
718 bias-disable;
721 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
724 drive-strength = <2>;
725 bias-disable;
728 blsp1_i2c4_default: blsp1-i2c4-default-state {
731 drive-strength = <2>;
732 bias-disable;
735 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
738 drive-strength = <2>;
739 bias-disable;
742 blsp2_uart2_active: blsp2-uart2-active-state {
745 drive-strength = <4>;
746 bias-disable;
749 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
752 drive-strength = <2>;
753 bias-disable;
757 blsp2_i2c2_default: blsp2-i2c2-default-state {
760 drive-strength = <2>;
761 bias-disable;
764 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
767 drive-strength = <2>;
768 bias-disable;
771 blsp2_i2c4_default: blsp2-i2c4-default-state {
774 drive-strength = <2>;
775 bias-disable;
778 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
781 drive-strength = <2>;
782 bias-disable;
785 sdc2_default: sdc2-default-state {
786 clk-pins {
788 bias-disable;
789 drive-strength = <16>;
791 cmd-pins {
793 bias-pull-up;
794 drive-strength = <10>;
796 data-pins {
798 bias-pull-up;
799 drive-strength = <10>;
803 sdc2_sleep: sdc2-sleep-state {
804 clk-pins {
806 bias-disable;
807 drive-strength = <2>;
809 cmd-pins {
811 bias-pull-up;
812 drive-strength = <2>;
814 data-pins {
816 bias-pull-up;
817 drive-strength = <2>;
821 wcss_wlan_default: wcss-wlan-default-state {
822 wcss-wlan2-pins {
825 drive-strength = <6>;
826 bias-pull-up;
829 wcss-wlan1-pins {
832 drive-strength = <6>;
833 bias-pull-up;
836 wcss-wlan0-pins {
839 drive-strength = <6>;
840 bias-pull-up;
843 wcss-wlan-pins {
846 drive-strength = <6>;
847 bias-pull-up;
852 gcc: clock-controller@1800000 {
853 compatible = "qcom,gcc-msm8976";
855 #clock-cells = <1>;
856 #reset-cells = <1>;
857 #power-domain-cells = <1>;
859 assigned-clocks = <&gcc GPLL3>;
860 assigned-clock-rates = <1100000000>;
868 clock-names = "xo",
877 compatible = "qcom,tcsr-mutex";
879 #hwlock-cells = <1>;
883 compatible = "qcom,msm8976-tcsr", "syscon";
887 mdss: display-subsystem@1a00000 {
892 reg-names = "mdss_phys", "vbif_phys";
894 power-domains = <&gcc MDSS_GDSC>;
897 interrupt-controller;
898 #interrupt-cells = <1>;
904 clock-names = "iface",
909 #address-cells = <1>;
910 #size-cells = <1>;
915 mdss_mdp: display-controller@1a01000 {
916 compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
918 reg-names = "mdp_phys";
920 interrupt-parent = <&mdss>;
929 clock-names = "iface",
936 operating-points-v2 = <&mdp_opp_table>;
937 power-domains = <&gcc MDSS_GDSC>;
942 #address-cells = <1>;
943 #size-cells = <0>;
949 remote-endpoint = <&mdss_dsi0_in>;
957 remote-endpoint = <&mdss_dsi1_in>;
962 mdp_opp_table: opp-table {
963 compatible = "operating-points-v2";
965 opp-177780000 {
966 opp-hz = /bits/ 64 <177780000>;
967 required-opps = <&rpmpd_opp_svs>;
970 opp-270000000 {
971 opp-hz = /bits/ 64 <270000000>;
972 required-opps = <&rpmpd_opp_svs_plus>;
975 opp-320000000 {
976 opp-hz = /bits/ 64 <320000000>;
977 required-opps = <&rpmpd_opp_nom>;
980 opp-360000000 {
981 opp-hz = /bits/ 64 <360000000>;
982 required-opps = <&rpmpd_opp_turbo>;
988 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
990 reg-names = "dsi_ctrl";
992 interrupt-parent = <&mdss>;
1001 clock-names = "mdp_core",
1008 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
1010 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1015 operating-points-v2 = <&dsi0_opp_table>;
1016 power-domains = <&gcc MDSS_GDSC>;
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1031 remote-endpoint = <&mdss_mdp5_intf1_out>;
1043 dsi0_opp_table: opp-table {
1044 compatible = "operating-points-v2";
1046 opp-125000000 {
1047 opp-hz = /bits/ 64 <125000000>;
1048 required-opps = <&rpmpd_opp_svs>;
1051 opp-161250000 {
1052 opp-hz = /bits/ 64 <161250000>;
1053 required-opps = <&rpmpd_opp_svs_plus>;
1056 opp-187500000 {
1057 opp-hz = /bits/ 64 <187500000>;
1058 required-opps = <&rpmpd_opp_nom>;
1064 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1066 reg-names = "dsi_ctrl";
1068 interrupt-parent = <&mdss>;
1077 clock-names = "mdp_core",
1084 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
1086 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
1091 operating-points-v2 = <&dsi0_opp_table>;
1092 power-domains = <&gcc MDSS_GDSC>;
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1107 remote-endpoint = <&mdss_mdp5_intf2_out>;
1121 compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
1125 reg-names = "dsi_pll",
1129 #clock-cells = <1>;
1130 #phy-cells = <0>;
1134 clock-names = "iface", "ref";
1140 compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
1144 reg-names = "dsi_pll",
1148 #clock-cells = <1>;
1149 #phy-cells = <0>;
1153 clock-names = "iface", "ref";
1160 compatible = "qcom,adreno-510.0", "qcom,adreno";
1163 reg-names = "kgsl_3d0_reg_memory";
1166 interrupt-names = "kgsl_3d0_irq";
1174 clock-names = "core",
1181 power-domains = <&gcc OXILI_GX_GDSC>;
1185 operating-points-v2 = <&gpu_opp_table>;
1189 gpu_opp_table: opp-table {
1190 compatible = "operating-points-v2";
1192 opp-200000000 {
1193 opp-hz = /bits/ 64 <200000000>;
1194 required-opps = <&rpmpd_opp_low_svs>;
1195 opp-supported-hw = <0xff>;
1198 opp-300000000 {
1199 opp-hz = /bits/ 64 <300000000>;
1200 required-opps = <&rpmpd_opp_svs>;
1201 opp-supported-hw = <0xff>;
1204 opp-400000000 {
1205 opp-hz = /bits/ 64 <400000000>;
1206 required-opps = <&rpmpd_opp_nom>;
1207 opp-supported-hw = <0xff>;
1210 opp-480000000 {
1211 opp-hz = /bits/ 64 <480000000>;
1212 required-opps = <&rpmpd_opp_nom_plus>;
1213 opp-supported-hw = <0xff>;
1216 opp-540000000 {
1217 opp-hz = /bits/ 64 <540000000>;
1218 required-opps = <&rpmpd_opp_turbo>;
1219 opp-supported-hw = <0xff>;
1222 opp-600000000 {
1223 opp-hz = /bits/ 64 <600000000>;
1224 required-opps = <&rpmpd_opp_turbo>;
1225 opp-supported-hw = <0xff>;
1231 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
1237 clock-names = "iface", "bus";
1239 qcom,iommu-secure-id = <17>;
1241 #address-cells = <1>;
1242 #size-cells = <1>;
1243 #iommu-cells = <1>;
1246 iommu-ctx@15000 {
1247 compatible = "qcom,msm-iommu-v2-ns";
1249 qcom,ctx-asid = <20>;
1254 iommu-ctx@16000 {
1255 compatible = "qcom,msm-iommu-v2-ns";
1257 qcom,ctx-asid = <21>;
1262 iommu-ctx@17000 {
1263 compatible = "qcom,msm-iommu-v2-ns";
1265 qcom,ctx-asid = <22>;
1271 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
1276 clock-names = "iface", "bus";
1278 power-domains = <&gcc OXILI_CX_GDSC>;
1280 qcom,iommu-secure-id = <18>;
1282 #address-cells = <1>;
1283 #size-cells = <1>;
1284 #iommu-cells = <1>;
1287 iommu-ctx@0 {
1288 compatible = "qcom,msm-iommu-v2-ns";
1290 qcom,ctx-asid = <0>;
1295 iommu-ctx@1000 {
1296 compatible = "qcom,msm-iommu-v2-sec";
1298 qcom,ctx-asid = <2>;
1303 iommu-ctx@2000 {
1304 compatible = "qcom,msm-iommu-v2-sec";
1306 qcom,ctx-asid = <1>;
1312 compatible = "qcom,spmi-pmic-arb";
1318 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1320 interrupt-names = "periph_irq";
1324 #address-cells = <2>;
1325 #size-cells = <0>;
1326 interrupt-controller;
1327 #interrupt-cells = <4>;
1331 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1333 reg-names = "hc", "core";
1337 interrupt-names = "hc_irq", "pwr_irq";
1342 clock-names = "iface", "core", "xo";
1347 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1349 reg-names = "hc", "core";
1353 interrupt-names = "hc_irq", "pwr_irq";
1358 clock-names = "iface", "core", "xo";
1362 blsp1_dma: dma-controller@7884000 {
1363 compatible = "qcom,bam-v1.7.0";
1367 clock-names = "bam_clk";
1368 #dma-cells = <1>;
1370 qcom,controlled-remotely;
1374 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1378 clock-names = "core", "iface";
1380 dma-names = "tx", "rx";
1385 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1389 clock-names = "core", "iface";
1391 dma-names = "tx", "rx";
1396 compatible = "qcom,spi-qup-v2.2.1";
1400 clock-names = "core", "iface";
1402 dma-names = "tx", "rx";
1403 pinctrl-names = "default", "sleep";
1404 pinctrl-0 = <&spi1_default>;
1405 pinctrl-1 = <&spi1_sleep>;
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1412 compatible = "qcom,i2c-qup-v2.2.1";
1416 clock-names = "core", "iface";
1417 clock-frequency = <400000>;
1419 dma-names = "tx", "rx";
1420 pinctrl-names = "default", "sleep";
1421 pinctrl-0 = <&blsp1_i2c2_default>;
1422 pinctrl-1 = <&blsp1_i2c2_default>;
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1429 compatible = "qcom,i2c-qup-v2.2.1";
1433 clock-names = "core", "iface";
1434 clock-frequency = <400000>;
1436 dma-names = "tx", "rx";
1437 pinctrl-names = "default", "sleep";
1438 pinctrl-0 = <&blsp1_i2c4_default>;
1439 pinctrl-1 = <&blsp1_i2c4_sleep>;
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1446 compatible = "qcom,ci-hdrc";
1452 clock-names = "iface", "core";
1453 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1454 assigned-clock-rates = <80000000>;
1456 reset-names = "core";
1457 ahb-burst-config = <0>;
1460 phy-names = "usb-phy";
1463 #reset-cells = <1>;
1467 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1469 reg-names = "hc", "core";
1473 interrupt-names = "hc_irq", "pwr_irq";
1478 clock-names = "iface", "core", "xo";
1483 blsp2_dma: dma-controller@7ac4000 {
1484 compatible = "qcom,bam-v1.7.0";
1488 clock-names = "bam_clk";
1489 #dma-cells = <1>;
1491 qcom,controlled-remotely;
1495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1499 clock-names = "core", "iface";
1501 dma-names = "tx", "rx";
1506 compatible = "qcom,i2c-qup-v2.2.1";
1510 clock-names = "core", "iface";
1511 clock-frequency = <400000>;
1513 dma-names = "tx", "rx";
1514 pinctrl-names = "default", "sleep";
1515 pinctrl-0 = <&blsp2_i2c2_default>;
1516 pinctrl-1 = <&blsp2_i2c2_sleep>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1523 compatible = "qcom,i2c-qup-v2.2.1";
1527 clock-names = "core", "iface";
1528 clock-frequency = <400000>;
1530 dma-names = "tx", "rx";
1531 pinctrl-names = "default", "sleep";
1532 pinctrl-0 = <&blsp2_i2c4_default>;
1533 pinctrl-1 = <&blsp2_i2c4_sleep>;
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1540 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1544 reg-names = "ccu",
1548 memory-region = <&wcnss_fw_mem>;
1550 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1555 interrupt-names = "wdog",
1559 "stop-ack";
1561 power-domains = <&rpmpd MSM8976_VDDCX>,
1563 power-domain-names = "cx", "mx";
1565 qcom,smem-states = <&wcnss_smp2p_out 0>;
1566 qcom,smem-state-names = "stop";
1568 pinctrl-0 = <&wcss_wlan_default>;
1569 pinctrl-names = "default";
1574 /* Separate chip, compatible is board-specific */
1576 clock-names = "xo";
1579 smd-edge {
1583 qcom,smd-edge = <6>;
1584 qcom,remote-pid = <4>;
1590 qcom,smd-channels = "WCNSS_CTRL";
1595 compatible = "qcom,wcnss-bt";
1599 compatible = "qcom,wcnss-wlan";
1603 interrupt-names = "tx", "rx";
1605 qcom,smem-states = <&apps_smsm 10>,
1607 qcom,smem-state-names = "tx-enable",
1608 "tx-rings-empty";
1614 intc: interrupt-controller@b000000 {
1615 compatible = "qcom,msm-qgic2";
1617 interrupt-controller;
1618 #interrupt-cells = <3>;
1622 compatible = "qcom,msm8976-apcs-kpss-global",
1623 "qcom,msm8994-apcs-kpss-global", "syscon";
1625 #mbox-cells = <1>;
1629 compatible = "arm,armv7-timer-mem";
1631 #address-cells = <1>;
1632 #size-cells = <1>;
1634 clock-frequency = <19200000>;
1640 frame-number = <0>;
1646 frame-number = <1>;
1653 frame-number = <2>;
1660 frame-number = <3>;
1667 frame-number = <4>;
1674 frame-number = <5>;
1681 frame-number = <6>;
1687 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
1689 #address-cells = <1>;
1690 #size-cells = <1>;
1694 pil-reloc@94c {
1695 compatible = "qcom,pil-reloc-info";
1701 thermal-zones {
1702 aoss0-thermal {
1703 polling-delay-passive = <250>;
1705 thermal-sensors = <&tsens 0>;
1708 aoss0_alert0: trip-point0 {
1716 modem-thermal {
1717 polling-delay-passive = <250>;
1719 thermal-sensors = <&tsens 1>;
1721 modem_alert0: trip-point0 {
1729 qdsp-thermal {
1730 polling-delay-passive = <250>;
1732 thermal-sensors = <&tsens 2>;
1734 qdsp_alert0: trip-point0 {
1742 cam-isp-thermal {
1743 polling-delay-passive = <250>;
1745 thermal-sensors = <&tsens 3>;
1747 cam_isp_alert0: trip-point0 {
1755 cpu4-thermal {
1756 polling-delay-passive = <250>;
1758 thermal-sensors = <&tsens 4>;
1761 cpu4_alert0: trip-point0 {
1766 cpu4_alert1: trip-point1 {
1771 cpu4_crit: cpu-crit {
1779 cpu5-thermal {
1780 polling-delay-passive = <250>;
1782 thermal-sensors = <&tsens 5>;
1785 cpu5_alert0: trip-point0 {
1790 cpu5_alert1: trip-point1 {
1795 cpu5_crit: cpu-crit {
1803 cpu6-thermal {
1804 polling-delay-passive = <250>;
1806 thermal-sensors = <&tsens 6>;
1809 cpu6_alert0: trip-point0 {
1814 cpu6_alert1: trip-point1 {
1819 cpu6_crit: cpu-crit {
1827 cpu7-thermal {
1828 polling-delay-passive = <250>;
1830 thermal-sensors = <&tsens 7>;
1833 cpu7_alert0: trip-point0 {
1838 cpu7_alert1: trip-point1 {
1843 cpu7_crit: cpu-crit {
1851 big-l2-thermal {
1852 polling-delay-passive = <250>;
1854 thermal-sensors = <&tsens 8>;
1857 l2_alert0: trip-point0 {
1862 l2_alert1: trip-point1 {
1867 l2_crit: l2-crit {
1875 cpu0-thermal {
1876 polling-delay-passive = <250>;
1878 thermal-sensors = <&tsens 9>;
1881 cpu0_alert0: trip-point0 {
1886 cpu0_alert1: trip-point1 {
1891 cpu0_crit: cpu-crit {
1899 gpu-thermal {
1900 polling-delay-passive = <250>;
1902 thermal-sensors = <&tsens 10>;
1905 gpu_alert0: trip-point0 {
1910 gpu_alert1: trip-point1 {
1915 gpu_crit: gpu-crit {
1925 compatible = "arm,armv8-timer";
1930 clock-frequency = <19200000>;