Lines Matching +full:pil +full:- +full:reloc +full:- +full:info
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 cpu-idle-states = <&little_cpu_sleep_0>;
40 capacity-dmips-mhz = <573>;
41 next-level-cache = <&l2_0>;
42 #cooling-cells = <2>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 cpu-idle-states = <&little_cpu_sleep_0>;
51 capacity-dmips-mhz = <573>;
52 next-level-cache = <&l2_0>;
53 #cooling-cells = <2>;
58 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 cpu-idle-states = <&little_cpu_sleep_0>;
62 capacity-dmips-mhz = <573>;
63 next-level-cache = <&l2_0>;
64 #cooling-cells = <2>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&little_cpu_sleep_0>;
73 capacity-dmips-mhz = <573>;
74 next-level-cache = <&l2_0>;
75 #cooling-cells = <2>;
80 compatible = "arm,cortex-a72";
82 enable-method = "psci";
83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
84 capacity-dmips-mhz = <1024>;
85 next-level-cache = <&l2_1>;
86 #cooling-cells = <2>;
91 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
95 capacity-dmips-mhz = <1024>;
96 next-level-cache = <&l2_1>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a72";
104 enable-method = "psci";
105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a72";
115 enable-method = "psci";
116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
117 capacity-dmips-mhz = <1024>;
118 next-level-cache = <&l2_1>;
119 #cooling-cells = <2>;
122 cpu-map {
160 idle-states {
161 entry-method = "psci";
163 little_cpu_sleep_0: cpu-sleep-0-0 {
164 compatible = "arm,idle-state";
165 idle-state-name = "little-power-collapse";
166 arm,psci-suspend-param = <0x40000003>;
167 entry-latency-us = <181>;
168 exit-latency-us = <149>;
169 min-residency-us = <703>;
170 local-timer-stop;
173 big_cpu_sleep_0: cpu-sleep-1-0 {
174 compatible = "arm,idle-state";
175 idle-state-name = "big-retention";
176 arm,psci-suspend-param = <0x00000002>;
177 entry-latency-us = <142>;
178 exit-latency-us = <99>;
179 min-residency-us = <242>;
182 big_cpu_sleep_1: cpu-sleep-1-1 {
183 compatible = "arm,idle-state";
184 idle-state-name = "big-power-collapse";
185 arm,psci-suspend-param = <0x40000003>;
186 entry-latency-us = <158>;
187 exit-latency-us = <144>;
188 min-residency-us = <863>;
189 local-timer-stop;
193 l2_0: l2-cache0 {
195 cache-level = <2>;
196 cache-unified;
199 l2_1: l2-cache1 {
201 cache-level = <2>;
202 cache-unified;
208 compatible = "qcom,scm-msm8976", "qcom,scm";
212 clock-names = "core", "bus", "iface";
213 #reset-cells = <1>;
215 qcom,dload-mode = <&tcsr 0x6100>;
225 pmu-a53 {
226 compatible = "arm,cortex-a53-pmu";
230 pmu_a72: pmu-a72 {
231 compatible = "arm,cortex-a72-pmu";
237 compatible = "arm,psci-1.0";
242 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
244 smd-edge {
247 qcom,smd-edge = <15>;
249 rpm_requests: rpm-requests {
250 compatible = "qcom,rpm-msm8976", "qcom,smd-rpm";
251 qcom,smd-channels = "rpm_requests";
253 rpmcc: clock-controller {
254 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
256 clock-names = "xo";
257 #clock-cells = <1>;
260 rpmpd: power-controller {
261 compatible = "qcom,msm8976-rpmpd";
262 #power-domain-cells = <1>;
263 operating-points-v2 = <&rpmpd_opp_table>;
265 rpmpd_opp_table: opp-table {
266 compatible = "operating-points-v2";
269 opp-level = <RPM_SMD_LEVEL_RETENTION>;
273 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
277 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
281 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
285 opp-level = <RPM_SMD_LEVEL_SVS>;
289 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
293 opp-level = <RPM_SMD_LEVEL_NOM>;
297 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
301 opp-level = <RPM_SMD_LEVEL_TURBO>;
305 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
309 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
317 reserved-memory {
318 #address-cells = <2>;
319 #size-cells = <2>;
322 ext-region@85b00000 {
324 no-map;
330 no-map;
333 qcom,rpm-msg-ram = <&rpm_msg_ram>;
338 no-map;
343 no-map;
348 no-map;
353 no-map;
358 no-map;
361 tz-apps@8dd00000 {
363 no-map;
367 smp2p-hexagon {
372 qcom,local-pid = <0>;
373 qcom,remote-pid = <2>;
376 adsp_smp2p_out: master-kernel {
377 qcom,entry-name = "master-kernel";
379 #qcom,smem-state-cells = <1>;
382 adsp_smp2p_in: slave-kernel {
383 qcom,entry-name = "slave-kernel";
385 interrupt-controller;
386 #interrupt-cells = <2>;
390 smp2p-modem {
395 qcom,local-pid = <0>;
396 qcom,remote-pid = <1>;
399 modem_smp2p_out: master-kernel {
400 qcom,entry-name = "master-kernel";
402 #qcom,smem-state-cells = <1>;
405 modem_smp2p_in: slave-kernel {
406 qcom,entry-name = "slave-kernel";
408 interrupt-controller;
409 #interrupt-cells = <2>;
413 smp2p-wcnss {
418 qcom,local-pid = <0>;
419 qcom,remote-pid = <4>;
422 wcnss_smp2p_out: master-kernel {
423 qcom,entry-name = "master-kernel";
425 #qcom,smem-state-cells = <1>;
428 wcnss_smp2p_in: slave-kernel {
429 qcom,entry-name = "slave-kernel";
431 interrupt-controller;
432 #interrupt-cells = <2>;
439 #address-cells = <1>;
440 #size-cells = <0>;
446 #qcom,smem-state-cells = <1>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
467 #address-cells = <1>;
468 #size-cells = <1>;
470 compatible = "simple-bus";
476 clock-names = "core";
480 compatible = "qcom,rpm-msg-ram";
485 compatible = "qcom,usb-hs-28nm-femtophy";
487 #phy-cells = <0>;
491 clock-names = "ref", "ahb", "sleep";
494 reset-names = "phy", "por";
499 compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
501 #address-cells = <1>;
502 #size-cells = <1>;
509 tsens_s0_p1: s0-p1@219 {
514 tsens_s0_p2: s0-p2@219 {
519 tsens_s1_p1: s1-p1@21a {
524 tsens_s1_p2: s1-p2@21b {
529 tsens_s2_p1: s2-p1@21c {
534 tsens_s2_p2: s2-p2@21c {
539 tsens_s3_p1: s3-p1@21d {
544 tsens_s3_p2: s3-p2@21e {
554 tsens_s4_p1: s4-p1@221 {
559 tsens_s4_p2: s4-p2@221 {
564 tsens_s5_p1: s5-p1@222 {
569 tsens_s5_p2: s5-p2@223 {
574 tsens_s6_p1: s6-p1@224 {
579 tsens_s6_p2: s6-p2@224 {
584 tsens_s7_p1: s7-p1@225 {
589 tsens_s7_p2: s7-p2@226 {
599 tsens_s8_p1: s8-p1@228 {
604 tsens_s8_p2: s8-p2@229 {
609 tsens_s9_p1: s9-p1@229 {
614 tsens_s9_p2: s9-p2@22a {
619 tsens_s10_p1: s10-p1@22b {
624 tsens_s10_p2: s10-p2@22c {
630 tsens: thermal-sensor@4a9000 {
631 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
635 interrupt-names = "uplow";
636 nvmem-cells = <&tsens_mode>,
649 nvmem-cell-names = "mode",
663 #thermal-sensor-cells = <1>;
672 compatible = "qcom,msm8976-pinctrl";
675 #gpio-cells = <2>;
676 gpio-controller;
677 gpio-ranges = <&tlmm 0 0 145>;
678 interrupt-controller;
679 #interrupt-cells = <2>;
681 spi1_default: spi0-default-state {
682 spi-pins {
685 drive-strength = <12>;
686 bias-disable;
689 cs-pins {
692 drive-strength = <2>;
693 bias-disable;
697 spi1_sleep: spi0-sleep-state {
698 spi-pins {
701 drive-strength = <2>;
702 bias-pull-down;
705 cs-pins {
708 drive-strength = <2>;
709 bias-disable;
713 blsp1_i2c2_default: blsp1-i2c2-default-state {
716 drive-strength = <2>;
717 bias-disable;
720 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
723 drive-strength = <2>;
724 bias-disable;
727 blsp1_i2c4_default: blsp1-i2c4-default-state {
730 drive-strength = <2>;
731 bias-disable;
734 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
737 drive-strength = <2>;
738 bias-disable;
741 blsp2_uart2_active: blsp2-uart2-active-state {
744 drive-strength = <4>;
745 bias-disable;
748 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
751 drive-strength = <2>;
752 bias-disable;
756 blsp2_i2c2_default: blsp2-i2c2-default-state {
759 drive-strength = <2>;
760 bias-disable;
763 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
766 drive-strength = <2>;
767 bias-disable;
770 blsp2_i2c4_default: blsp2-i2c4-default-state {
773 drive-strength = <2>;
774 bias-disable;
777 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
780 drive-strength = <2>;
781 bias-disable;
784 wcss_wlan_default: wcss-wlan-default-state {
785 wcss-wlan2-pins {
788 drive-strength = <6>;
789 bias-pull-up;
792 wcss-wlan1-pins {
795 drive-strength = <6>;
796 bias-pull-up;
799 wcss-wlan0-pins {
802 drive-strength = <6>;
803 bias-pull-up;
806 wcss-wlan-pins {
809 drive-strength = <6>;
810 bias-pull-up;
815 gcc: clock-controller@1800000 {
816 compatible = "qcom,gcc-msm8976";
818 #clock-cells = <1>;
819 #reset-cells = <1>;
820 #power-domain-cells = <1>;
822 assigned-clocks = <&gcc GPLL3>;
823 assigned-clock-rates = <1100000000>;
831 clock-names = "xo",
840 compatible = "qcom,tcsr-mutex";
842 #hwlock-cells = <1>;
846 compatible = "qcom,msm8976-tcsr", "syscon";
850 mdss: display-subsystem@1a00000 {
855 reg-names = "mdss_phys", "vbif_phys";
857 power-domains = <&gcc MDSS_GDSC>;
860 interrupt-controller;
861 #interrupt-cells = <1>;
867 clock-names = "iface",
872 #address-cells = <1>;
873 #size-cells = <1>;
878 mdss_mdp: display-controller@1a01000 {
879 compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
881 reg-names = "mdp_phys";
883 interrupt-parent = <&mdss>;
892 clock-names = "iface",
899 operating-points-v2 = <&mdp_opp_table>;
900 power-domains = <&gcc MDSS_GDSC>;
905 #address-cells = <1>;
906 #size-cells = <0>;
912 remote-endpoint = <&mdss_dsi0_in>;
920 remote-endpoint = <&mdss_dsi1_in>;
925 mdp_opp_table: opp-table {
926 compatible = "operating-points-v2";
928 opp-177780000 {
929 opp-hz = /bits/ 64 <177780000>;
930 required-opps = <&rpmpd_opp_svs>;
933 opp-270000000 {
934 opp-hz = /bits/ 64 <270000000>;
935 required-opps = <&rpmpd_opp_svs_plus>;
938 opp-320000000 {
939 opp-hz = /bits/ 64 <320000000>;
940 required-opps = <&rpmpd_opp_nom>;
943 opp-360000000 {
944 opp-hz = /bits/ 64 <360000000>;
945 required-opps = <&rpmpd_opp_turbo>;
951 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
953 reg-names = "dsi_ctrl";
955 interrupt-parent = <&mdss>;
964 clock-names = "mdp_core",
971 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
973 assigned-clock-parents = <&mdss_dsi0_phy 0>,
978 operating-points-v2 = <&dsi0_opp_table>;
979 power-domains = <&gcc MDSS_GDSC>;
981 #address-cells = <1>;
982 #size-cells = <0>;
987 #address-cells = <1>;
988 #size-cells = <0>;
994 remote-endpoint = <&mdss_mdp5_intf1_out>;
1006 dsi0_opp_table: opp-table {
1007 compatible = "operating-points-v2";
1009 opp-125000000 {
1010 opp-hz = /bits/ 64 <125000000>;
1011 required-opps = <&rpmpd_opp_svs>;
1014 opp-161250000 {
1015 opp-hz = /bits/ 64 <161250000>;
1016 required-opps = <&rpmpd_opp_svs_plus>;
1019 opp-187500000 {
1020 opp-hz = /bits/ 64 <187500000>;
1021 required-opps = <&rpmpd_opp_nom>;
1027 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1029 reg-names = "dsi_ctrl";
1031 interrupt-parent = <&mdss>;
1040 clock-names = "mdp_core",
1047 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
1049 assigned-clock-parents = <&mdss_dsi1_phy 0>,
1054 operating-points-v2 = <&dsi0_opp_table>;
1055 power-domains = <&gcc MDSS_GDSC>;
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1070 remote-endpoint = <&mdss_mdp5_intf2_out>;
1084 compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
1088 reg-names = "dsi_pll",
1092 #clock-cells = <1>;
1093 #phy-cells = <0>;
1097 clock-names = "iface", "ref";
1103 compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
1107 reg-names = "dsi_pll",
1111 #clock-cells = <1>;
1112 #phy-cells = <0>;
1116 clock-names = "iface", "ref";
1123 compatible = "qcom,adreno-510.0", "qcom,adreno";
1126 reg-names = "kgsl_3d0_reg_memory";
1129 interrupt-names = "kgsl_3d0_irq";
1137 clock-names = "core",
1144 power-domains = <&gcc OXILI_GX_GDSC>;
1148 operating-points-v2 = <&gpu_opp_table>;
1152 gpu_opp_table: opp-table {
1153 compatible = "operating-points-v2";
1155 opp-200000000 {
1156 opp-hz = /bits/ 64 <200000000>;
1157 required-opps = <&rpmpd_opp_low_svs>;
1158 opp-supported-hw = <0xff>;
1161 opp-300000000 {
1162 opp-hz = /bits/ 64 <300000000>;
1163 required-opps = <&rpmpd_opp_svs>;
1164 opp-supported-hw = <0xff>;
1167 opp-400000000 {
1168 opp-hz = /bits/ 64 <400000000>;
1169 required-opps = <&rpmpd_opp_nom>;
1170 opp-supported-hw = <0xff>;
1173 opp-480000000 {
1174 opp-hz = /bits/ 64 <480000000>;
1175 required-opps = <&rpmpd_opp_nom_plus>;
1176 opp-supported-hw = <0xff>;
1179 opp-540000000 {
1180 opp-hz = /bits/ 64 <540000000>;
1181 required-opps = <&rpmpd_opp_turbo>;
1182 opp-supported-hw = <0xff>;
1185 opp-600000000 {
1186 opp-hz = /bits/ 64 <600000000>;
1187 required-opps = <&rpmpd_opp_turbo>;
1188 opp-supported-hw = <0xff>;
1194 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
1200 clock-names = "iface", "bus";
1202 qcom,iommu-secure-id = <17>;
1204 #address-cells = <1>;
1205 #size-cells = <1>;
1206 #iommu-cells = <1>;
1209 iommu-ctx@15000 {
1210 compatible = "qcom,msm-iommu-v2-ns";
1212 qcom,ctx-asid = <20>;
1217 iommu-ctx@16000 {
1218 compatible = "qcom,msm-iommu-v2-ns";
1220 qcom,ctx-asid = <21>;
1225 iommu-ctx@17000 {
1226 compatible = "qcom,msm-iommu-v2-ns";
1228 qcom,ctx-asid = <22>;
1234 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
1239 clock-names = "iface", "bus";
1241 power-domains = <&gcc OXILI_CX_GDSC>;
1243 qcom,iommu-secure-id = <18>;
1245 #address-cells = <1>;
1246 #size-cells = <1>;
1247 #iommu-cells = <1>;
1250 iommu-ctx@0 {
1251 compatible = "qcom,msm-iommu-v2-ns";
1253 qcom,ctx-asid = <0>;
1258 iommu-ctx@1000 {
1259 compatible = "qcom,msm-iommu-v2-sec";
1261 qcom,ctx-asid = <2>;
1266 iommu-ctx@2000 {
1267 compatible = "qcom,msm-iommu-v2-sec";
1269 qcom,ctx-asid = <1>;
1275 compatible = "qcom,spmi-pmic-arb";
1281 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1283 interrupt-names = "periph_irq";
1287 #address-cells = <2>;
1288 #size-cells = <0>;
1289 interrupt-controller;
1290 #interrupt-cells = <4>;
1294 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1296 reg-names = "hc", "core";
1300 interrupt-names = "hc_irq", "pwr_irq";
1305 clock-names = "iface", "core", "xo";
1310 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1312 reg-names = "hc", "core";
1316 interrupt-names = "hc_irq", "pwr_irq";
1321 clock-names = "iface", "core", "xo";
1325 blsp1_dma: dma-controller@7884000 {
1326 compatible = "qcom,bam-v1.7.0";
1330 clock-names = "bam_clk";
1331 #dma-cells = <1>;
1336 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1340 clock-names = "core", "iface";
1342 dma-names = "tx", "rx";
1347 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1351 clock-names = "core", "iface";
1353 dma-names = "tx", "rx";
1358 compatible = "qcom,spi-qup-v2.2.1";
1362 clock-names = "core", "iface";
1364 dma-names = "tx", "rx";
1365 pinctrl-names = "default", "sleep";
1366 pinctrl-0 = <&spi1_default>;
1367 pinctrl-1 = <&spi1_sleep>;
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1374 compatible = "qcom,i2c-qup-v2.2.1";
1378 clock-names = "core", "iface";
1379 clock-frequency = <400000>;
1381 dma-names = "tx", "rx";
1382 pinctrl-names = "default", "sleep";
1383 pinctrl-0 = <&blsp1_i2c2_default>;
1384 pinctrl-1 = <&blsp1_i2c2_default>;
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1391 compatible = "qcom,i2c-qup-v2.2.1";
1395 clock-names = "core", "iface";
1396 clock-frequency = <400000>;
1398 dma-names = "tx", "rx";
1399 pinctrl-names = "default", "sleep";
1400 pinctrl-0 = <&blsp1_i2c4_default>;
1401 pinctrl-1 = <&blsp1_i2c4_sleep>;
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1408 compatible = "qcom,ci-hdrc";
1414 clock-names = "iface", "core";
1415 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1416 assigned-clock-rates = <80000000>;
1418 reset-names = "core";
1419 ahb-burst-config = <0>;
1422 phy-names = "usb-phy";
1425 #reset-cells = <1>;
1429 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1431 reg-names = "hc", "core";
1435 interrupt-names = "hc_irq", "pwr_irq";
1440 clock-names = "iface", "core", "xo";
1445 blsp2_dma: dma-controller@7ac4000 {
1446 compatible = "qcom,bam-v1.7.0";
1450 clock-names = "bam_clk";
1451 #dma-cells = <1>;
1456 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1460 clock-names = "core", "iface";
1462 dma-names = "tx", "rx";
1467 compatible = "qcom,i2c-qup-v2.2.1";
1471 clock-names = "core", "iface";
1472 clock-frequency = <400000>;
1474 dma-names = "tx", "rx";
1475 pinctrl-names = "default", "sleep";
1476 pinctrl-0 = <&blsp2_i2c2_default>;
1477 pinctrl-1 = <&blsp2_i2c2_sleep>;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1484 compatible = "qcom,i2c-qup-v2.2.1";
1488 clock-names = "core", "iface";
1489 clock-frequency = <400000>;
1491 dma-names = "tx", "rx";
1492 pinctrl-names = "default", "sleep";
1493 pinctrl-0 = <&blsp2_i2c4_default>;
1494 pinctrl-1 = <&blsp2_i2c4_sleep>;
1495 #address-cells = <1>;
1496 #size-cells = <0>;
1501 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1505 reg-names = "ccu",
1509 memory-region = <&wcnss_fw_mem>;
1511 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1516 interrupt-names = "wdog",
1520 "stop-ack";
1522 power-domains = <&rpmpd MSM8976_VDDCX>,
1524 power-domain-names = "cx", "mx";
1526 qcom,smem-states = <&wcnss_smp2p_out 0>;
1527 qcom,smem-state-names = "stop";
1529 pinctrl-0 = <&wcss_wlan_default>;
1530 pinctrl-names = "default";
1535 /* Separate chip, compatible is board-specific */
1537 clock-names = "xo";
1540 smd-edge {
1544 qcom,smd-edge = <6>;
1545 qcom,remote-pid = <4>;
1551 qcom,smd-channels = "WCNSS_CTRL";
1556 compatible = "qcom,wcnss-bt";
1560 compatible = "qcom,wcnss-wlan";
1564 interrupt-names = "tx", "rx";
1566 qcom,smem-states = <&apps_smsm 10>,
1568 qcom,smem-state-names = "tx-enable",
1569 "tx-rings-empty";
1575 intc: interrupt-controller@b000000 {
1576 compatible = "qcom,msm-qgic2";
1578 interrupt-controller;
1579 #interrupt-cells = <3>;
1583 compatible = "qcom,msm8976-apcs-kpss-global",
1584 "qcom,msm8994-apcs-kpss-global", "syscon";
1586 #mbox-cells = <1>;
1590 compatible = "arm,armv7-timer-mem";
1592 #address-cells = <1>;
1593 #size-cells = <1>;
1595 clock-frequency = <19200000>;
1601 frame-number = <0>;
1607 frame-number = <1>;
1614 frame-number = <2>;
1621 frame-number = <3>;
1628 frame-number = <4>;
1635 frame-number = <5>;
1642 frame-number = <6>;
1648 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
1650 #address-cells = <1>;
1651 #size-cells = <1>;
1655 pil-reloc@94c {
1656 compatible = "qcom,pil-reloc-info";
1662 thermal-zones {
1663 aoss0-thermal {
1664 polling-delay-passive = <250>;
1666 thermal-sensors = <&tsens 0>;
1669 aoss0_alert0: trip-point0 {
1677 modem-thermal {
1678 polling-delay-passive = <250>;
1680 thermal-sensors = <&tsens 1>;
1682 modem_alert0: trip-point0 {
1690 qdsp-thermal {
1691 polling-delay-passive = <250>;
1693 thermal-sensors = <&tsens 2>;
1695 qdsp_alert0: trip-point0 {
1703 cam-isp-thermal {
1704 polling-delay-passive = <250>;
1706 thermal-sensors = <&tsens 3>;
1708 cam_isp_alert0: trip-point0 {
1716 cpu4-thermal {
1717 polling-delay-passive = <250>;
1719 thermal-sensors = <&tsens 4>;
1722 cpu4_alert0: trip-point0 {
1727 cpu4_alert1: trip-point1 {
1732 cpu4_crit: cpu-crit {
1740 cpu5-thermal {
1741 polling-delay-passive = <250>;
1743 thermal-sensors = <&tsens 5>;
1746 cpu5_alert0: trip-point0 {
1751 cpu5_alert1: trip-point1 {
1756 cpu5_crit: cpu-crit {
1764 cpu6-thermal {
1765 polling-delay-passive = <250>;
1767 thermal-sensors = <&tsens 6>;
1770 cpu6_alert0: trip-point0 {
1775 cpu6_alert1: trip-point1 {
1780 cpu6_crit: cpu-crit {
1788 cpu7-thermal {
1789 polling-delay-passive = <250>;
1791 thermal-sensors = <&tsens 7>;
1794 cpu7_alert0: trip-point0 {
1799 cpu7_alert1: trip-point1 {
1804 cpu7_crit: cpu-crit {
1812 big-l2-thermal {
1813 polling-delay-passive = <250>;
1815 thermal-sensors = <&tsens 8>;
1818 l2_alert0: trip-point0 {
1823 l2_alert1: trip-point1 {
1828 l2_crit: l2-crit {
1836 cpu0-thermal {
1837 polling-delay-passive = <250>;
1839 thermal-sensors = <&tsens 9>;
1842 cpu0_alert0: trip-point0 {
1847 cpu0_alert1: trip-point1 {
1852 cpu0_crit: cpu-crit {
1860 gpu-thermal {
1861 polling-delay-passive = <250>;
1863 thermal-sensors = <&tsens 10>;
1866 gpu_alert0: trip-point0 {
1871 gpu_alert1: trip-point1 {
1876 gpu_crit: gpu-crit {
1886 compatible = "arm,armv8-timer";
1891 clock-frequency = <19200000>;