Lines Matching full:gcc
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
209 clocks = <&gcc GCC_CRYPTO_CLK>,
210 <&gcc GCC_CRYPTO_AXI_CLK>,
211 <&gcc GCC_CRYPTO_AHB_CLK>;
475 clocks = <&gcc GCC_PRNG_AHB_CLK>;
489 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
490 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
492 resets = <&gcc RST_QUSB2_PHY_BCR>,
493 <&gcc RST_USB2_HS_PHY_ONLY_BCR>;
815 gcc: clock-controller@1800000 { label
816 compatible = "qcom,gcc-msm8976";
822 assigned-clocks = <&gcc GPLL3>;
857 power-domains = <&gcc MDSS_GDSC>;
863 clocks = <&gcc GCC_MDSS_AHB_CLK>,
864 <&gcc GCC_MDSS_AXI_CLK>,
865 <&gcc GCC_MDSS_VSYNC_CLK>,
866 <&gcc GCC_MDSS_MDP_CLK>;
886 clocks = <&gcc GCC_MDSS_AHB_CLK>,
887 <&gcc GCC_MDSS_AXI_CLK>,
888 <&gcc GCC_MDSS_MDP_CLK>,
889 <&gcc GCC_MDSS_VSYNC_CLK>,
890 <&gcc GCC_MDP_TBU_CLK>,
891 <&gcc GCC_MDP_RT_TBU_CLK>;
900 power-domains = <&gcc MDSS_GDSC>;
958 clocks = <&gcc GCC_MDSS_MDP_CLK>,
959 <&gcc GCC_MDSS_AHB_CLK>,
960 <&gcc GCC_MDSS_AXI_CLK>,
961 <&gcc GCC_MDSS_BYTE0_CLK>,
962 <&gcc GCC_MDSS_PCLK0_CLK>,
963 <&gcc GCC_MDSS_ESC0_CLK>;
971 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
972 <&gcc GCC_MDSS_PCLK0_CLK_SRC>;
979 power-domains = <&gcc MDSS_GDSC>;
1034 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1035 <&gcc GCC_MDSS_AHB_CLK>,
1036 <&gcc GCC_MDSS_AXI_CLK>,
1037 <&gcc GCC_MDSS_BYTE1_CLK>,
1038 <&gcc GCC_MDSS_PCLK1_CLK>,
1039 <&gcc GCC_MDSS_ESC1_CLK>;
1047 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
1048 <&gcc GCC_MDSS_PCLK1_CLK_SRC>;
1055 power-domains = <&gcc MDSS_GDSC>;
1095 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1114 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1131 clocks = <&gcc GCC_GFX3D_OXILI_CLK>,
1132 <&gcc GCC_GFX3D_OXILI_AHB_CLK>,
1133 <&gcc GCC_GFX3D_OXILI_GMEM_CLK>,
1134 <&gcc GCC_GFX3D_BIMC_CLK>,
1135 <&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
1136 <&gcc GCC_GFX3D_OXILI_AON_CLK>;
1144 power-domains = <&gcc OXILI_GX_GDSC>;
1198 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1199 <&gcc GCC_APSS_TCU_CLK>;
1237 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1238 <&gcc GCC_GFX3D_TCU_CLK>;
1241 power-domains = <&gcc OXILI_CX_GDSC>;
1302 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1303 <&gcc GCC_SDCC1_APPS_CLK>,
1318 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1319 <&gcc GCC_SDCC2_APPS_CLK>,
1329 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1339 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1350 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1361 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1377 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1394 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1413 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>;
1415 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1417 resets = <&gcc RST_USB_HS_BCR>;
1437 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
1438 <&gcc GCC_SDCC3_APPS_CLK>,
1449 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1459 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1470 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1487 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;