Lines Matching +full:0 +full:x89000
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
38 reg = <0x0>;
49 reg = <0x1>;
60 reg = <0x2>;
71 reg = <0x3>;
82 reg = <0x100>;
93 reg = <0x101>;
104 reg = <0x102>;
115 reg = <0x103>;
164 little_cpu_sleep_0: cpu-sleep-0-0 {
167 arm,psci-suspend-param = <0x40000003>;
174 big_cpu_sleep_0: cpu-sleep-1-0 {
177 arm,psci-suspend-param = <0x00000002>;
186 arm,psci-suspend-param = <0x40000003>;
216 qcom,dload-mode = <&tcsr 0x6100>;
223 reg = <0x0 0x80000000 0x0 0x0>;
233 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
247 mboxes = <&apcs 0>;
324 reg = <0x0 0x85b00000 0x0 0x500000>;
330 reg = <0x0 0x86300000 0x0 0x100000>;
338 reg = <0x0 0x86400000 0x0 0x800000>;
343 reg = <0x0 0x86c00000 0x0 0x5600000>;
348 reg = <0x0 0x8c200000 0x0 0x1000000>;
353 reg = <0x0 0x8d200000 0x0 0x800000>;
358 reg = <0x0 0x8da00000 0x0 0x2600000>;
363 reg = <0x0 0x8dd00000 0x0 0x1400000>;
373 qcom,local-pid = <0>;
396 qcom,local-pid = <0>;
419 qcom,local-pid = <0>;
441 #size-cells = <0>;
443 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
445 apps_smsm: apps@0 {
446 reg = <0>;
467 soc: soc@0 {
470 ranges = <0 0 0 0xffffffff>;
475 reg = <0x00022000 0x140>;
482 reg = <0x00060000 0x8000>;
487 reg = <0x0006c000 0x200>;
488 #phy-cells = <0>;
501 reg = <0x000a4000 0x1000>;
506 reg = <0x218 1>;
507 bits = <0 8>;
511 reg = <0x219 0x1>;
512 bits = <0 6>;
516 reg = <0x219 0x2>;
521 reg = <0x21a 0x2>;
526 reg = <0x21b 0x1>;
531 reg = <0x21c 0x1>;
532 bits = <0 6>;
536 reg = <0x21c 0x2>;
541 reg = <0x21d 0x2>;
546 reg = <0x21e 0x1>;
551 reg = <0x220 1>;
552 bits = <0 8>;
556 reg = <0x221 0x1>;
557 bits = <0 6>;
561 reg = <0x221 0x2>;
566 reg = <0x222 0x2>;
571 reg = <0x224 0x1>;
576 reg = <0x224 0x1>;
577 bits = <0 6>;
581 reg = <0x224 0x2>;
586 reg = <0x225 0x2>;
591 reg = <0x226 0x2>;
596 reg = <0x228 1>;
597 bits = <0 3>;
601 reg = <0x228 0x2>;
606 reg = <0x229 0x1>;
611 reg = <0x229 0x2>;
616 reg = <0x22a 0x2>;
621 reg = <0x22b 0x2>;
626 reg = <0x22c 0x1>;
633 reg = <0x004a9000 0x1000>, /* TM */
634 <0x004a8000 0x1000>; /* SROT */
669 reg = <0x004ab000 0x4>;
674 reg = <0x01000000 0x300000>;
678 gpio-ranges = <&tlmm 0 0 145>;
854 reg = <0x01800000 0x80000>;
878 reg = <0x01905000 0x20000>;
884 reg = <0x01937000 0x30000>;
890 reg = <0x01a00000 0x1000>,
891 <0x01ab0000 0x3000>;
917 reg = <0x01a01000 0x89000>;
921 interrupts = <0>;
943 #size-cells = <0>;
945 port@0 {
946 reg = <0>;
989 reg = <0x01a94000 0x300>;
1019 #size-cells = <0>;
1025 #size-cells = <0>;
1027 port@0 {
1028 reg = <0>;
1065 reg = <0x01a96000 0x300>;
1095 #size-cells = <0>;
1101 #size-cells = <0>;
1103 port@0 {
1104 reg = <0>;
1122 reg = <0x01a94a00 0xd4>,
1123 <0x01a94400 0x280>,
1124 <0x01a94b80 0x30>;
1130 #phy-cells = <0>;
1141 reg = <0x01a96a00 0xd4>,
1142 <0x01a96400 0x280>,
1143 <0x01a96b80 0x30>;
1149 #phy-cells = <0>;
1162 reg = <0x01c00000 0x40000>;
1183 iommus = <&gpu_iommu 0>;
1195 opp-supported-hw = <0xff>;
1201 opp-supported-hw = <0xff>;
1207 opp-supported-hw = <0xff>;
1213 opp-supported-hw = <0xff>;
1219 opp-supported-hw = <0xff>;
1225 opp-supported-hw = <0xff>;
1232 reg = <0x01ee0000 0x3000>;
1233 ranges = <0 0x01e20000 0x20000>;
1248 reg = <0x15000 0x1000>;
1256 reg = <0x16000 0x1000>;
1264 reg = <0x17000 0x1000>;
1272 ranges = <0 0x01f08000 0x8000>;
1287 iommu-ctx@0 {
1289 reg = <0x0 0x1000>;
1290 qcom,ctx-asid = <0>;
1297 reg = <0x1000 0x1000>;
1305 reg = <0x2000 0x1000>;
1313 reg = <0x0200f000 0x1000>,
1314 <0x02400000 0x800000>,
1315 <0x02c00000 0x800000>,
1316 <0x03800000 0x200000>,
1317 <0x0200a000 0x2100>;
1321 qcom,channel = <0>;
1322 qcom,ee = <0>;
1325 #size-cells = <0>;
1332 reg = <0x07824900 0x500>, <0x07824000 0x800>;
1348 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1364 reg = <0x07884000 0x1f000>;
1369 qcom,ee = <0>;
1375 reg = <0x078af000 0x200>;
1379 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1386 reg = <0x078b0000 0x200>;
1397 reg = <0x078b5000 0x500>;
1404 pinctrl-0 = <&spi1_default>;
1407 #size-cells = <0>;
1413 reg = <0x078b6000 0x500>;
1421 pinctrl-0 = <&blsp1_i2c2_default>;
1424 #size-cells = <0>;
1430 reg = <0x078b8000 0x500>;
1438 pinctrl-0 = <&blsp1_i2c4_default>;
1441 #size-cells = <0>;
1447 reg = <0x078db000 0x200>,
1448 <0x078db200 0x200>;
1457 ahb-burst-config = <0>;
1468 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>;
1485 reg = <0x07ac4000 0x1f000>;
1490 qcom,ee = <0>;
1496 reg = <0x07af0000 0x200>;
1500 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1507 reg = <0x07af6000 0x600>;
1515 pinctrl-0 = <&blsp2_i2c2_default>;
1518 #size-cells = <0>;
1524 reg = <0x07af8000 0x600>;
1532 pinctrl-0 = <&blsp2_i2c4_default>;
1535 #size-cells = <0>;
1541 reg = <0x0a204000 0x2000>,
1542 <0x0a202000 0x1000>,
1543 <0x0a21b000 0x3000>;
1551 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1565 qcom,smem-states = <&wcnss_smp2p_out 0>;
1568 pinctrl-0 = <&wcss_wlan_default>;
1616 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1624 reg = <0x0b011000 0x1000>;
1630 reg = <0x0b120000 0x1000>;
1637 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>;
1640 frame-number = <0>;
1644 reg = <0x0b123000 0x1000>;
1651 reg = <0x0b124000 0x1000>;
1658 reg = <0x0b125000 0x1000>;
1665 reg = <0x0b126000 0x1000>;
1672 reg = <0x0b127000 0x1000>;
1679 reg = <0x0b128000 0x1000>;
1688 reg = <0x08600000 0x1000>;
1692 ranges = <0 0x08600000 0x1000>;
1696 reg = <0x94c 0xc8>;
1705 thermal-sensors = <&tsens 0>;