Lines Matching +full:0 +full:x01ee0000
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0>;
48 reg = <0x1>;
59 reg = <0x2>;
70 reg = <0x3>;
81 reg = <0x100>;
92 reg = <0x101>;
103 reg = <0x102>;
114 reg = <0x103>;
163 little_cpu_sleep_0: cpu-sleep-0-0 {
166 arm,psci-suspend-param = <0x40000003>;
173 big_cpu_sleep_0: cpu-sleep-1-0 {
176 arm,psci-suspend-param = <0x00000002>;
185 arm,psci-suspend-param = <0x40000003>;
215 qcom,dload-mode = <&tcsr 0x6100>;
222 reg = <0x0 0x80000000 0x0 0x0>;
232 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
246 mboxes = <&apcs 0>;
323 reg = <0x0 0x85b00000 0x0 0x500000>;
329 reg = <0x0 0x86300000 0x0 0x100000>;
337 reg = <0x0 0x86400000 0x0 0x800000>;
342 reg = <0x0 0x86c00000 0x0 0x5600000>;
347 reg = <0x0 0x8c200000 0x0 0x1000000>;
352 reg = <0x0 0x8d200000 0x0 0x800000>;
357 reg = <0x0 0x8da00000 0x0 0x2600000>;
362 reg = <0x0 0x8dd00000 0x0 0x1400000>;
372 qcom,local-pid = <0>;
395 qcom,local-pid = <0>;
418 qcom,local-pid = <0>;
440 #size-cells = <0>;
442 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
444 apps_smsm: apps@0 {
445 reg = <0>;
466 soc: soc@0 {
469 ranges = <0 0 0 0xffffffff>;
474 reg = <0x00022000 0x140>;
481 reg = <0x00060000 0x8000>;
486 reg = <0x0006c000 0x200>;
487 #phy-cells = <0>;
500 reg = <0x000a4000 0x1000>;
505 reg = <0x218 1>;
506 bits = <0 8>;
510 reg = <0x219 0x1>;
511 bits = <0 6>;
515 reg = <0x219 0x2>;
520 reg = <0x21a 0x2>;
525 reg = <0x21b 0x1>;
530 reg = <0x21c 0x1>;
531 bits = <0 6>;
535 reg = <0x21c 0x2>;
540 reg = <0x21d 0x2>;
545 reg = <0x21e 0x1>;
550 reg = <0x220 1>;
551 bits = <0 8>;
555 reg = <0x221 0x1>;
556 bits = <0 6>;
560 reg = <0x221 0x2>;
565 reg = <0x222 0x2>;
570 reg = <0x224 0x1>;
575 reg = <0x224 0x1>;
576 bits = <0 6>;
580 reg = <0x224 0x2>;
585 reg = <0x225 0x2>;
590 reg = <0x226 0x2>;
595 reg = <0x228 1>;
596 bits = <0 3>;
600 reg = <0x228 0x2>;
605 reg = <0x229 0x1>;
610 reg = <0x229 0x2>;
615 reg = <0x22a 0x2>;
620 reg = <0x22b 0x2>;
625 reg = <0x22c 0x1>;
632 reg = <0x004a9000 0x1000>, /* TM */
633 <0x004a8000 0x1000>; /* SROT */
668 reg = <0x004ab000 0x4>;
673 reg = <0x01000000 0x300000>;
677 gpio-ranges = <&tlmm 0 0 145>;
817 reg = <0x01800000 0x80000>;
828 <&mdss_dsi0_phy 0>,
830 <&mdss_dsi1_phy 0>;
841 reg = <0x01905000 0x20000>;
847 reg = <0x01937000 0x30000>;
853 reg = <0x01a00000 0x1000>,
854 <0x01ab0000 0x3000>;
880 reg = <0x01a01000 0x89000>;
884 interrupts = <0>;
906 #size-cells = <0>;
908 port@0 {
909 reg = <0>;
952 reg = <0x01a94000 0x300>;
973 assigned-clock-parents = <&mdss_dsi0_phy 0>,
982 #size-cells = <0>;
988 #size-cells = <0>;
990 port@0 {
991 reg = <0>;
1028 reg = <0x01a96000 0x300>;
1049 assigned-clock-parents = <&mdss_dsi1_phy 0>,
1058 #size-cells = <0>;
1064 #size-cells = <0>;
1066 port@0 {
1067 reg = <0>;
1085 reg = <0x01a94a00 0xd4>,
1086 <0x01a94400 0x280>,
1087 <0x01a94b80 0x30>;
1093 #phy-cells = <0>;
1104 reg = <0x01a96a00 0xd4>,
1105 <0x01a96400 0x280>,
1106 <0x01a96b80 0x30>;
1112 #phy-cells = <0>;
1125 reg = <0x01c00000 0x40000>;
1146 iommus = <&gpu_iommu 0>;
1158 opp-supported-hw = <0xff>;
1164 opp-supported-hw = <0xff>;
1170 opp-supported-hw = <0xff>;
1176 opp-supported-hw = <0xff>;
1182 opp-supported-hw = <0xff>;
1188 opp-supported-hw = <0xff>;
1195 reg = <0x01ee0000 0x3000>;
1196 ranges = <0 0x01e20000 0x20000>;
1211 reg = <0x15000 0x1000>;
1219 reg = <0x16000 0x1000>;
1227 reg = <0x17000 0x1000>;
1235 ranges = <0 0x01f08000 0x8000>;
1250 iommu-ctx@0 {
1252 reg = <0x0 0x1000>;
1253 qcom,ctx-asid = <0>;
1260 reg = <0x1000 0x1000>;
1268 reg = <0x2000 0x1000>;
1276 reg = <0x0200f000 0x1000>,
1277 <0x02400000 0x800000>,
1278 <0x02c00000 0x800000>,
1279 <0x03800000 0x200000>,
1280 <0x0200a000 0x2100>;
1284 qcom,channel = <0>;
1285 qcom,ee = <0>;
1288 #size-cells = <0>;
1295 reg = <0x07824900 0x500>, <0x07824000 0x800>;
1311 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1327 reg = <0x07884000 0x1f000>;
1332 qcom,ee = <0>;
1337 reg = <0x078af000 0x200>;
1341 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1348 reg = <0x078b0000 0x200>;
1359 reg = <0x078b5000 0x500>;
1366 pinctrl-0 = <&spi1_default>;
1369 #size-cells = <0>;
1375 reg = <0x078b6000 0x500>;
1383 pinctrl-0 = <&blsp1_i2c2_default>;
1386 #size-cells = <0>;
1392 reg = <0x078b8000 0x500>;
1400 pinctrl-0 = <&blsp1_i2c4_default>;
1403 #size-cells = <0>;
1409 reg = <0x078db000 0x200>,
1410 <0x078db200 0x200>;
1419 ahb-burst-config = <0>;
1430 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>;
1447 reg = <0x07ac4000 0x1f000>;
1452 qcom,ee = <0>;
1457 reg = <0x07af0000 0x200>;
1461 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1468 reg = <0x07af6000 0x600>;
1476 pinctrl-0 = <&blsp2_i2c2_default>;
1479 #size-cells = <0>;
1485 reg = <0x07af8000 0x600>;
1493 pinctrl-0 = <&blsp2_i2c4_default>;
1496 #size-cells = <0>;
1502 reg = <0x0a204000 0x2000>,
1503 <0x0a202000 0x1000>,
1504 <0x0a21b000 0x3000>;
1512 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1526 qcom,smem-states = <&wcnss_smp2p_out 0>;
1529 pinctrl-0 = <&wcss_wlan_default>;
1577 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1585 reg = <0x0b011000 0x1000>;
1591 reg = <0x0b120000 0x1000>;
1598 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>;
1601 frame-number = <0>;
1605 reg = <0x0b123000 0x1000>;
1612 reg = <0x0b124000 0x1000>;
1619 reg = <0x0b125000 0x1000>;
1626 reg = <0x0b126000 0x1000>;
1633 reg = <0x0b127000 0x1000>;
1640 reg = <0x0b128000 0x1000>;
1649 reg = <0x08600000 0x1000>;
1653 ranges = <0 0x08600000 0x1000>;
1657 reg = <0x94c 0xc8>;
1666 thermal-sensors = <&tsens 0>;