Lines Matching +full:smp2p +full:- +full:mpss
1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interconnect/qcom,msm8953.h>
9 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,apr.h>
13 #include <dt-bindings/sound/qcom,q6afe.h>
14 #include <dt-bindings/sound/qcom,q6asm.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
26 sleep_clk: sleep-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <32768>;
32 xo_board: xo-board {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <19200000>;
36 clock-output-names = "xo";
41 #address-cells = <1>;
42 #size-cells = <0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 capacity-dmips-mhz = <1024>;
52 next-level-cache = <&l2_0>;
53 #cooling-cells = <2>;
58 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 capacity-dmips-mhz = <1024>;
64 next-level-cache = <&l2_0>;
65 #cooling-cells = <2>;
70 compatible = "arm,cortex-a53";
72 enable-method = "psci";
73 capacity-dmips-mhz = <1024>;
76 next-level-cache = <&l2_0>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a53";
84 enable-method = "psci";
85 capacity-dmips-mhz = <1024>;
88 next-level-cache = <&l2_0>;
89 #cooling-cells = <2>;
94 compatible = "arm,cortex-a53";
96 enable-method = "psci";
97 capacity-dmips-mhz = <1024>;
100 next-level-cache = <&l2_1>;
101 #cooling-cells = <2>;
106 compatible = "arm,cortex-a53";
108 enable-method = "psci";
109 capacity-dmips-mhz = <1024>;
112 next-level-cache = <&l2_1>;
113 #cooling-cells = <2>;
118 compatible = "arm,cortex-a53";
120 enable-method = "psci";
121 capacity-dmips-mhz = <1024>;
124 next-level-cache = <&l2_1>;
125 #cooling-cells = <2>;
130 compatible = "arm,cortex-a53";
132 enable-method = "psci";
133 capacity-dmips-mhz = <1024>;
136 next-level-cache = <&l2_1>;
137 #cooling-cells = <2>;
140 cpu-map {
172 l2_0: l2-cache-0 {
174 cache-level = <2>;
175 cache-unified;
178 l2_1: l2-cache-1 {
180 cache-level = <2>;
181 cache-unified;
187 compatible = "qcom,scm-msm8953", "qcom,scm";
191 clock-names = "core", "bus", "iface";
192 #reset-cells = <1>;
203 compatible = "arm,cortex-a53-pmu";
208 compatible = "arm,psci-1.0";
213 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc";
215 smd-edge {
218 qcom,smd-edge = <15>;
220 rpm_requests: rpm-requests {
221 compatible = "qcom,rpm-msm8953", "qcom,smd-rpm";
222 qcom,smd-channels = "rpm_requests";
224 rpmcc: clock-controller {
225 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
227 clock-names = "xo";
228 #clock-cells = <1>;
231 rpmpd: power-controller {
232 compatible = "qcom,msm8953-rpmpd";
233 #power-domain-cells = <1>;
234 operating-points-v2 = <&rpmpd_opp_table>;
236 rpmpd_opp_table: opp-table {
237 compatible = "operating-points-v2";
240 opp-level = <RPM_SMD_LEVEL_RETENTION>;
244 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
248 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
252 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
256 opp-level = <RPM_SMD_LEVEL_SVS>;
260 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
264 opp-level = <RPM_SMD_LEVEL_NOM>;
268 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
272 opp-level = <RPM_SMD_LEVEL_TURBO>;
280 reserved-memory {
281 #address-cells = <2>;
282 #size-cells = <2>;
286 compatible = "shared-dma-pool";
288 no-map;
293 no-map;
299 qcom,rpm-msg-ram = <&rpm_msg_ram>;
301 no-map;
306 no-map;
309 mpss_mem: mpss@86c00000 {
311 no-map;
316 no-map;
321 no-map;
324 dfps_data_mem: dfps-data@90000000 {
326 no-map;
329 cont_splash_mem: cont-splash@90001000 {
331 no-map;
336 no-map;
341 no-map;
345 compatible = "qcom,rmtfs-mem";
347 no-map;
349 qcom,client-id = <1>;
353 smp2p-adsp {
354 compatible = "qcom,smp2p";
361 qcom,local-pid = <0>;
362 qcom,remote-pid = <2>;
364 smp2p_adsp_out: master-kernel {
365 qcom,entry-name = "master-kernel";
366 #qcom,smem-state-cells = <1>;
369 smp2p_adsp_in: slave-kernel {
370 qcom,entry-name = "slave-kernel";
372 interrupt-controller;
373 #interrupt-cells = <2>;
377 smp2p-modem {
378 compatible = "qcom,smp2p";
385 qcom,local-pid = <0>;
386 qcom,remote-pid = <1>;
388 smp2p_modem_out: master-kernel {
389 qcom,entry-name = "master-kernel";
391 #qcom,smem-state-cells = <1>;
394 smp2p_modem_in: slave-kernel {
395 qcom,entry-name = "slave-kernel";
397 interrupt-controller;
398 #interrupt-cells = <2>;
402 smp2p-wcnss {
403 compatible = "qcom,smp2p";
410 qcom,local-pid = <0>;
411 qcom,remote-pid = <4>;
413 smp2p_wcnss_out: master-kernel {
414 qcom,entry-name = "master-kernel";
416 #qcom,smem-state-cells = <1>;
419 smp2p_wcnss_in: slave-kernel {
420 qcom,entry-name = "slave-kernel";
422 interrupt-controller;
423 #interrupt-cells = <2>;
430 #address-cells = <1>;
431 #size-cells = <0>;
438 #qcom,smem-state-cells = <1>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
459 #address-cells = <1>;
460 #size-cells = <1>;
462 compatible = "simple-bus";
465 compatible = "qcom,rpm-msg-ram";
470 compatible = "qcom,msm8953-qusb2-phy";
472 #phy-cells = <0>;
476 clock-names = "cfg_ahb", "ref";
478 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
489 clock-names = "core";
493 compatible = "qcom,msm8953-bimc";
496 #interconnect-cells = <2>;
499 tsens0: thermal-sensor@4a9000 {
500 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
506 interrupt-names = "uplow", "critical";
507 #thermal-sensor-cells = <1>;
516 compatible = "qcom,msm8953-pcnoc";
520 clock-names = "pcnoc_usb3_axi";
522 #interconnect-cells = <2>;
526 compatible = "qcom,msm8953-snoc";
529 #interconnect-cells = <2>;
531 snoc_mm: interconnect-snoc {
532 compatible = "qcom,msm8953-snoc-mm";
534 #interconnect-cells = <2>;
539 compatible = "qcom,msm8953-pinctrl";
542 gpio-controller;
543 gpio-ranges = <&tlmm 0 0 142>;
544 #gpio-cells = <2>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
548 uart_console_active: uart-console-active-state {
551 drive-strength = <2>;
552 bias-disable;
555 uart_console_sleep: uart-console-sleep-state {
558 drive-strength = <2>;
559 bias-pull-down;
562 sdc1_clk_on: sdc1-clk-on-state {
564 bias-disable;
565 drive-strength = <16>;
568 sdc1_clk_off: sdc1-clk-off-state {
570 bias-disable;
571 drive-strength = <2>;
574 sdc1_cmd_on: sdc1-cmd-on-state {
576 bias-disable;
577 drive-strength = <10>;
580 sdc1_cmd_off: sdc1-cmd-off-state {
582 bias-disable;
583 drive-strength = <2>;
586 sdc1_data_on: sdc1-data-on-state {
588 bias-pull-up;
589 drive-strength = <10>;
592 sdc1_data_off: sdc1-data-off-state {
594 bias-pull-up;
595 drive-strength = <2>;
598 sdc1_rclk_on: sdc1-rclk-on-state {
600 bias-pull-down;
603 sdc1_rclk_off: sdc1-rclk-off-state {
605 bias-pull-down;
608 sdc2_clk_on: sdc2-clk-on-state {
610 drive-strength = <16>;
611 bias-disable;
614 sdc2_clk_off: sdc2-clk-off-state {
616 bias-disable;
617 drive-strength = <2>;
620 sdc2_cmd_on: sdc2-cmd-on-state {
622 bias-pull-up;
623 drive-strength = <10>;
626 sdc2_cmd_off: sdc2-cmd-off-state {
628 bias-pull-up;
629 drive-strength = <2>;
632 sdc2_data_on: sdc2-data-on-state {
634 bias-pull-up;
635 drive-strength = <10>;
638 sdc2_data_off: sdc2-data-off-state {
640 bias-pull-up;
641 drive-strength = <2>;
644 sdc2_cd_on: cd-on-state {
647 drive-strength = <2>;
648 bias-pull-up;
651 sdc2_cd_off: cd-off-state {
654 drive-strength = <2>;
655 bias-disable;
658 gpio_key_default: gpio-key-default-state {
661 drive-strength = <2>;
662 bias-pull-up;
665 i2c_1_default: i2c-1-default-state {
668 drive-strength = <2>;
669 bias-disable;
672 i2c_1_sleep: i2c-1-sleep-state {
675 drive-strength = <2>;
676 bias-disable;
679 i2c_2_default: i2c-2-default-state {
682 drive-strength = <2>;
683 bias-disable;
686 i2c_2_sleep: i2c-2-sleep-state {
689 drive-strength = <2>;
690 bias-disable;
693 i2c_3_default: i2c-3-default-state {
696 drive-strength = <2>;
697 bias-disable;
700 i2c_3_sleep: i2c-3-sleep-state {
703 drive-strength = <2>;
704 bias-disable;
707 i2c_4_default: i2c-4-default-state {
710 drive-strength = <2>;
711 bias-disable;
714 i2c_4_sleep: i2c-4-sleep-state {
717 drive-strength = <2>;
718 bias-disable;
721 i2c_5_default: i2c-5-default-state {
724 drive-strength = <2>;
725 bias-disable;
728 i2c_5_sleep: i2c-5-sleep-state {
731 drive-strength = <2>;
732 bias-disable;
735 i2c_6_default: i2c-6-default-state {
738 drive-strength = <2>;
739 bias-disable;
742 i2c_6_sleep: i2c-6-sleep-state {
745 drive-strength = <2>;
746 bias-disable;
749 i2c_7_default: i2c-7-default-state {
752 drive-strength = <2>;
753 bias-disable;
756 i2c_7_sleep: i2c-7-sleep-state {
759 drive-strength = <2>;
760 bias-disable;
763 i2c_8_default: i2c-8-default-state {
766 drive-strength = <2>;
767 bias-disable;
770 i2c_8_sleep: i2c-8-sleep-state {
773 drive-strength = <2>;
774 bias-disable;
777 spi_3_default: spi-3-default-state {
780 drive-strength = <2>;
781 bias-disable;
784 spi_3_sleep: spi-3-sleep-state {
787 drive-strength = <2>;
788 bias-disable;
791 spi_5_default: spi-5-default-state {
794 drive-strength = <2>;
795 bias-disable;
798 spi_5_sleep: spi-5-sleep-state {
801 drive-strength = <2>;
802 bias-disable;
805 spi_6_default: spi-6-default-state {
808 drive-strength = <2>;
809 bias-disable;
812 spi_6_sleep: spi-6-sleep-state {
815 drive-strength = <2>;
816 bias-disable;
819 uart_5_default: uart-5-default-state {
822 drive-strength = <16>;
823 bias-disable;
826 uart_5_sleep: uart-5-sleep-state {
829 drive-strength = <2>;
830 bias-disable;
833 wcnss_pin_a: wcnss-active-state {
835 wcss-wlan2-pins {
838 drive-strength = <6>;
839 bias-pull-up;
842 wcss-wlan1-pins {
845 drive-strength = <6>;
846 bias-pull-up;
849 wcss-wlan0-pins {
852 drive-strength = <6>;
853 bias-pull-up;
856 wcss-wlan-pins {
859 drive-strength = <6>;
860 bias-pull-up;
865 gcc: clock-controller@1800000 {
866 compatible = "qcom,gcc-msm8953";
868 #clock-cells = <1>;
869 #reset-cells = <1>;
870 #power-domain-cells = <1>;
877 clock-names = "xo",
886 compatible = "qcom,tcsr-mutex";
888 #hwlock-cells = <1>;
892 compatible = "qcom,tcsr-msm8953", "syscon";
897 compatible = "qcom,tcsr-msm8953", "syscon";
901 mdss: display-subsystem@1a00000 {
906 reg-names = "mdss_phys",
909 power-domains = <&gcc MDSS_GDSC>;
912 interrupt-controller;
913 #interrupt-cells = <1>;
919 interconnect-names = "mdp0-mem",
920 "cpu-cfg";
926 clock-names = "iface",
933 #address-cells = <1>;
934 #size-cells = <1>;
939 mdp: display-controller@1a01000 {
940 compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
942 reg-names = "mdp_phys";
944 interrupt-parent = <&mdss>;
947 power-domains = <&gcc MDSS_GDSC>;
953 clock-names = "iface",
961 #address-cells = <1>;
962 #size-cells = <0>;
967 remote-endpoint = <&mdss_dsi0_in>;
974 remote-endpoint = <&mdss_dsi1_in>;
981 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
983 reg-names = "dsi_ctrl";
985 interrupt-parent = <&mdss>;
988 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
990 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
999 clock-names = "mdp_core",
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 remote-endpoint = <&mdp5_intf1_out>;
1033 compatible = "qcom,dsi-phy-14nm-8953";
1037 reg-names = "dsi_phy",
1041 #clock-cells = <1>;
1042 #phy-cells = <0>;
1045 clock-names = "iface", "ref";
1051 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1053 reg-names = "dsi_ctrl";
1055 interrupt-parent = <&mdss>;
1058 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1060 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
1069 clock-names = "mdp_core",
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1087 remote-endpoint = <&mdp5_intf2_out>;
1100 compatible = "qcom,dsi-phy-14nm-8953";
1104 reg-names = "dsi_phy",
1108 #clock-cells = <1>;
1109 #phy-cells = <0>;
1112 clock-names = "iface", "ref";
1119 compatible = "qcom,adreno-506.0", "qcom,adreno";
1121 reg-names = "kgsl_3d0_reg_memory";
1130 clock-names = "core",
1136 power-domains = <&gcc OXILI_GX_GDSC>;
1144 operating-points-v2 = <&gpu_opp_table>;
1146 #cooling-cells = <2>;
1150 zap-shader {
1151 memory-region = <&zap_shader_region>;
1154 gpu_opp_table: opp-table {
1155 compatible = "operating-points-v2";
1157 opp-19200000 {
1158 opp-hz = /bits/ 64 <19200000>;
1159 opp-supported-hw = <0xff>;
1160 required-opps = <&rpmpd_opp_min_svs>;
1163 opp-133300000 {
1164 opp-hz = /bits/ 64 <133300000>;
1165 opp-supported-hw = <0xff>;
1166 required-opps = <&rpmpd_opp_min_svs>;
1169 opp-216000000 {
1170 opp-hz = /bits/ 64 <216000000>;
1171 opp-supported-hw = <0xff>;
1172 required-opps = <&rpmpd_opp_low_svs>;
1175 opp-320000000 {
1176 opp-hz = /bits/ 64 <320000000>;
1177 opp-supported-hw = <0xff>;
1178 required-opps = <&rpmpd_opp_svs>;
1181 opp-400000000 {
1182 opp-hz = /bits/ 64 <400000000>;
1183 opp-supported-hw = <0xff>;
1184 required-opps = <&rpmpd_opp_svs_plus>;
1187 opp-510000000 {
1188 opp-hz = /bits/ 64 <510000000>;
1189 opp-supported-hw = <0xff>;
1190 required-opps = <&rpmpd_opp_nom>;
1193 opp-560000000 {
1194 opp-hz = /bits/ 64 <560000000>;
1195 opp-supported-hw = <0xff>;
1196 required-opps = <&rpmpd_opp_nom_plus>;
1203 opp-650000000 {
1204 opp-hz = /bits/ 64 <650000000>;
1205 opp-supported-hw = <0xff>;
1206 required-opps = <&rpmpd_opp_turbo>;
1212 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2";
1217 clock-names = "iface", "bus";
1219 power-domains = <&gcc OXILI_CX_GDSC>;
1221 qcom,iommu-secure-id = <18>;
1223 #address-cells = <1>;
1224 #iommu-cells = <1>;
1225 #size-cells = <1>;
1228 iommu-ctx@0 {
1229 compatible = "qcom,msm-iommu-v2-ns";
1235 iommu-ctx@2000 {
1236 compatible = "qcom,msm-iommu-v2-sec";
1243 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
1248 clock-names = "iface", "bus";
1250 qcom,iommu-secure-id = <17>;
1252 #address-cells = <1>;
1253 #iommu-cells = <1>;
1254 #size-cells = <1>;
1257 iommu-ctx@14000 {
1258 compatible = "qcom,msm-iommu-v1-ns";
1264 iommu-ctx@15000 {
1265 compatible = "qcom,msm-iommu-v1-ns";
1271 iommu-ctx@16000 {
1272 compatible = "qcom,msm-iommu-v1-ns";
1279 compatible = "qcom,spmi-pmic-arb";
1285 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1286 interrupt-names = "periph_irq";
1290 interrupt-controller;
1292 #interrupt-cells = <4>;
1293 #address-cells = <2>;
1294 #size-cells = <0>;
1297 mpss: remoteproc@4080000 { label
1298 compatible = "qcom,msm8953-mss-pil";
1301 reg-names = "qdsp6", "rmb";
1303 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1308 interrupt-names = "wdog", "fatal", "ready",
1309 "handover", "stop-ack";
1311 power-domains = <&rpmpd MSM8953_VDDCX>,
1314 power-domain-names = "cx", "mx","mss";
1320 clock-names = "iface", "bus", "mem", "xo";
1322 qcom,smem-states = <&smp2p_modem_out 0>;
1323 qcom,smem-state-names = "stop";
1326 reset-names = "mss_restart";
1328 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1333 memory-region = <&mba_mem>;
1336 mpss {
1337 memory-region = <&mpss_mem>;
1340 smd-edge {
1343 qcom,smd-edge = <0>;
1345 qcom,remote-pid = <1>;
1352 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
1354 #address-cells = <1>;
1355 #size-cells = <1>;
1361 interrupt-names = "pwr_event",
1370 clock-names = "cfg_noc",
1376 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1378 assigned-clock-rates = <19200000>, <133330000>;
1384 interconnect-names = "usb-ddr",
1385 "apps-usb";
1387 power-domains = <&gcc USB30_GDSC>;
1389 qcom,select-utmi-as-pipe-clk;
1398 phy-names = "usb2-phy";
1400 snps,usb2-gadget-lpm-disable;
1401 snps,dis-u1-entry-quirk;
1402 snps,dis-u2-entry-quirk;
1403 snps,is-utmi-l1-suspend;
1404 snps,hird-threshold = /bits/ 8 <0x00>;
1406 maximum-speed = "high-speed";
1408 usb-role-switch;
1411 #address-cells = <1>;
1412 #size-cells = <0>;
1425 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1428 reg-names = "hc", "core";
1432 interrupt-names = "hc_irq", "pwr_irq";
1437 clock-names = "iface", "core", "xo";
1443 interconnect-names = "sdhc-ddr",
1444 "cpu-sdhc";
1446 power-domains = <&rpmpd MSM8953_VDDCX>;
1447 operating-points-v2 = <&sdhc1_opp_table>;
1449 pinctrl-names = "default", "sleep";
1450 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1451 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
1453 mmc-hs400-1_8v;
1454 mmc-hs200-1_8v;
1455 mmc-ddr-1_8v;
1456 bus-width = <8>;
1457 non-removable;
1461 sdhc1_opp_table: opp-table-sdhc1 {
1462 compatible = "operating-points-v2";
1464 opp-25000000 {
1465 opp-hz = /bits/ 64 <25000000>;
1466 opp-peak-kBps = <200000>, <100000>;
1467 opp-avg-kBps = <65360>, <32768>;
1468 required-opps = <&rpmpd_opp_low_svs>;
1471 opp-50000000 {
1472 opp-hz = /bits/ 64 <50000000>;
1473 opp-peak-kBps = <400000>, <200000>;
1474 opp-avg-kBps = <130718>, <65360>;
1475 required-opps = <&rpmpd_opp_svs>;
1478 opp-100000000 {
1479 opp-hz = /bits/ 64 <100000000>;
1480 opp-peak-kBps = <400000>, <400000>;
1481 opp-avg-kBps = <130718>, <65360>;
1482 required-opps = <&rpmpd_opp_svs>;
1485 opp-192000000 {
1486 opp-hz = /bits/ 64 <192000000>;
1487 opp-peak-kBps = <800000>, <600000>;
1488 opp-avg-kBps = <261438>, <130718>;
1489 required-opps = <&rpmpd_opp_nom>;
1492 opp-384000000 {
1493 opp-hz = /bits/ 64 <384000000>;
1494 opp-peak-kBps = <800000>, <800000>;
1495 opp-avg-kBps = <261438>, <300000>;
1496 required-opps = <&rpmpd_opp_nom>;
1502 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1505 reg-names = "hc", "core";
1509 interrupt-names = "hc_irq", "pwr_irq";
1514 clock-names = "iface", "core", "xo";
1520 interconnect-names = "sdhc-ddr",
1521 "cpu-sdhc";
1523 power-domains = <&rpmpd MSM8953_VDDCX>;
1524 operating-points-v2 = <&sdhc2_opp_table>;
1526 pinctrl-names = "default", "sleep";
1527 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1528 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
1530 bus-width = <4>;
1534 sdhc2_opp_table: opp-table-sdhc2 {
1535 compatible = "operating-points-v2";
1537 opp-25000000 {
1538 opp-hz = /bits/ 64 <25000000>;
1539 opp-peak-kBps = <200000>, <100000>;
1540 opp-avg-kBps = <65360>, <32768>;
1541 required-opps = <&rpmpd_opp_low_svs>;
1544 opp-50000000 {
1545 opp-hz = /bits/ 64 <50000000>;
1546 opp-peak-kBps = <400000>, <400000>;
1547 opp-avg-kBps = <130718>, <65360>;
1548 required-opps = <&rpmpd_opp_svs>;
1551 opp-100000000 {
1552 opp-hz = /bits/ 64 <100000000>;
1553 opp-peak-kBps = <800000>, <400000>;
1554 opp-avg-kBps = <130718>, <130718>;
1555 required-opps = <&rpmpd_opp_svs>;
1558 opp-177770000 {
1559 opp-hz = /bits/ 64 <177770000>;
1560 opp-peak-kBps = <600000>, <600000>;
1561 opp-avg-kBps = <261438>, <130718>;
1562 required-opps = <&rpmpd_opp_nom>;
1565 opp-200000000 {
1566 opp-hz = /bits/ 64 <200000000>;
1567 opp-peak-kBps = <800000>, <800000>;
1568 opp-avg-kBps = <261438>, <130718>;
1569 required-opps = <&rpmpd_opp_nom>;
1574 blsp1_dma: dma-controller@7884000 {
1575 compatible = "qcom,bam-v1.7.0";
1579 clock-names = "bam_clk";
1580 num-channels = <12>;
1581 #dma-cells = <1>;
1583 qcom,num-ees = <4>;
1584 qcom,controlled-remotely;
1588 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1593 clock-names = "core", "iface";
1599 compatible = "qcom,i2c-qup-v2.2.1";
1602 clock-names = "core", "iface";
1606 dma-names = "tx", "rx";
1608 pinctrl-names = "default", "sleep";
1609 pinctrl-0 = <&i2c_1_default>;
1610 pinctrl-1 = <&i2c_1_sleep>;
1612 #address-cells = <1>;
1613 #size-cells = <0>;
1619 compatible = "qcom,i2c-qup-v2.2.1";
1622 clock-names = "core", "iface";
1626 dma-names = "tx", "rx";
1628 pinctrl-names = "default", "sleep";
1629 pinctrl-0 = <&i2c_2_default>;
1630 pinctrl-1 = <&i2c_2_sleep>;
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1639 compatible = "qcom,i2c-qup-v2.2.1";
1642 clock-names = "core", "iface";
1646 dma-names = "tx", "rx";
1648 pinctrl-names = "default", "sleep";
1649 pinctrl-0 = <&i2c_3_default>;
1650 pinctrl-1 = <&i2c_3_sleep>;
1652 #address-cells = <1>;
1653 #size-cells = <0>;
1659 compatible = "qcom,spi-qup-v2.2.1";
1662 clock-names = "core", "iface";
1666 dma-names = "tx", "rx";
1668 pinctrl-names = "default", "sleep";
1669 pinctrl-0 = <&spi_3_default>;
1670 pinctrl-1 = <&spi_3_sleep>;
1672 #address-cells = <1>;
1673 #size-cells = <0>;
1679 compatible = "qcom,i2c-qup-v2.2.1";
1682 clock-names = "core", "iface";
1686 dma-names = "tx", "rx";
1688 pinctrl-names = "default", "sleep";
1689 pinctrl-0 = <&i2c_4_default>;
1690 pinctrl-1 = <&i2c_4_sleep>;
1692 #address-cells = <1>;
1693 #size-cells = <0>;
1698 blsp2_dma: dma-controller@7ac4000 {
1699 compatible = "qcom,bam-v1.7.0";
1703 clock-names = "bam_clk";
1704 num-channels = <12>;
1705 #dma-cells = <1>;
1707 qcom,num-ees = <4>;
1708 qcom,controlled-remotely;
1712 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1717 clock-names = "core",
1720 dma-names = "tx", "rx";
1722 pinctrl-0 = <&uart_5_default>;
1723 pinctrl-1 = <&uart_5_sleep>;
1724 pinctrl-names = "default", "sleep";
1730 compatible = "qcom,i2c-qup-v2.2.1";
1733 clock-names = "core", "iface";
1737 dma-names = "tx", "rx";
1739 pinctrl-names = "default", "sleep";
1740 pinctrl-0 = <&i2c_5_default>;
1741 pinctrl-1 = <&i2c_5_sleep>;
1743 #address-cells = <1>;
1744 #size-cells = <0>;
1750 compatible = "qcom,spi-qup-v2.2.1";
1753 clock-names = "core", "iface";
1757 dma-names = "tx", "rx";
1759 pinctrl-names = "default", "sleep";
1760 pinctrl-0 = <&spi_5_default>;
1761 pinctrl-1 = <&spi_5_sleep>;
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1770 compatible = "qcom,i2c-qup-v2.2.1";
1773 clock-names = "core", "iface";
1777 dma-names = "tx", "rx";
1779 pinctrl-names = "default", "sleep";
1780 pinctrl-0 = <&i2c_6_default>;
1781 pinctrl-1 = <&i2c_6_sleep>;
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1790 compatible = "qcom,spi-qup-v2.2.1";
1793 clock-names = "core", "iface";
1797 dma-names = "tx", "rx";
1799 pinctrl-names = "default", "sleep";
1800 pinctrl-0 = <&spi_6_default>;
1801 pinctrl-1 = <&spi_6_sleep>;
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1810 compatible = "qcom,i2c-qup-v2.2.1";
1813 clock-names = "core", "iface";
1817 dma-names = "tx", "rx";
1819 pinctrl-names = "default", "sleep";
1820 pinctrl-0 = <&i2c_7_default>;
1821 pinctrl-1 = <&i2c_7_sleep>;
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1830 compatible = "qcom,i2c-qup-v2.2.1";
1833 clock-names = "core", "iface";
1837 dma-names = "tx", "rx";
1839 pinctrl-names = "default", "sleep";
1840 pinctrl-0 = <&i2c_8_default>;
1841 pinctrl-1 = <&i2c_8_sleep>;
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1850 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1852 reg-names = "ccu", "dxe", "pmu";
1854 memory-region = <&wcnss_fw_mem>;
1856 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1861 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1863 power-domains = <&rpmpd MSM8953_VDDCX>,
1865 power-domain-names = "cx", "mx";
1867 qcom,smem-states = <&smp2p_wcnss_out 0>;
1868 qcom,smem-state-names = "stop";
1870 pinctrl-names = "default";
1871 pinctrl-0 = <&wcnss_pin_a>;
1876 /* Separate chip, compatible is board-specific */
1878 clock-names = "xo";
1881 smd-edge {
1885 qcom,smd-edge = <6>;
1886 qcom,remote-pid = <4>;
1892 qcom,smd-channels = "WCNSS_CTRL";
1897 compatible = "qcom,wcnss-bt";
1901 compatible = "qcom,wcnss-wlan";
1905 interrupt-names = "tx", "rx";
1907 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1908 qcom,smem-state-names = "tx-enable",
1909 "tx-rings-empty";
1915 intc: interrupt-controller@b000000 {
1916 compatible = "qcom,msm-qgic2";
1917 interrupt-controller;
1918 #interrupt-cells = <3>;
1923 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1925 #mbox-cells = <1>;
1929 compatible = "arm,armv7-timer-mem";
1931 #address-cells = <1>;
1932 #size-cells = <1>;
1936 frame-number = <0>;
1944 frame-number = <1>;
1951 frame-number = <2>;
1958 frame-number = <3>;
1965 frame-number = <4>;
1972 frame-number = <5>;
1979 frame-number = <6>;
1987 compatible = "qcom,msm8953-adsp-pil";
1990 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1995 interrupt-names = "wdog", "fatal", "ready",
1996 "handover", "stop-ack";
1998 clock-names = "xo";
2000 power-domains = <&rpmpd MSM8953_VDDCX>;
2001 power-domain-names = "cx";
2003 memory-region = <&adsp_fw_mem>;
2005 qcom,smem-states = <&smp2p_adsp_out 0>;
2006 qcom,smem-state-names = "stop";
2010 smd-edge {
2015 qcom,smd-edge = <1>;
2016 qcom,remote-pid = <2>;
2019 compatible = "qcom,apr-v2";
2020 qcom,smd-channels = "apr_audio_svc";
2022 #address-cells = <1>;
2023 #size-cells = <0>;
2034 compatible = "qcom,q6afe-dais";
2035 #address-cells = <1>;
2036 #size-cells = <0>;
2037 #sound-dai-cells = <1>;
2041 qcom,sd-lines = <0 1>;
2045 qcom,sd-lines = <0 1>;
2049 qcom,sd-lines = <0>;
2053 q6afecc: clock-controller {
2054 compatible = "qcom,q6afe-clocks";
2055 #clock-cells = <2>;
2063 compatible = "qcom,q6asm-dais";
2064 #address-cells = <1>;
2065 #size-cells = <0>;
2066 #sound-dai-cells = <1>;
2083 is-compress-dai;
2092 compatible = "qcom,q6adm-routing";
2093 #sound-dai-cells = <0>;
2101 thermal-zones {
2102 cpu0-thermal {
2103 polling-delay-passive = <250>;
2105 thermal-sensors = <&tsens0 9>;
2108 cpu0_alert: trip-point0 {
2119 cooling-maps {
2122 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2126 cpu1-thermal {
2127 polling-delay-passive = <250>;
2129 thermal-sensors = <&tsens0 10>;
2132 cpu1_alert: trip-point0 {
2143 cooling-maps {
2146 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2150 cpu2-thermal {
2151 polling-delay-passive = <250>;
2153 thermal-sensors = <&tsens0 11>;
2156 cpu2_alert: trip-point0 {
2167 cooling-maps {
2170 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2174 cpu3-thermal {
2175 polling-delay-passive = <250>;
2177 thermal-sensors = <&tsens0 12>;
2180 cpu3_alert: trip-point0 {
2191 cooling-maps {
2194 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2198 cpu4-thermal {
2199 polling-delay-passive = <250>;
2200 thermal-sensors = <&tsens0 4>;
2202 cpu4_alert: trip-point0 {
2213 cooling-maps {
2216 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2220 cpu5-thermal {
2221 polling-delay-passive = <250>;
2222 thermal-sensors = <&tsens0 5>;
2224 cpu5_alert: trip-point0 {
2235 cooling-maps {
2238 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2242 cpu6-thermal {
2243 polling-delay-passive = <250>;
2244 thermal-sensors = <&tsens0 6>;
2246 cpu6_alert: trip-point0 {
2257 cooling-maps {
2260 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2264 cpu7-thermal {
2265 polling-delay-passive = <250>;
2266 thermal-sensors = <&tsens0 7>;
2268 cpu7_alert: trip-point0 {
2279 cooling-maps {
2282 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2287 gpu-thermal {
2288 polling-delay-passive = <250>;
2289 thermal-sensors = <&tsens0 15>;
2292 gpu_alert: trip-point0 {
2305 cooling-maps {
2308 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2315 compatible = "arm,armv8-timer";