Lines Matching +full:q6afe +full:- +full:clocks
1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
22 clocks {
23 sleep_clk: sleep-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <32768>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <19200000>;
33 clock-output-names = "xo";
38 #address-cells = <1>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 capacity-dmips-mhz = <1024>;
47 next-level-cache = <&L2_0>;
48 #cooling-cells = <2>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
58 #cooling-cells = <2>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 capacity-dmips-mhz = <1024>;
67 next-level-cache = <&L2_0>;
68 #cooling-cells = <2>;
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 capacity-dmips-mhz = <1024>;
77 next-level-cache = <&L2_0>;
78 #cooling-cells = <2>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <1024>;
87 next-level-cache = <&L2_1>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a53";
95 enable-method = "psci";
96 capacity-dmips-mhz = <1024>;
97 next-level-cache = <&L2_1>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 enable-method = "psci";
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&L2_1>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a53";
115 enable-method = "psci";
116 capacity-dmips-mhz = <1024>;
117 next-level-cache = <&L2_1>;
118 #cooling-cells = <2>;
121 cpu-map {
153 L2_0: l2-cache-0 {
155 cache-level = <2>;
156 cache-unified;
159 L2_1: l2-cache-1 {
161 cache-level = <2>;
162 cache-unified;
168 compatible = "qcom,scm-msm8953", "qcom,scm";
169 clocks = <&gcc GCC_CRYPTO_CLK>,
172 clock-names = "core", "bus", "iface";
173 #reset-cells = <1>;
184 compatible = "arm,cortex-a53-pmu";
189 compatible = "arm,psci-1.0";
194 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc";
196 smd-edge {
199 qcom,smd-edge = <15>;
201 rpm_requests: rpm-requests {
202 compatible = "qcom,rpm-msm8953", "qcom,smd-rpm";
203 qcom,smd-channels = "rpm_requests";
205 rpmcc: clock-controller {
206 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
207 clocks = <&xo_board>;
208 clock-names = "xo";
209 #clock-cells = <1>;
212 rpmpd: power-controller {
213 compatible = "qcom,msm8953-rpmpd";
214 #power-domain-cells = <1>;
215 operating-points-v2 = <&rpmpd_opp_table>;
217 rpmpd_opp_table: opp-table {
218 compatible = "operating-points-v2";
221 opp-level = <RPM_SMD_LEVEL_RETENTION>;
225 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
229 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
233 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
237 opp-level = <RPM_SMD_LEVEL_SVS>;
241 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
245 opp-level = <RPM_SMD_LEVEL_NOM>;
249 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
253 opp-level = <RPM_SMD_LEVEL_TURBO>;
261 reserved-memory {
262 #address-cells = <2>;
263 #size-cells = <2>;
267 compatible = "shared-dma-pool";
269 no-map;
274 no-map;
280 qcom,rpm-msg-ram = <&rpm_msg_ram>;
282 no-map;
287 no-map;
292 no-map;
297 no-map;
302 no-map;
305 dfps_data_mem: dfps-data@90000000 {
307 no-map;
310 cont_splash_mem: cont-splash@90001000 {
312 no-map;
317 no-map;
322 no-map;
326 compatible = "qcom,rmtfs-mem";
328 no-map;
330 qcom,client-id = <1>;
334 smp2p-adsp {
342 qcom,local-pid = <0>;
343 qcom,remote-pid = <2>;
345 smp2p_adsp_out: master-kernel {
346 qcom,entry-name = "master-kernel";
347 #qcom,smem-state-cells = <1>;
350 smp2p_adsp_in: slave-kernel {
351 qcom,entry-name = "slave-kernel";
353 interrupt-controller;
354 #interrupt-cells = <2>;
358 smp2p-modem {
366 qcom,local-pid = <0>;
367 qcom,remote-pid = <1>;
369 smp2p_modem_out: master-kernel {
370 qcom,entry-name = "master-kernel";
372 #qcom,smem-state-cells = <1>;
375 smp2p_modem_in: slave-kernel {
376 qcom,entry-name = "slave-kernel";
378 interrupt-controller;
379 #interrupt-cells = <2>;
383 smp2p-wcnss {
391 qcom,local-pid = <0>;
392 qcom,remote-pid = <4>;
394 smp2p_wcnss_out: master-kernel {
395 qcom,entry-name = "master-kernel";
397 #qcom,smem-state-cells = <1>;
400 smp2p_wcnss_in: slave-kernel {
401 qcom,entry-name = "slave-kernel";
403 interrupt-controller;
404 #interrupt-cells = <2>;
411 #address-cells = <1>;
412 #size-cells = <0>;
419 #qcom,smem-state-cells = <1>;
426 interrupt-controller;
427 #interrupt-cells = <2>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
440 #address-cells = <1>;
441 #size-cells = <1>;
443 compatible = "simple-bus";
446 compatible = "qcom,rpm-msg-ram";
451 compatible = "qcom,msm8953-qusb2-phy";
453 #phy-cells = <0>;
455 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
457 clock-names = "cfg_ahb", "ref";
459 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
469 clocks = <&gcc GCC_PRNG_AHB_CLK>;
470 clock-names = "core";
473 tsens0: thermal-sensor@4a9000 {
474 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
480 interrupt-names = "uplow", "critical";
481 #thermal-sensor-cells = <1>;
490 compatible = "qcom,msm8953-pinctrl";
493 gpio-controller;
494 gpio-ranges = <&tlmm 0 0 142>;
495 #gpio-cells = <2>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
499 uart_console_active: uart-console-active-state {
502 drive-strength = <2>;
503 bias-disable;
506 uart_console_sleep: uart-console-sleep-state {
509 drive-strength = <2>;
510 bias-pull-down;
513 sdc1_clk_on: sdc1-clk-on-state {
515 bias-disable;
516 drive-strength = <16>;
519 sdc1_clk_off: sdc1-clk-off-state {
521 bias-disable;
522 drive-strength = <2>;
525 sdc1_cmd_on: sdc1-cmd-on-state {
527 bias-disable;
528 drive-strength = <10>;
531 sdc1_cmd_off: sdc1-cmd-off-state {
533 bias-disable;
534 drive-strength = <2>;
537 sdc1_data_on: sdc1-data-on-state {
539 bias-pull-up;
540 drive-strength = <10>;
543 sdc1_data_off: sdc1-data-off-state {
545 bias-pull-up;
546 drive-strength = <2>;
549 sdc1_rclk_on: sdc1-rclk-on-state {
551 bias-pull-down;
554 sdc1_rclk_off: sdc1-rclk-off-state {
556 bias-pull-down;
559 sdc2_clk_on: sdc2-clk-on-state {
561 drive-strength = <16>;
562 bias-disable;
565 sdc2_clk_off: sdc2-clk-off-state {
567 bias-disable;
568 drive-strength = <2>;
571 sdc2_cmd_on: sdc2-cmd-on-state {
573 bias-pull-up;
574 drive-strength = <10>;
577 sdc2_cmd_off: sdc2-cmd-off-state {
579 bias-pull-up;
580 drive-strength = <2>;
583 sdc2_data_on: sdc2-data-on-state {
585 bias-pull-up;
586 drive-strength = <10>;
589 sdc2_data_off: sdc2-data-off-state {
591 bias-pull-up;
592 drive-strength = <2>;
595 sdc2_cd_on: cd-on-state {
598 drive-strength = <2>;
599 bias-pull-up;
602 sdc2_cd_off: cd-off-state {
605 drive-strength = <2>;
606 bias-disable;
609 gpio_key_default: gpio-key-default-state {
612 drive-strength = <2>;
613 bias-pull-up;
616 i2c_1_default: i2c-1-default-state {
619 drive-strength = <2>;
620 bias-disable;
623 i2c_1_sleep: i2c-1-sleep-state {
626 drive-strength = <2>;
627 bias-disable;
630 i2c_2_default: i2c-2-default-state {
633 drive-strength = <2>;
634 bias-disable;
637 i2c_2_sleep: i2c-2-sleep-state {
640 drive-strength = <2>;
641 bias-disable;
644 i2c_3_default: i2c-3-default-state {
647 drive-strength = <2>;
648 bias-disable;
651 i2c_3_sleep: i2c-3-sleep-state {
654 drive-strength = <2>;
655 bias-disable;
658 i2c_4_default: i2c-4-default-state {
661 drive-strength = <2>;
662 bias-disable;
665 i2c_4_sleep: i2c-4-sleep-state {
668 drive-strength = <2>;
669 bias-disable;
672 i2c_5_default: i2c-5-default-state {
675 drive-strength = <2>;
676 bias-disable;
679 i2c_5_sleep: i2c-5-sleep-state {
682 drive-strength = <2>;
683 bias-disable;
686 i2c_6_default: i2c-6-default-state {
689 drive-strength = <2>;
690 bias-disable;
693 i2c_6_sleep: i2c-6-sleep-state {
696 drive-strength = <2>;
697 bias-disable;
700 i2c_7_default: i2c-7-default-state {
703 drive-strength = <2>;
704 bias-disable;
707 i2c_7_sleep: i2c-7-sleep-state {
710 drive-strength = <2>;
711 bias-disable;
714 i2c_8_default: i2c-8-default-state {
717 drive-strength = <2>;
718 bias-disable;
721 i2c_8_sleep: i2c-8-sleep-state {
724 drive-strength = <2>;
725 bias-disable;
728 spi_3_default: spi-3-default-state {
731 drive-strength = <2>;
732 bias-disable;
735 spi_3_sleep: spi-3-sleep-state {
738 drive-strength = <2>;
739 bias-disable;
742 spi_5_default: spi-5-default-state {
745 drive-strength = <2>;
746 bias-disable;
749 spi_5_sleep: spi-5-sleep-state {
752 drive-strength = <2>;
753 bias-disable;
756 spi_6_default: spi-6-default-state {
759 drive-strength = <2>;
760 bias-disable;
763 spi_6_sleep: spi-6-sleep-state {
766 drive-strength = <2>;
767 bias-disable;
770 wcnss_pin_a: wcnss-active-state {
772 wcss-wlan2-pins {
775 drive-strength = <6>;
776 bias-pull-up;
779 wcss-wlan1-pins {
782 drive-strength = <6>;
783 bias-pull-up;
786 wcss-wlan0-pins {
789 drive-strength = <6>;
790 bias-pull-up;
793 wcss-wlan-pins {
796 drive-strength = <6>;
797 bias-pull-up;
802 gcc: clock-controller@1800000 {
803 compatible = "qcom,gcc-msm8953";
805 #clock-cells = <1>;
806 #reset-cells = <1>;
807 #power-domain-cells = <1>;
808 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
814 clock-names = "xo",
823 compatible = "qcom,tcsr-mutex";
825 #hwlock-cells = <1>;
829 compatible = "qcom,tcsr-msm8953", "syscon";
834 compatible = "qcom,tcsr-msm8953", "syscon";
838 mdss: display-subsystem@1a00000 {
843 reg-names = "mdss_phys",
846 power-domains = <&gcc MDSS_GDSC>;
849 interrupt-controller;
850 #interrupt-cells = <1>;
852 clocks = <&gcc GCC_MDSS_AHB_CLK>,
856 clock-names = "iface",
863 #address-cells = <1>;
864 #size-cells = <1>;
869 mdp: display-controller@1a01000 {
870 compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
872 reg-names = "mdp_phys";
874 interrupt-parent = <&mdss>;
877 power-domains = <&gcc MDSS_GDSC>;
879 clocks = <&gcc GCC_MDSS_AHB_CLK>,
883 clock-names = "iface",
891 #address-cells = <1>;
892 #size-cells = <0>;
897 remote-endpoint = <&mdss_dsi0_in>;
904 remote-endpoint = <&mdss_dsi1_in>;
911 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
913 reg-names = "dsi_ctrl";
915 interrupt-parent = <&mdss>;
918 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
920 assigned-clock-parents = <&mdss_dsi0_phy 0>,
923 clocks = <&gcc GCC_MDSS_MDP_CLK>,
929 clock-names = "mdp_core",
938 #address-cells = <1>;
939 #size-cells = <0>;
944 #address-cells = <1>;
945 #size-cells = <0>;
950 remote-endpoint = <&mdp5_intf1_out>;
963 compatible = "qcom,dsi-phy-14nm-8953";
967 reg-names = "dsi_phy",
971 #clock-cells = <1>;
972 #phy-cells = <0>;
974 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
975 clock-names = "iface", "ref";
981 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
983 reg-names = "dsi_ctrl";
985 interrupt-parent = <&mdss>;
988 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
990 assigned-clock-parents = <&mdss_dsi1_phy 0>,
993 clocks = <&gcc GCC_MDSS_MDP_CLK>,
999 clock-names = "mdp_core",
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1017 remote-endpoint = <&mdp5_intf2_out>;
1030 compatible = "qcom,dsi-phy-14nm-8953";
1034 reg-names = "dsi_phy",
1038 #clock-cells = <1>;
1039 #phy-cells = <0>;
1041 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1042 clock-names = "iface", "ref";
1049 compatible = "qcom,adreno-506.0", "qcom,adreno";
1051 reg-names = "kgsl_3d0_reg_memory";
1054 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1060 clock-names = "core",
1066 power-domains = <&gcc OXILI_GX_GDSC>;
1069 operating-points-v2 = <&gpu_opp_table>;
1071 #cooling-cells = <2>;
1075 zap-shader {
1076 memory-region = <&zap_shader_region>;
1079 gpu_opp_table: opp-table {
1080 compatible = "operating-points-v2";
1082 opp-19200000 {
1083 opp-hz = /bits/ 64 <19200000>;
1084 opp-supported-hw = <0xff>;
1085 required-opps = <&rpmpd_opp_min_svs>;
1088 opp-133300000 {
1089 opp-hz = /bits/ 64 <133300000>;
1090 opp-supported-hw = <0xff>;
1091 required-opps = <&rpmpd_opp_min_svs>;
1094 opp-216000000 {
1095 opp-hz = /bits/ 64 <216000000>;
1096 opp-supported-hw = <0xff>;
1097 required-opps = <&rpmpd_opp_low_svs>;
1100 opp-320000000 {
1101 opp-hz = /bits/ 64 <320000000>;
1102 opp-supported-hw = <0xff>;
1103 required-opps = <&rpmpd_opp_svs>;
1106 opp-400000000 {
1107 opp-hz = /bits/ 64 <400000000>;
1108 opp-supported-hw = <0xff>;
1109 required-opps = <&rpmpd_opp_svs_plus>;
1112 opp-510000000 {
1113 opp-hz = /bits/ 64 <510000000>;
1114 opp-supported-hw = <0xff>;
1115 required-opps = <&rpmpd_opp_nom>;
1118 opp-560000000 {
1119 opp-hz = /bits/ 64 <560000000>;
1120 opp-supported-hw = <0xff>;
1121 required-opps = <&rpmpd_opp_nom_plus>;
1128 opp-650000000 {
1129 opp-hz = /bits/ 64 <650000000>;
1130 opp-supported-hw = <0xff>;
1131 required-opps = <&rpmpd_opp_turbo>;
1137 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2";
1140 clocks = <&gcc GCC_OXILI_AHB_CLK>,
1142 clock-names = "iface", "bus";
1144 power-domains = <&gcc OXILI_CX_GDSC>;
1146 qcom,iommu-secure-id = <18>;
1148 #address-cells = <1>;
1149 #iommu-cells = <1>;
1150 #size-cells = <1>;
1153 iommu-ctx@0 {
1154 compatible = "qcom,msm-iommu-v2-ns";
1160 iommu-ctx@2000 {
1161 compatible = "qcom,msm-iommu-v2-sec";
1168 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
1171 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1173 clock-names = "iface", "bus";
1175 qcom,iommu-secure-id = <17>;
1177 #address-cells = <1>;
1178 #iommu-cells = <1>;
1179 #size-cells = <1>;
1182 iommu-ctx@14000 {
1183 compatible = "qcom,msm-iommu-v1-ns";
1189 iommu-ctx@15000 {
1190 compatible = "qcom,msm-iommu-v1-ns";
1196 iommu-ctx@16000 {
1197 compatible = "qcom,msm-iommu-v1-ns";
1204 compatible = "qcom,spmi-pmic-arb";
1210 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1211 interrupt-names = "periph_irq";
1215 interrupt-controller;
1217 #interrupt-cells = <4>;
1218 #address-cells = <2>;
1219 #size-cells = <0>;
1223 compatible = "qcom,msm8953-mss-pil";
1226 reg-names = "qdsp6", "rmb";
1228 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1233 interrupt-names = "wdog", "fatal", "ready",
1234 "handover", "stop-ack";
1236 power-domains = <&rpmpd MSM8953_VDDCX>,
1239 power-domain-names = "cx", "mx","mss";
1241 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1245 clock-names = "iface", "bus", "mem", "xo";
1247 qcom,smem-states = <&smp2p_modem_out 0>;
1248 qcom,smem-state-names = "stop";
1251 reset-names = "mss_restart";
1253 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1258 memory-region = <&mba_mem>;
1262 memory-region = <&mpss_mem>;
1265 smd-edge {
1268 qcom,smd-edge = <0>;
1270 qcom,remote-pid = <1>;
1277 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
1279 #address-cells = <1>;
1280 #size-cells = <1>;
1286 interrupt-names = "pwr_event",
1290 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
1295 clock-names = "cfg_noc",
1301 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1303 assigned-clock-rates = <19200000>, <133330000>;
1305 power-domains = <&gcc USB30_GDSC>;
1307 qcom,select-utmi-as-pipe-clk;
1316 phy-names = "usb2-phy";
1318 snps,usb2-gadget-lpm-disable;
1319 snps,dis-u1-entry-quirk;
1320 snps,dis-u2-entry-quirk;
1321 snps,is-utmi-l1-suspend;
1322 snps,hird-threshold = /bits/ 8 <0x00>;
1324 maximum-speed = "high-speed";
1326 usb-role-switch;
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1343 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1346 reg-names = "hc", "core";
1350 interrupt-names = "hc_irq", "pwr_irq";
1352 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1355 clock-names = "iface", "core", "xo";
1357 power-domains = <&rpmpd MSM8953_VDDCX>;
1358 operating-points-v2 = <&sdhc1_opp_table>;
1360 pinctrl-names = "default", "sleep";
1361 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1362 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
1364 mmc-hs400-1_8v;
1365 mmc-hs200-1_8v;
1366 mmc-ddr-1_8v;
1367 bus-width = <8>;
1368 non-removable;
1372 sdhc1_opp_table: opp-table-sdhc1 {
1373 compatible = "operating-points-v2";
1375 opp-25000000 {
1376 opp-hz = /bits/ 64 <25000000>;
1377 required-opps = <&rpmpd_opp_low_svs>;
1380 opp-50000000 {
1381 opp-hz = /bits/ 64 <50000000>;
1382 required-opps = <&rpmpd_opp_svs>;
1385 opp-100000000 {
1386 opp-hz = /bits/ 64 <100000000>;
1387 required-opps = <&rpmpd_opp_svs>;
1390 opp-192000000 {
1391 opp-hz = /bits/ 64 <192000000>;
1392 required-opps = <&rpmpd_opp_nom>;
1395 opp-384000000 {
1396 opp-hz = /bits/ 64 <384000000>;
1397 required-opps = <&rpmpd_opp_nom>;
1403 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1406 reg-names = "hc", "core";
1410 interrupt-names = "hc_irq", "pwr_irq";
1412 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1415 clock-names = "iface", "core", "xo";
1417 power-domains = <&rpmpd MSM8953_VDDCX>;
1418 operating-points-v2 = <&sdhc2_opp_table>;
1420 pinctrl-names = "default", "sleep";
1421 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1422 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
1424 bus-width = <4>;
1428 sdhc2_opp_table: opp-table-sdhc2 {
1429 compatible = "operating-points-v2";
1431 opp-25000000 {
1432 opp-hz = /bits/ 64 <25000000>;
1433 required-opps = <&rpmpd_opp_low_svs>;
1436 opp-50000000 {
1437 opp-hz = /bits/ 64 <50000000>;
1438 required-opps = <&rpmpd_opp_svs>;
1441 opp-100000000 {
1442 opp-hz = /bits/ 64 <100000000>;
1443 required-opps = <&rpmpd_opp_svs>;
1446 opp-177770000 {
1447 opp-hz = /bits/ 64 <177770000>;
1448 required-opps = <&rpmpd_opp_nom>;
1451 opp-200000000 {
1452 opp-hz = /bits/ 64 <200000000>;
1453 required-opps = <&rpmpd_opp_nom>;
1458 blsp1_dma: dma-controller@7884000 {
1459 compatible = "qcom,bam-v1.7.0";
1462 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1463 clock-names = "bam_clk";
1464 num-channels = <12>;
1465 #dma-cells = <1>;
1467 qcom,num-ees = <4>;
1468 qcom,controlled-remotely;
1472 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1475 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1477 clock-names = "core", "iface";
1483 compatible = "qcom,i2c-qup-v2.2.1";
1486 clock-names = "core", "iface";
1487 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1490 dma-names = "tx", "rx";
1492 pinctrl-names = "default", "sleep";
1493 pinctrl-0 = <&i2c_1_default>;
1494 pinctrl-1 = <&i2c_1_sleep>;
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1503 compatible = "qcom,i2c-qup-v2.2.1";
1506 clock-names = "core", "iface";
1507 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1510 dma-names = "tx", "rx";
1512 pinctrl-names = "default", "sleep";
1513 pinctrl-0 = <&i2c_2_default>;
1514 pinctrl-1 = <&i2c_2_sleep>;
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1523 compatible = "qcom,i2c-qup-v2.2.1";
1526 clock-names = "core", "iface";
1527 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1530 dma-names = "tx", "rx";
1532 pinctrl-names = "default", "sleep";
1533 pinctrl-0 = <&i2c_3_default>;
1534 pinctrl-1 = <&i2c_3_sleep>;
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1543 compatible = "qcom,spi-qup-v2.2.1";
1546 clock-names = "core", "iface";
1547 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1550 dma-names = "tx", "rx";
1552 pinctrl-names = "default", "sleep";
1553 pinctrl-0 = <&spi_3_default>;
1554 pinctrl-1 = <&spi_3_sleep>;
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1563 compatible = "qcom,i2c-qup-v2.2.1";
1566 clock-names = "core", "iface";
1567 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1570 dma-names = "tx", "rx";
1572 pinctrl-names = "default", "sleep";
1573 pinctrl-0 = <&i2c_4_default>;
1574 pinctrl-1 = <&i2c_4_sleep>;
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1582 blsp2_dma: dma-controller@7ac4000 {
1583 compatible = "qcom,bam-v1.7.0";
1586 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1587 clock-names = "bam_clk";
1588 num-channels = <12>;
1589 #dma-cells = <1>;
1591 qcom,num-ees = <4>;
1592 qcom,controlled-remotely;
1596 compatible = "qcom,i2c-qup-v2.2.1";
1599 clock-names = "core", "iface";
1600 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1603 dma-names = "tx", "rx";
1605 pinctrl-names = "default", "sleep";
1606 pinctrl-0 = <&i2c_5_default>;
1607 pinctrl-1 = <&i2c_5_sleep>;
1609 #address-cells = <1>;
1610 #size-cells = <0>;
1616 compatible = "qcom,spi-qup-v2.2.1";
1619 clock-names = "core", "iface";
1620 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1623 dma-names = "tx", "rx";
1625 pinctrl-names = "default", "sleep";
1626 pinctrl-0 = <&spi_5_default>;
1627 pinctrl-1 = <&spi_5_sleep>;
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1636 compatible = "qcom,i2c-qup-v2.2.1";
1639 clock-names = "core", "iface";
1640 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1643 dma-names = "tx", "rx";
1645 pinctrl-names = "default", "sleep";
1646 pinctrl-0 = <&i2c_6_default>;
1647 pinctrl-1 = <&i2c_6_sleep>;
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1656 compatible = "qcom,spi-qup-v2.2.1";
1659 clock-names = "core", "iface";
1660 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1663 dma-names = "tx", "rx";
1665 pinctrl-names = "default", "sleep";
1666 pinctrl-0 = <&spi_6_default>;
1667 pinctrl-1 = <&spi_6_sleep>;
1669 #address-cells = <1>;
1670 #size-cells = <0>;
1676 compatible = "qcom,i2c-qup-v2.2.1";
1679 clock-names = "core", "iface";
1680 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1683 dma-names = "tx", "rx";
1685 pinctrl-names = "default", "sleep";
1686 pinctrl-0 = <&i2c_7_default>;
1687 pinctrl-1 = <&i2c_7_sleep>;
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1696 compatible = "qcom,i2c-qup-v2.2.1";
1699 clock-names = "core", "iface";
1700 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1703 dma-names = "tx", "rx";
1705 pinctrl-names = "default", "sleep";
1706 pinctrl-0 = <&i2c_8_default>;
1707 pinctrl-1 = <&i2c_8_sleep>;
1709 #address-cells = <1>;
1710 #size-cells = <0>;
1716 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1718 reg-names = "ccu", "dxe", "pmu";
1720 memory-region = <&wcnss_fw_mem>;
1722 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1727 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1729 power-domains = <&rpmpd MSM8953_VDDCX>,
1731 power-domain-names = "cx", "mx";
1733 qcom,smem-states = <&smp2p_wcnss_out 0>;
1734 qcom,smem-state-names = "stop";
1736 pinctrl-names = "default";
1737 pinctrl-0 = <&wcnss_pin_a>;
1742 /* Separate chip, compatible is board-specific */
1743 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1744 clock-names = "xo";
1747 smd-edge {
1751 qcom,smd-edge = <6>;
1752 qcom,remote-pid = <4>;
1758 qcom,smd-channels = "WCNSS_CTRL";
1763 compatible = "qcom,wcnss-bt";
1767 compatible = "qcom,wcnss-wlan";
1771 interrupt-names = "tx", "rx";
1773 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1774 qcom,smem-state-names = "tx-enable",
1775 "tx-rings-empty";
1781 intc: interrupt-controller@b000000 {
1782 compatible = "qcom,msm-qgic2";
1783 interrupt-controller;
1784 #interrupt-cells = <3>;
1789 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1791 #mbox-cells = <1>;
1795 compatible = "arm,armv7-timer-mem";
1797 #address-cells = <1>;
1798 #size-cells = <1>;
1802 frame-number = <0>;
1810 frame-number = <1>;
1817 frame-number = <2>;
1824 frame-number = <3>;
1831 frame-number = <4>;
1838 frame-number = <5>;
1845 frame-number = <6>;
1853 compatible = "qcom,msm8953-adsp-pil";
1856 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1861 interrupt-names = "wdog", "fatal", "ready",
1862 "handover", "stop-ack";
1863 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1864 clock-names = "xo";
1866 power-domains = <&rpmpd MSM8953_VDDCX>;
1867 power-domain-names = "cx";
1869 memory-region = <&adsp_fw_mem>;
1871 qcom,smem-states = <&smp2p_adsp_out 0>;
1872 qcom,smem-state-names = "stop";
1876 smd-edge {
1881 qcom,smd-edge = <1>;
1882 qcom,remote-pid = <2>;
1885 compatible = "qcom,apr-v2";
1886 qcom,smd-channels = "apr_audio_svc";
1888 #address-cells = <1>;
1889 #size-cells = <0>;
1896 q6afe: service@4 { label
1897 compatible = "qcom,q6afe";
1900 compatible = "qcom,q6afe-dais";
1901 #address-cells = <1>;
1902 #size-cells = <0>;
1903 #sound-dai-cells = <1>;
1907 qcom,sd-lines = <0 1>;
1911 qcom,sd-lines = <0 1>;
1915 qcom,sd-lines = <0>;
1919 q6afecc: clock-controller {
1920 compatible = "qcom,q6afe-clocks";
1921 #clock-cells = <2>;
1929 compatible = "qcom,q6asm-dais";
1930 #address-cells = <1>;
1931 #size-cells = <0>;
1932 #sound-dai-cells = <1>;
1949 is-compress-dai;
1958 compatible = "qcom,q6adm-routing";
1959 #sound-dai-cells = <0>;
1967 thermal-zones {
1968 cpu0-thermal {
1969 polling-delay-passive = <250>;
1971 thermal-sensors = <&tsens0 9>;
1974 cpu0_alert: trip-point0 {
1985 cooling-maps {
1988 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1992 cpu1-thermal {
1993 polling-delay-passive = <250>;
1995 thermal-sensors = <&tsens0 10>;
1998 cpu1_alert: trip-point0 {
2009 cooling-maps {
2012 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2016 cpu2-thermal {
2017 polling-delay-passive = <250>;
2019 thermal-sensors = <&tsens0 11>;
2022 cpu2_alert: trip-point0 {
2033 cooling-maps {
2036 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2040 cpu3-thermal {
2041 polling-delay-passive = <250>;
2043 thermal-sensors = <&tsens0 12>;
2046 cpu3_alert: trip-point0 {
2057 cooling-maps {
2060 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2064 cpu4-thermal {
2065 polling-delay-passive = <250>;
2066 thermal-sensors = <&tsens0 4>;
2068 cpu4_alert: trip-point0 {
2079 cooling-maps {
2082 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2086 cpu5-thermal {
2087 polling-delay-passive = <250>;
2088 thermal-sensors = <&tsens0 5>;
2090 cpu5_alert: trip-point0 {
2101 cooling-maps {
2104 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2108 cpu6-thermal {
2109 polling-delay-passive = <250>;
2110 thermal-sensors = <&tsens0 6>;
2112 cpu6_alert: trip-point0 {
2123 cooling-maps {
2126 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2130 cpu7-thermal {
2131 polling-delay-passive = <250>;
2132 thermal-sensors = <&tsens0 7>;
2134 cpu7_alert: trip-point0 {
2145 cooling-maps {
2148 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2153 gpu-thermal {
2154 polling-delay-passive = <250>;
2155 thermal-sensors = <&tsens0 15>;
2158 gpu_alert: trip-point0 {
2171 cooling-maps {
2174 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2181 compatible = "arm,armv8-timer";