Lines Matching +full:smp2p +full:- +full:mpss
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8939.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
14 #include <dt-bindings/soc/qcom,apr.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
21 * Stock LK wants address-cells/size-cells = 2
23 * hence the disparity between top-level and /soc below.
25 #address-cells = <2>;
26 #size-cells = <2>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <19200000>;
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
43 #address-cells = <1>;
44 #size-cells = <0>;
47 compatible = "arm,cortex-a53";
49 enable-method = "spin-table";
50 cpu-release-addr = /bits/ 64 <0>;
52 next-level-cache = <&l2_1>;
55 cpu-idle-states = <&cpu_sleep_0>;
57 #cooling-cells = <2>;
58 l2_1: l2-cache {
60 cache-level = <2>;
61 cache-unified;
66 compatible = "arm,cortex-a53";
68 enable-method = "spin-table";
69 cpu-release-addr = /bits/ 64 <0>;
71 next-level-cache = <&l2_1>;
74 cpu-idle-states = <&cpu_sleep_0>;
76 #cooling-cells = <2>;
80 compatible = "arm,cortex-a53";
82 enable-method = "spin-table";
83 cpu-release-addr = /bits/ 64 <0>;
85 next-level-cache = <&l2_1>;
88 cpu-idle-states = <&cpu_sleep_0>;
90 #cooling-cells = <2>;
94 compatible = "arm,cortex-a53";
96 enable-method = "spin-table";
97 cpu-release-addr = /bits/ 64 <0>;
99 next-level-cache = <&l2_1>;
102 cpu-idle-states = <&cpu_sleep_0>;
104 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 enable-method = "spin-table";
111 cpu-release-addr = /bits/ 64 <0>;
115 cpu-idle-states = <&cpu_sleep_0>;
117 #cooling-cells = <2>;
118 next-level-cache = <&l2_0>;
119 l2_0: l2-cache {
121 cache-level = <2>;
122 cache-unified;
127 compatible = "arm,cortex-a53";
129 enable-method = "spin-table";
130 cpu-release-addr = /bits/ 64 <0>;
132 next-level-cache = <&l2_0>;
135 cpu-idle-states = <&cpu_sleep_0>;
137 #cooling-cells = <2>;
141 compatible = "arm,cortex-a53";
143 enable-method = "spin-table";
144 cpu-release-addr = /bits/ 64 <0>;
146 next-level-cache = <&l2_0>;
149 cpu-idle-states = <&cpu_sleep_0>;
151 #cooling-cells = <2>;
155 compatible = "arm,cortex-a53";
157 enable-method = "spin-table";
158 cpu-release-addr = /bits/ 64 <0>;
160 next-level-cache = <&l2_0>;
163 cpu-idle-states = <&cpu_sleep_0>;
165 #cooling-cells = <2>;
168 idle-states {
169 cpu_sleep_0: cpu-sleep-0 {
170 compatible = "arm,idle-state";
171 entry-latency-us = <130>;
172 exit-latency-us = <150>;
173 min-residency-us = <2000>;
174 local-timer-stop;
181 * consisting of two clusters of four ARM Cortex-A53s each. The
182 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
183 * at 1.5-1.7GHz.
185 * The enable method used here is spin-table which presupposes use
187 * spin-table, the downstream non-psci/non-spin-table method that
190 cpu-map {
233 compatible = "qcom,scm-msm8916", "qcom,scm";
237 clock-names = "core", "bus", "iface";
238 #reset-cells = <1>;
240 qcom,dload-mode = <&tcsr 0x6100>;
251 compatible = "arm,cortex-a53-pmu";
256 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
258 smd-edge {
261 qcom,smd-edge = <15>;
263 rpm_requests: rpm-requests {
264 compatible = "qcom,rpm-msm8936", "qcom,smd-rpm";
265 qcom,smd-channels = "rpm_requests";
267 rpmcc: clock-controller {
268 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
269 #clock-cells = <1>;
270 clock-names = "xo";
274 rpmpd: power-controller {
275 compatible = "qcom,msm8939-rpmpd";
276 #power-domain-cells = <1>;
277 operating-points-v2 = <&rpmpd_opp_table>;
279 rpmpd_opp_table: opp-table {
280 compatible = "operating-points-v2";
283 opp-level = <1>;
287 opp-level = <2>;
291 opp-level = <3>;
295 opp-level = <4>;
299 opp-level = <5>;
303 opp-level = <6>;
311 reserved-memory {
312 #address-cells = <2>;
313 #size-cells = <2>;
316 tz-apps@86000000 {
318 no-map;
324 no-map;
327 qcom,rpm-msg-ram = <&rpm_msg_ram>;
332 no-map;
337 no-map;
342 no-map;
346 compatible = "qcom,rmtfs-mem";
348 no-map;
350 qcom,client-id = <1>;
355 no-map;
358 mpss_mem: mpss@86800000 {
360 * The memory region for the mpss firmware is generally
364 * define reliable alloc-ranges.
367 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
369 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
370 no-map;
377 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
378 no-map;
385 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
386 no-map;
393 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
394 no-map;
399 smp2p-hexagon {
400 compatible = "qcom,smp2p";
407 qcom,local-pid = <0>;
408 qcom,remote-pid = <1>;
410 hexagon_smp2p_out: master-kernel {
411 qcom,entry-name = "master-kernel";
413 #qcom,smem-state-cells = <1>;
416 hexagon_smp2p_in: slave-kernel {
417 qcom,entry-name = "slave-kernel";
419 interrupt-controller;
420 #interrupt-cells = <2>;
424 smp2p-wcnss {
425 compatible = "qcom,smp2p";
432 qcom,local-pid = <0>;
433 qcom,remote-pid = <4>;
435 wcnss_smp2p_in: slave-kernel {
436 qcom,entry-name = "slave-kernel";
438 interrupt-controller;
439 #interrupt-cells = <2>;
442 wcnss_smp2p_out: master-kernel {
443 qcom,entry-name = "master-kernel";
445 #qcom,smem-state-cells = <1>;
452 #address-cells = <1>;
453 #size-cells = <0>;
460 #qcom,smem-state-cells = <1>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
481 compatible = "simple-bus";
482 #address-cells = <1>;
483 #size-cells = <1>;
490 clock-names = "core";
494 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
496 #address-cells = <1>;
497 #size-cells = <1>;
504 tsens_s6_p1: s6-p1@a1 {
509 tsens_s6_p2: s6-p2@a1 {
514 tsens_s7_p1: s7-p1@a2 {
519 tsens_s7_p2: s7-p2@a3 {
524 tsens_s8_p1: s8-p1@a4 {
529 tsens_s8_p2: s8-p2@a4 {
534 tsens_s9_p1: s9-p1@a5 {
539 tsens_s9_p2: s9-p2@a6 {
554 tsens_s0_p1: s0-p1@d0 {
559 tsens_s0_p2: s0-p1@d1 {
564 tsens_s1_p1: s1-p1@d1 {
569 tsens_s1_p2: s1-p2@d2 {
574 tsens_s2_p1: s2-p1@d3 {
579 tsens_s2_p2: s2-p2@d4 {
584 tsens_s3_p1: s3-p1@d4 {
589 tsens_s3_p2: s3-p2@d5 {
594 tsens_s5_p1: s5-p1@d6 {
599 tsens_s5_p2: s5-p2@d7 {
606 compatible = "qcom,rpm-msg-ram";
611 compatible = "qcom,msm8939-bimc";
613 #interconnect-cells = <1>;
616 tsens: thermal-sensor@4a9000 {
617 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
620 nvmem-cells = <&tsens_mode>,
631 nvmem-cell-names = "mode",
644 interrupt-names = "uplow";
645 #thermal-sensor-cells = <1>;
654 compatible = "qcom,msm8939-pcnoc";
656 #interconnect-cells = <1>;
660 compatible = "qcom,msm8939-snoc";
662 #interconnect-cells = <1>;
664 snoc_mm: interconnect-snoc {
665 compatible = "qcom,msm8939-snoc-mm";
666 #interconnect-cells = <1>;
671 compatible = "qcom,msm8916-pinctrl";
674 gpio-controller;
675 gpio-ranges = <&tlmm 0 0 122>;
676 #gpio-cells = <2>;
677 interrupt-controller;
678 #interrupt-cells = <2>;
680 blsp_i2c1_default: blsp-i2c1-default-state {
683 drive-strength = <2>;
684 bias-disable;
687 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
690 drive-strength = <2>;
691 bias-disable;
694 blsp_i2c2_default: blsp-i2c2-default-state {
697 drive-strength = <2>;
698 bias-disable;
701 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
704 drive-strength = <2>;
705 bias-disable;
708 blsp_i2c3_default: blsp-i2c3-default-state {
711 drive-strength = <2>;
712 bias-disable;
715 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
718 drive-strength = <2>;
719 bias-disable;
722 blsp_i2c4_default: blsp-i2c4-default-state {
725 drive-strength = <2>;
726 bias-disable;
729 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
732 drive-strength = <2>;
733 bias-disable;
736 blsp_i2c5_default: blsp-i2c5-default-state {
739 drive-strength = <2>;
740 bias-disable;
743 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
746 drive-strength = <2>;
747 bias-disable;
750 blsp_i2c6_default: blsp-i2c6-default-state {
753 drive-strength = <2>;
754 bias-disable;
757 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
760 drive-strength = <2>;
761 bias-disable;
764 blsp_spi1_default: blsp-spi1-default-state {
765 spi-pins {
768 drive-strength = <12>;
769 bias-disable;
772 cs-pins {
775 drive-strength = <16>;
776 bias-disable;
777 output-high;
781 blsp_spi1_sleep: blsp-spi1-sleep-state {
784 drive-strength = <2>;
785 bias-pull-down;
788 blsp_spi2_default: blsp-spi2-default-state {
789 spi-pins {
792 drive-strength = <12>;
793 bias-disable;
796 cs-pins {
799 drive-strength = <16>;
800 bias-disable;
801 output-high;
805 blsp_spi2_sleep: blsp-spi2-sleep-state {
808 drive-strength = <2>;
809 bias-pull-down;
812 blsp_spi3_default: blsp-spi3-default-state {
813 spi-pins {
816 drive-strength = <12>;
817 bias-disable;
820 cs-pins {
823 drive-strength = <16>;
824 bias-disable;
825 output-high;
829 blsp_spi3_sleep: blsp-spi3-sleep-state {
832 drive-strength = <2>;
833 bias-pull-down;
836 blsp_spi4_default: blsp-spi4-default-state {
837 spi-pins {
840 drive-strength = <12>;
841 bias-disable;
844 cs-pins {
847 drive-strength = <16>;
848 bias-disable;
849 output-high;
853 blsp_spi4_sleep: blsp-spi4-sleep-state {
856 drive-strength = <2>;
857 bias-pull-down;
860 blsp_spi5_default: blsp-spi5-default-state {
861 spi-pins {
864 drive-strength = <12>;
865 bias-disable;
868 cs-pins {
871 drive-strength = <16>;
872 bias-disable;
873 output-high;
877 blsp_spi5_sleep: blsp-spi5-sleep-state {
880 drive-strength = <2>;
881 bias-pull-down;
884 blsp_spi6_default: blsp-spi6-default-state {
885 spi-pins {
888 drive-strength = <12>;
889 bias-disable;
892 cs-pins {
895 drive-strength = <16>;
896 bias-disable;
897 output-high;
901 blsp_spi6_sleep: blsp-spi6-sleep-state {
904 drive-strength = <2>;
905 bias-pull-down;
908 blsp_uart1_console_default: blsp-uart1-console-default-state {
909 tx-pins {
912 drive-strength = <16>;
913 bias-disable;
914 bootph-all;
917 rx-pins {
920 drive-strength = <16>;
921 bias-pull-up;
922 bootph-all;
926 blsp_uart1_console_sleep: blsp-uart1-console-sleep-state {
929 drive-strength = <2>;
930 bias-pull-down;
933 blsp_uart2_console_default: blsp-uart2-console-default-state {
934 tx-pins {
937 drive-strength = <16>;
938 bias-disable;
939 bootph-all;
942 rx-pins {
945 drive-strength = <16>;
946 bias-pull-up;
947 bootph-all;
951 blsp_uart2_console_sleep: blsp-uart2-console-sleep-state {
954 drive-strength = <2>;
955 bias-pull-down;
958 camera_front_default: camera-front-default-state {
959 pwdn-pins {
962 drive-strength = <16>;
963 bias-disable;
966 rst-pins {
969 drive-strength = <16>;
970 bias-disable;
973 mclk1-pins {
976 drive-strength = <16>;
977 bias-disable;
981 camera_rear_default: camera-rear-default-state {
982 pwdn-pins {
985 drive-strength = <16>;
986 bias-disable;
989 rst-pins {
992 drive-strength = <16>;
993 bias-disable;
996 mclk0-pins {
999 drive-strength = <16>;
1000 bias-disable;
1004 cci0_default: cci0-default-state {
1007 drive-strength = <16>;
1008 bias-disable;
1011 cdc_dmic_default: cdc-dmic-default-state {
1012 clk-pins {
1015 drive-strength = <8>;
1018 data-pins {
1021 drive-strength = <8>;
1025 cdc_dmic_sleep: cdc-dmic-sleep-state {
1026 clk-pins {
1029 drive-strength = <2>;
1030 bias-disable;
1033 data-pins {
1036 drive-strength = <2>;
1037 bias-disable;
1041 cdc_pdm_default: cdc-pdm-default-state {
1045 drive-strength = <8>;
1046 bias-disable;
1049 cdc_pdm_sleep: cdc-pdm-sleep-state {
1053 drive-strength = <2>;
1054 bias-pull-down;
1057 pri_mi2s_default: mi2s-pri-default-state {
1060 drive-strength = <8>;
1061 bias-disable;
1064 pri_mi2s_sleep: mi2s-pri-sleep-state {
1067 drive-strength = <2>;
1068 bias-disable;
1071 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1074 drive-strength = <8>;
1075 bias-disable;
1078 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1081 drive-strength = <2>;
1082 bias-disable;
1085 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1088 drive-strength = <8>;
1089 bias-disable;
1092 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1095 drive-strength = <2>;
1096 bias-disable;
1099 sec_mi2s_default: mi2s-sec-default-state {
1102 drive-strength = <8>;
1103 bias-disable;
1106 sec_mi2s_sleep: mi2s-sec-sleep-state {
1109 drive-strength = <2>;
1110 bias-disable;
1113 sdc1_default: sdc1-default-state {
1114 clk-pins {
1116 bias-disable;
1117 drive-strength = <16>;
1120 cmd-pins {
1122 bias-pull-up;
1123 drive-strength = <10>;
1126 data-pins {
1128 bias-pull-up;
1129 drive-strength = <10>;
1133 sdc1_sleep: sdc1-sleep-state {
1134 clk-pins {
1136 bias-disable;
1137 drive-strength = <2>;
1140 cmd-pins {
1142 bias-pull-up;
1143 drive-strength = <2>;
1146 data-pins {
1148 bias-pull-up;
1149 drive-strength = <2>;
1153 sdc2_default: sdc2-default-state {
1154 clk-pins {
1156 bias-disable;
1157 drive-strength = <16>;
1160 cmd-pins {
1162 bias-pull-up;
1163 drive-strength = <10>;
1166 data-pins {
1168 bias-pull-up;
1169 drive-strength = <10>;
1173 sdc2_sleep: sdc2-sleep-state {
1174 clk-pins {
1176 bias-disable;
1177 drive-strength = <2>;
1180 cmd-pins {
1182 bias-pull-up;
1183 drive-strength = <2>;
1186 data-pins {
1188 bias-pull-up;
1189 drive-strength = <2>;
1193 wcss_wlan_default: wcss-wlan-default-state {
1196 drive-strength = <6>;
1197 bias-pull-up;
1201 gcc: clock-controller@1800000 {
1202 compatible = "qcom,gcc-msm8939";
1211 clock-names = "xo",
1218 #clock-cells = <1>;
1219 #reset-cells = <1>;
1220 #power-domain-cells = <1>;
1224 compatible = "qcom,tcsr-mutex";
1226 #hwlock-cells = <1>;
1230 compatible = "qcom,tcsr-msm8916", "syscon";
1234 mdss: display-subsystem@1a00000 {
1238 reg-names = "mdss_phys", "vbif_phys";
1241 interrupt-controller;
1246 clock-names = "iface",
1250 power-domains = <&gcc MDSS_GDSC>;
1252 #address-cells = <1>;
1253 #size-cells = <1>;
1254 #interrupt-cells = <1>;
1259 mdss_mdp: display-controller@1a01000 {
1262 reg-names = "mdp_phys";
1264 interrupt-parent = <&mdss>;
1271 clock-names = "iface",
1280 interconnect-names = "mdp0-mem", "mdp1-mem";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1289 remote-endpoint = <&mdss_dsi0_in>;
1296 remote-endpoint = <&mdss_dsi1_in>;
1303 compatible = "qcom,msm8916-dsi-ctrl",
1304 "qcom,mdss-dsi-ctrl";
1306 reg-names = "dsi_ctrl";
1308 interrupt-parent = <&mdss>;
1317 clock-names = "mdp_core",
1323 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1325 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1331 #address-cells = <1>;
1332 #size-cells = <0>;
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1341 remote-endpoint = <&mdss_mdp_intf1_out>;
1354 compatible = "qcom,dsi-phy-28nm-lp";
1358 reg-names = "dsi_pll",
1364 clock-names = "iface", "ref";
1366 #clock-cells = <1>;
1367 #phy-cells = <0>;
1372 compatible = "qcom,msm8916-dsi-ctrl",
1373 "qcom,mdss-dsi-ctrl";
1375 reg-names = "dsi_ctrl";
1377 interrupt-parent = <&mdss>;
1386 clock-names = "mdp_core",
1392 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1394 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1406 remote-endpoint = <&mdss_mdp_intf2_out>;
1419 compatible = "qcom,dsi-phy-28nm-lp";
1423 reg-names = "dsi_pll",
1429 clock-names = "iface", "ref";
1431 #clock-cells = <1>;
1432 #phy-cells = <0>;
1438 compatible = "qcom,adreno-405.0", "qcom,adreno";
1440 reg-names = "kgsl_3d0_reg_memory";
1442 interrupt-names = "kgsl_3d0_irq";
1443 clock-names = "core",
1457 power-domains = <&gcc OXILI_GDSC>;
1458 operating-points-v2 = <&opp_table>;
1460 #cooling-cells = <2>;
1464 opp_table: opp-table {
1465 compatible = "operating-points-v2";
1467 opp-550000000 {
1468 opp-hz = /bits/ 64 <550000000>;
1471 opp-465000000 {
1472 opp-hz = /bits/ 64 <465000000>;
1475 opp-400000000 {
1476 opp-hz = /bits/ 64 <400000000>;
1479 opp-220000000 {
1480 opp-hz = /bits/ 64 <220000000>;
1483 opp-19200000 {
1484 opp-hz = /bits/ 64 <19200000>;
1490 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1495 clock-names = "iface", "bus";
1496 #address-cells = <1>;
1497 #size-cells = <1>;
1498 #iommu-cells = <1>;
1499 qcom,iommu-secure-id = <17>;
1502 iommu-ctx@4000 {
1503 compatible = "qcom,msm-iommu-v1-ns";
1509 iommu-ctx@5000 {
1510 compatible = "qcom,msm-iommu-v1-sec";
1517 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1522 clock-names = "iface", "bus", "tbu";
1523 #address-cells = <1>;
1524 #size-cells = <1>;
1525 #iommu-cells = <1>;
1526 qcom,iommu-secure-id = <18>;
1529 iommu-ctx@1000 {
1530 compatible = "qcom,msm-iommu-v1-ns";
1536 iommu-ctx@2000 {
1537 compatible = "qcom,msm-iommu-v1-ns";
1544 compatible = "qcom,spmi-pmic-arb";
1550 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1551 interrupt-names = "periph_irq";
1555 #address-cells = <2>;
1556 #size-cells = <0>;
1557 interrupt-controller;
1558 #interrupt-cells = <4>;
1561 bam_dmux_dma: dma-controller@4044000 {
1562 compatible = "qcom,bam-v1.7.0";
1565 #dma-cells = <1>;
1568 num-channels = <6>;
1569 qcom,num-ees = <1>;
1570 qcom,powered-remotely;
1575 mpss: remoteproc@4080000 { label
1576 compatible = "qcom,msm8916-mss-pil";
1578 reg-names = "qdsp6", "rmb";
1579 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1584 interrupt-names = "wdog",
1588 "stop-ack";
1593 clock-names = "iface",
1597 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1599 power-domain-names = "cx", "mx";
1600 qcom,smem-states = <&hexagon_smp2p_out 0>;
1601 qcom,smem-state-names = "stop";
1603 reset-names = "mss_restart";
1604 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1607 bam_dmux: bam-dmux {
1608 compatible = "qcom,bam-dmux";
1610 interrupt-parent = <&hexagon_smsm>;
1612 interrupt-names = "pc", "pc-ack";
1614 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1615 qcom,smem-state-names = "pc", "pc-ack";
1618 dma-names = "tx", "rx";
1624 memory-region = <&mba_mem>;
1627 mpss {
1628 memory-region = <&mpss_mem>;
1631 smd-edge {
1634 qcom,smd-edge = <0>;
1636 qcom,remote-pid = <1>;
1641 compatible = "qcom,apr-v2";
1642 qcom,smd-channels = "apr_audio_svc";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1658 compatible = "qcom,q6afe-dais";
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1661 #sound-dai-cells = <1>;
1670 compatible = "qcom,q6asm-dais";
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1673 #sound-dai-cells = <1>;
1682 compatible = "qcom,q6adm-routing";
1683 #sound-dai-cells = <0>;
1691 compatible = "qcom,apq8016-sbc-sndcard";
1694 reg-names = "mic-iomux", "spkr-iomux";
1698 lpass: audio-controller@7708000 {
1699 compatible = "qcom,apq8016-lpass-cpu";
1701 reg-names = "lpass-lpaif";
1703 interrupt-names = "lpass-irq-lpaif";
1711 clock-names = "ahbix-clk",
1712 "mi2s-bit-clk0",
1713 "mi2s-bit-clk1",
1714 "mi2s-bit-clk2",
1715 "mi2s-bit-clk3",
1716 "pcnoc-mport-clk",
1717 "pcnoc-sway-clk";
1718 #sound-dai-cells = <1>;
1719 #address-cells = <1>;
1720 #size-cells = <0>;
1724 lpass_codec: audio-codec@771c000 {
1725 compatible = "qcom,msm8916-wcd-digital-codec";
1729 clock-names = "ahbix-clk", "mclk";
1730 #sound-dai-cells = <1>;
1735 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1737 reg-names = "hc", "core";
1741 interrupt-names = "hc_irq", "pwr_irq";
1745 clock-names = "iface", "core", "xo";
1747 pinctrl-0 = <&sdc1_default>;
1748 pinctrl-1 = <&sdc1_sleep>;
1749 pinctrl-names = "default", "sleep";
1750 mmc-ddr-1_8v;
1751 bus-width = <8>;
1752 non-removable;
1757 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1759 reg-names = "hc", "core";
1763 interrupt-names = "hc_irq", "pwr_irq";
1767 clock-names = "iface", "core", "xo";
1769 pinctrl-0 = <&sdc2_default>;
1770 pinctrl-1 = <&sdc2_sleep>;
1771 pinctrl-names = "default", "sleep";
1772 bus-width = <4>;
1776 blsp_dma: dma-controller@7884000 {
1777 compatible = "qcom,bam-v1.7.0";
1781 clock-names = "bam_clk";
1782 #dma-cells = <1>;
1784 qcom,controlled-remotely;
1788 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1792 clock-names = "core", "iface";
1794 dma-names = "tx", "rx";
1799 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1803 clock-names = "core", "iface";
1805 dma-names = "tx", "rx";
1810 compatible = "qcom,i2c-qup-v2.2.1";
1815 clock-names = "core", "iface";
1817 dma-names = "tx", "rx";
1818 pinctrl-0 = <&blsp_i2c1_default>;
1819 pinctrl-1 = <&blsp_i2c1_sleep>;
1820 pinctrl-names = "default", "sleep";
1821 #address-cells = <1>;
1822 #size-cells = <0>;
1827 compatible = "qcom,spi-qup-v2.2.1";
1832 clock-names = "core", "iface";
1834 dma-names = "tx", "rx";
1835 pinctrl-0 = <&blsp_spi1_default>;
1836 pinctrl-1 = <&blsp_spi1_sleep>;
1837 pinctrl-names = "default", "sleep";
1838 #address-cells = <1>;
1839 #size-cells = <0>;
1844 compatible = "qcom,i2c-qup-v2.2.1";
1849 clock-names = "core", "iface";
1851 dma-names = "tx", "rx";
1852 pinctrl-0 = <&blsp_i2c2_default>;
1853 pinctrl-1 = <&blsp_i2c2_sleep>;
1854 pinctrl-names = "default", "sleep";
1855 #address-cells = <1>;
1856 #size-cells = <0>;
1861 compatible = "qcom,spi-qup-v2.2.1";
1866 clock-names = "core", "iface";
1868 dma-names = "tx", "rx";
1869 pinctrl-0 = <&blsp_spi2_default>;
1870 pinctrl-1 = <&blsp_spi2_sleep>;
1871 pinctrl-names = "default", "sleep";
1872 #address-cells = <1>;
1873 #size-cells = <0>;
1878 compatible = "qcom,i2c-qup-v2.2.1";
1883 clock-names = "core", "iface";
1885 dma-names = "tx", "rx";
1886 pinctrl-0 = <&blsp_i2c3_default>;
1887 pinctrl-1 = <&blsp_i2c3_sleep>;
1888 pinctrl-names = "default", "sleep";
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1895 compatible = "qcom,spi-qup-v2.2.1";
1900 clock-names = "core", "iface";
1902 dma-names = "tx", "rx";
1903 pinctrl-0 = <&blsp_spi3_default>;
1904 pinctrl-1 = <&blsp_spi3_sleep>;
1905 pinctrl-names = "default", "sleep";
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1912 compatible = "qcom,i2c-qup-v2.2.1";
1917 clock-names = "core", "iface";
1919 dma-names = "tx", "rx";
1920 pinctrl-0 = <&blsp_i2c4_default>;
1921 pinctrl-1 = <&blsp_i2c4_sleep>;
1922 pinctrl-names = "default", "sleep";
1923 #address-cells = <1>;
1924 #size-cells = <0>;
1929 compatible = "qcom,spi-qup-v2.2.1";
1934 clock-names = "core", "iface";
1936 dma-names = "tx", "rx";
1937 pinctrl-0 = <&blsp_spi4_default>;
1938 pinctrl-1 = <&blsp_spi4_sleep>;
1939 pinctrl-names = "default", "sleep";
1940 #address-cells = <1>;
1941 #size-cells = <0>;
1946 compatible = "qcom,i2c-qup-v2.2.1";
1951 clock-names = "core", "iface";
1953 dma-names = "tx", "rx";
1954 pinctrl-0 = <&blsp_i2c5_default>;
1955 pinctrl-1 = <&blsp_i2c5_sleep>;
1956 pinctrl-names = "default", "sleep";
1957 #address-cells = <1>;
1958 #size-cells = <0>;
1963 compatible = "qcom,spi-qup-v2.2.1";
1968 clock-names = "core", "iface";
1970 dma-names = "tx", "rx";
1971 pinctrl-0 = <&blsp_spi5_default>;
1972 pinctrl-1 = <&blsp_spi5_sleep>;
1973 pinctrl-names = "default", "sleep";
1974 #address-cells = <1>;
1975 #size-cells = <0>;
1980 compatible = "qcom,i2c-qup-v2.2.1";
1985 clock-names = "core", "iface";
1987 dma-names = "tx", "rx";
1988 pinctrl-0 = <&blsp_i2c6_default>;
1989 pinctrl-1 = <&blsp_i2c6_sleep>;
1990 pinctrl-names = "default", "sleep";
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1997 compatible = "qcom,spi-qup-v2.2.1";
2002 clock-names = "core", "iface";
2004 dma-names = "tx", "rx";
2005 pinctrl-0 = <&blsp_spi6_default>;
2006 pinctrl-1 = <&blsp_spi6_sleep>;
2007 pinctrl-names = "default", "sleep";
2008 #address-cells = <1>;
2009 #size-cells = <0>;
2014 compatible = "qcom,ci-hdrc";
2021 clock-names = "iface", "core";
2022 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2023 assigned-clock-rates = <80000000>;
2025 reset-names = "core";
2026 #reset-cells = <1>;
2029 adp-disable;
2030 hnp-disable;
2031 srp-disable;
2032 ahb-burst-config = <0>;
2033 phy-names = "usb-phy";
2039 compatible = "qcom,usb-hs-phy-msm8916",
2040 "qcom,usb-hs-phy";
2043 clock-names = "ref", "sleep";
2045 reset-names = "phy", "por";
2046 #phy-cells = <0>;
2047 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2056 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2057 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2062 interrupt-names = "wdog",
2066 "stop-ack";
2070 reg-names = "ccu", "dxe", "pmu";
2072 memory-region = <&wcnss_mem>;
2074 power-domains = <&rpmpd MSM8939_VDDCX>,
2076 power-domain-names = "cx", "mx";
2078 qcom,smem-states = <&wcnss_smp2p_out 0>;
2079 qcom,smem-state-names = "stop";
2081 pinctrl-names = "default";
2082 pinctrl-0 = <&wcss_wlan_default>;
2087 /* Separate chip, compatible is board-specific */
2089 clock-names = "xo";
2092 smd-edge {
2095 qcom,smd-edge = <6>;
2096 qcom,remote-pid = <4>;
2102 qcom,smd-channels = "WCNSS_CTRL";
2107 compatible = "qcom,wcnss-bt";
2111 compatible = "qcom,wcnss-wlan";
2115 interrupt-names = "tx", "rx";
2117 qcom,smem-states = <&apps_smsm 10>,
2119 qcom,smem-state-names = "tx-enable",
2120 "tx-rings-empty";
2126 intc: interrupt-controller@b000000 {
2127 compatible = "qcom,msm-qgic2";
2130 interrupt-controller;
2131 #interrupt-cells = <3>;
2136 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2139 clock-names = "pll", "aux", "ref";
2140 #clock-cells = <0>;
2141 assigned-clocks = <&apcs2>;
2142 assigned-clock-rates = <297600000>;
2143 #mbox-cells = <1>;
2147 compatible = "qcom,msm8939-a53pll";
2149 #clock-cells = <0>;
2152 acc0: clock-controller@b088000 {
2153 compatible = "qcom,kpss-acc-v2";
2157 saw0: power-manager@b089000 {
2158 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2162 acc1: clock-controller@b098000 {
2163 compatible = "qcom,kpss-acc-v2";
2167 saw1: power-manager@b099000 {
2168 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2172 acc2: clock-controller@b0a8000 {
2173 compatible = "qcom,kpss-acc-v2";
2177 saw2: power-manager@b0a9000 {
2178 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2182 acc3: clock-controller@b0b8000 {
2183 compatible = "qcom,kpss-acc-v2";
2187 saw3: power-manager@b0b9000 {
2188 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2193 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2196 clock-names = "pll", "aux", "ref";
2197 #clock-cells = <0>;
2198 #mbox-cells = <1>;
2202 compatible = "qcom,msm8939-a53pll";
2204 #clock-cells = <0>;
2208 compatible = "arm,armv7-timer-mem";
2210 #address-cells = <1>;
2211 #size-cells = <1>;
2214 clock-frequency = <19200000>;
2221 frame-number = <0>;
2227 frame-number = <1>;
2234 frame-number = <2>;
2241 frame-number = <3>;
2248 frame-number = <4>;
2255 frame-number = <5>;
2262 frame-number = <6>;
2267 acc4: clock-controller@b188000 {
2268 compatible = "qcom,kpss-acc-v2";
2272 saw4: power-manager@b189000 {
2273 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2277 acc5: clock-controller@b198000 {
2278 compatible = "qcom,kpss-acc-v2";
2282 saw5: power-manager@b199000 {
2283 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2287 acc6: clock-controller@b1a8000 {
2288 compatible = "qcom,kpss-acc-v2";
2292 saw6: power-manager@b1a9000 {
2293 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2297 acc7: clock-controller@b1b8000 {
2298 compatible = "qcom,kpss-acc-v2";
2302 saw7: power-manager@b1b9000 {
2303 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2308 compatible = "qcom,msm8939-a53pll";
2310 #clock-cells = <0>;
2314 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2317 clock-names = "pll", "aux", "ref";
2318 #clock-cells = <0>;
2319 #mbox-cells = <1>;
2323 thermal_zones: thermal-zones {
2324 cpu0-thermal {
2325 polling-delay-passive = <250>;
2327 thermal-sensors = <&tsens 5>;
2343 cooling-maps {
2346 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2354 cpu1-thermal {
2355 polling-delay-passive = <250>;
2357 thermal-sensors = <&tsens 6>;
2373 cooling-maps {
2376 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2384 cpu2-thermal {
2385 polling-delay-passive = <250>;
2387 thermal-sensors = <&tsens 7>;
2403 cooling-maps {
2406 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2414 cpu3-thermal {
2415 polling-delay-passive = <250>;
2417 thermal-sensors = <&tsens 8>;
2433 cooling-maps {
2436 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2444 cpu4567-thermal {
2445 polling-delay-passive = <250>;
2447 thermal-sensors = <&tsens 9>;
2463 cooling-maps {
2466 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2474 gpu-thermal {
2475 polling-delay-passive = <250>;
2477 thermal-sensors = <&tsens 3>;
2479 cooling-maps {
2482 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2487 gpu_alert0: trip-point0 {
2493 gpu_crit: gpu-crit {
2501 modem1-thermal {
2502 polling-delay-passive = <250>;
2504 thermal-sensors = <&tsens 0>;
2507 modem1_alert0: trip-point0 {
2515 modem2-thermal {
2516 polling-delay-passive = <250>;
2518 thermal-sensors = <&tsens 2>;
2521 modem2_alert0: trip-point0 {
2529 camera-thermal {
2530 polling-delay-passive = <250>;
2532 thermal-sensors = <&tsens 1>;
2535 cam_alert0: trip-point0 {
2545 compatible = "arm,armv8-timer";