Lines Matching +full:q6afe +full:- +full:dais
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/soc/qcom,apr.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&intc>;
20 * Stock LK wants address-cells/size-cells = 2
22 * hence the disparity between top-level and /soc below.
24 #address-cells = <2>;
25 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <19200000>;
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32768>;
42 #address-cells = <1>;
43 #size-cells = <0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "spin-table";
50 next-level-cache = <&l2_1>;
53 cpu-idle-states = <&cpu_sleep_0>;
55 #cooling-cells = <2>;
56 l2_1: l2-cache {
58 cache-level = <2>;
59 cache-unified;
64 compatible = "arm,cortex-a53";
66 enable-method = "spin-table";
68 next-level-cache = <&l2_1>;
71 cpu-idle-states = <&cpu_sleep_0>;
73 #cooling-cells = <2>;
77 compatible = "arm,cortex-a53";
79 enable-method = "spin-table";
81 next-level-cache = <&l2_1>;
84 cpu-idle-states = <&cpu_sleep_0>;
86 #cooling-cells = <2>;
90 compatible = "arm,cortex-a53";
92 enable-method = "spin-table";
94 next-level-cache = <&l2_1>;
97 cpu-idle-states = <&cpu_sleep_0>;
99 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 enable-method = "spin-table";
109 cpu-idle-states = <&cpu_sleep_0>;
111 #cooling-cells = <2>;
112 next-level-cache = <&l2_0>;
113 l2_0: l2-cache {
115 cache-level = <2>;
116 cache-unified;
121 compatible = "arm,cortex-a53";
123 enable-method = "spin-table";
125 next-level-cache = <&l2_0>;
128 cpu-idle-states = <&cpu_sleep_0>;
130 #cooling-cells = <2>;
134 compatible = "arm,cortex-a53";
136 enable-method = "spin-table";
138 next-level-cache = <&l2_0>;
141 cpu-idle-states = <&cpu_sleep_0>;
143 #cooling-cells = <2>;
147 compatible = "arm,cortex-a53";
149 enable-method = "spin-table";
151 next-level-cache = <&l2_0>;
154 cpu-idle-states = <&cpu_sleep_0>;
156 #cooling-cells = <2>;
159 idle-states {
160 cpu_sleep_0: cpu-sleep-0 {
161 compatible = "arm,idle-state";
162 entry-latency-us = <130>;
163 exit-latency-us = <150>;
164 min-residency-us = <2000>;
165 local-timer-stop;
172 * consisting of two clusters of four ARM Cortex-A53s each. The
173 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
174 * at 1.5-1.7GHz.
176 * The enable method used here is spin-table which presupposes use
178 * spin-table, the downstream non-psci/non-spin-table method that
181 cpu-map {
224 compatible = "qcom,scm-msm8916", "qcom,scm";
228 clock-names = "core", "bus", "iface";
229 #reset-cells = <1>;
231 qcom,dload-mode = <&tcsr 0x6100>;
242 compatible = "arm,cortex-a53-pmu";
247 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
249 smd-edge {
252 qcom,smd-edge = <15>;
254 rpm_requests: rpm-requests {
255 compatible = "qcom,rpm-msm8936", "qcom,smd-rpm";
256 qcom,smd-channels = "rpm_requests";
258 rpmcc: clock-controller {
259 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
260 #clock-cells = <1>;
261 clock-names = "xo";
265 rpmpd: power-controller {
266 compatible = "qcom,msm8939-rpmpd";
267 #power-domain-cells = <1>;
268 operating-points-v2 = <&rpmpd_opp_table>;
270 rpmpd_opp_table: opp-table {
271 compatible = "operating-points-v2";
274 opp-level = <1>;
278 opp-level = <2>;
282 opp-level = <3>;
286 opp-level = <4>;
290 opp-level = <5>;
294 opp-level = <6>;
302 reserved-memory {
303 #address-cells = <2>;
304 #size-cells = <2>;
307 tz-apps@86000000 {
309 no-map;
315 no-map;
318 qcom,rpm-msg-ram = <&rpm_msg_ram>;
323 no-map;
328 no-map;
333 no-map;
337 compatible = "qcom,rmtfs-mem";
339 no-map;
341 qcom,client-id = <1>;
346 no-map;
355 * define reliable alloc-ranges.
358 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
360 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
361 no-map;
368 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
369 no-map;
376 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
377 no-map;
384 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
385 no-map;
390 smp2p-hexagon {
398 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>;
401 hexagon_smp2p_out: master-kernel {
402 qcom,entry-name = "master-kernel";
404 #qcom,smem-state-cells = <1>;
407 hexagon_smp2p_in: slave-kernel {
408 qcom,entry-name = "slave-kernel";
410 interrupt-controller;
411 #interrupt-cells = <2>;
415 smp2p-wcnss {
423 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>;
426 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "slave-kernel";
429 interrupt-controller;
430 #interrupt-cells = <2>;
433 wcnss_smp2p_out: master-kernel {
434 qcom,entry-name = "master-kernel";
436 #qcom,smem-state-cells = <1>;
443 #address-cells = <1>;
444 #size-cells = <0>;
451 #qcom,smem-state-cells = <1>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
472 compatible = "simple-bus";
473 #address-cells = <1>;
474 #size-cells = <1>;
481 clock-names = "core";
485 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
487 #address-cells = <1>;
488 #size-cells = <1>;
495 tsens_s6_p1: s6-p1@a1 {
500 tsens_s6_p2: s6-p2@a1 {
505 tsens_s7_p1: s7-p1@a2 {
510 tsens_s7_p2: s7-p2@a3 {
515 tsens_s8_p1: s8-p1@a4 {
520 tsens_s8_p2: s8-p2@a4 {
525 tsens_s9_p1: s9-p1@a5 {
530 tsens_s9_p2: s9-p2@a6 {
545 tsens_s0_p1: s0-p1@d0 {
550 tsens_s0_p2: s0-p1@d1 {
555 tsens_s1_p1: s1-p1@d1 {
560 tsens_s1_p2: s1-p2@d2 {
565 tsens_s2_p1: s2-p1@d3 {
570 tsens_s2_p2: s2-p2@d4 {
575 tsens_s3_p1: s3-p1@d4 {
580 tsens_s3_p2: s3-p2@d5 {
585 tsens_s5_p1: s5-p1@d6 {
590 tsens_s5_p2: s5-p2@d7 {
597 compatible = "qcom,rpm-msg-ram";
602 compatible = "qcom,msm8939-bimc";
604 #interconnect-cells = <1>;
607 tsens: thermal-sensor@4a9000 {
608 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
611 nvmem-cells = <&tsens_mode>,
622 nvmem-cell-names = "mode",
635 interrupt-names = "uplow";
636 #thermal-sensor-cells = <1>;
645 compatible = "qcom,msm8939-pcnoc";
647 #interconnect-cells = <1>;
651 compatible = "qcom,msm8939-snoc";
653 #interconnect-cells = <1>;
655 snoc_mm: interconnect-snoc {
656 compatible = "qcom,msm8939-snoc-mm";
657 #interconnect-cells = <1>;
662 compatible = "qcom,msm8916-pinctrl";
665 gpio-controller;
666 gpio-ranges = <&tlmm 0 0 122>;
667 #gpio-cells = <2>;
668 interrupt-controller;
669 #interrupt-cells = <2>;
671 blsp_i2c1_default: blsp-i2c1-default-state {
674 drive-strength = <2>;
675 bias-disable;
678 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
681 drive-strength = <2>;
682 bias-disable;
685 blsp_i2c2_default: blsp-i2c2-default-state {
688 drive-strength = <2>;
689 bias-disable;
692 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
695 drive-strength = <2>;
696 bias-disable;
699 blsp_i2c3_default: blsp-i2c3-default-state {
702 drive-strength = <2>;
703 bias-disable;
706 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
709 drive-strength = <2>;
710 bias-disable;
713 blsp_i2c4_default: blsp-i2c4-default-state {
716 drive-strength = <2>;
717 bias-disable;
720 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
723 drive-strength = <2>;
724 bias-disable;
727 blsp_i2c5_default: blsp-i2c5-default-state {
730 drive-strength = <2>;
731 bias-disable;
734 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
737 drive-strength = <2>;
738 bias-disable;
741 blsp_i2c6_default: blsp-i2c6-default-state {
744 drive-strength = <2>;
745 bias-disable;
748 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
751 drive-strength = <2>;
752 bias-disable;
755 blsp_spi1_default: blsp-spi1-default-state {
756 spi-pins {
759 drive-strength = <12>;
760 bias-disable;
763 cs-pins {
766 drive-strength = <16>;
767 bias-disable;
768 output-high;
772 blsp_spi1_sleep: blsp-spi1-sleep-state {
775 drive-strength = <2>;
776 bias-pull-down;
779 blsp_spi2_default: blsp-spi2-default-state {
780 spi-pins {
783 drive-strength = <12>;
784 bias-disable;
787 cs-pins {
790 drive-strength = <16>;
791 bias-disable;
792 output-high;
796 blsp_spi2_sleep: blsp-spi2-sleep-state {
799 drive-strength = <2>;
800 bias-pull-down;
803 blsp_spi3_default: blsp-spi3-default-state {
804 spi-pins {
807 drive-strength = <12>;
808 bias-disable;
811 cs-pins {
814 drive-strength = <16>;
815 bias-disable;
816 output-high;
820 blsp_spi3_sleep: blsp-spi3-sleep-state {
823 drive-strength = <2>;
824 bias-pull-down;
827 blsp_spi4_default: blsp-spi4-default-state {
828 spi-pins {
831 drive-strength = <12>;
832 bias-disable;
835 cs-pins {
838 drive-strength = <16>;
839 bias-disable;
840 output-high;
844 blsp_spi4_sleep: blsp-spi4-sleep-state {
847 drive-strength = <2>;
848 bias-pull-down;
851 blsp_spi5_default: blsp-spi5-default-state {
852 spi-pins {
855 drive-strength = <12>;
856 bias-disable;
859 cs-pins {
862 drive-strength = <16>;
863 bias-disable;
864 output-high;
868 blsp_spi5_sleep: blsp-spi5-sleep-state {
871 drive-strength = <2>;
872 bias-pull-down;
875 blsp_spi6_default: blsp-spi6-default-state {
876 spi-pins {
879 drive-strength = <12>;
880 bias-disable;
883 cs-pins {
886 drive-strength = <16>;
887 bias-disable;
888 output-high;
892 blsp_spi6_sleep: blsp-spi6-sleep-state {
895 drive-strength = <2>;
896 bias-pull-down;
899 blsp_uart1_default: blsp-uart1-default-state {
902 drive-strength = <16>;
903 bias-disable;
906 blsp_uart1_sleep: blsp-uart1-sleep-state {
909 drive-strength = <2>;
910 bias-pull-down;
913 blsp_uart2_default: blsp-uart2-default-state {
916 drive-strength = <16>;
917 bias-disable;
920 blsp_uart2_sleep: blsp-uart2-sleep-state {
923 drive-strength = <2>;
924 bias-pull-down;
927 camera_front_default: camera-front-default-state {
928 pwdn-pins {
931 drive-strength = <16>;
932 bias-disable;
935 rst-pins {
938 drive-strength = <16>;
939 bias-disable;
942 mclk1-pins {
945 drive-strength = <16>;
946 bias-disable;
950 camera_rear_default: camera-rear-default-state {
951 pwdn-pins {
954 drive-strength = <16>;
955 bias-disable;
958 rst-pins {
961 drive-strength = <16>;
962 bias-disable;
965 mclk0-pins {
968 drive-strength = <16>;
969 bias-disable;
973 cci0_default: cci0-default-state {
976 drive-strength = <16>;
977 bias-disable;
980 cdc_dmic_default: cdc-dmic-default-state {
981 clk-pins {
984 drive-strength = <8>;
987 data-pins {
990 drive-strength = <8>;
994 cdc_dmic_sleep: cdc-dmic-sleep-state {
995 clk-pins {
998 drive-strength = <2>;
999 bias-disable;
1002 data-pins {
1005 drive-strength = <2>;
1006 bias-disable;
1010 cdc_pdm_default: cdc-pdm-default-state {
1014 drive-strength = <8>;
1015 bias-disable;
1018 cdc_pdm_sleep: cdc-pdm-sleep-state {
1022 drive-strength = <2>;
1023 bias-pull-down;
1026 pri_mi2s_default: mi2s-pri-default-state {
1029 drive-strength = <8>;
1030 bias-disable;
1033 pri_mi2s_sleep: mi2s-pri-sleep-state {
1036 drive-strength = <2>;
1037 bias-disable;
1040 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1043 drive-strength = <8>;
1044 bias-disable;
1047 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1050 drive-strength = <2>;
1051 bias-disable;
1054 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1057 drive-strength = <8>;
1058 bias-disable;
1061 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1064 drive-strength = <2>;
1065 bias-disable;
1068 sec_mi2s_default: mi2s-sec-default-state {
1071 drive-strength = <8>;
1072 bias-disable;
1075 sec_mi2s_sleep: mi2s-sec-sleep-state {
1078 drive-strength = <2>;
1079 bias-disable;
1082 sdc1_default: sdc1-default-state {
1083 clk-pins {
1085 bias-disable;
1086 drive-strength = <16>;
1089 cmd-pins {
1091 bias-pull-up;
1092 drive-strength = <10>;
1095 data-pins {
1097 bias-pull-up;
1098 drive-strength = <10>;
1102 sdc1_sleep: sdc1-sleep-state {
1103 clk-pins {
1105 bias-disable;
1106 drive-strength = <2>;
1109 cmd-pins {
1111 bias-pull-up;
1112 drive-strength = <2>;
1115 data-pins {
1117 bias-pull-up;
1118 drive-strength = <2>;
1122 sdc2_default: sdc2-default-state {
1123 clk-pins {
1125 bias-disable;
1126 drive-strength = <16>;
1129 cmd-pins {
1131 bias-pull-up;
1132 drive-strength = <10>;
1135 data-pins {
1137 bias-pull-up;
1138 drive-strength = <10>;
1142 sdc2_sleep: sdc2-sleep-state {
1143 clk-pins {
1145 bias-disable;
1146 drive-strength = <2>;
1149 cmd-pins {
1151 bias-pull-up;
1152 drive-strength = <2>;
1155 data-pins {
1157 bias-pull-up;
1158 drive-strength = <2>;
1162 wcss_wlan_default: wcss-wlan-default-state {
1165 drive-strength = <6>;
1166 bias-pull-up;
1170 gcc: clock-controller@1800000 {
1171 compatible = "qcom,gcc-msm8939";
1180 clock-names = "xo",
1187 #clock-cells = <1>;
1188 #reset-cells = <1>;
1189 #power-domain-cells = <1>;
1193 compatible = "qcom,tcsr-mutex";
1195 #hwlock-cells = <1>;
1199 compatible = "qcom,tcsr-msm8916", "syscon";
1203 mdss: display-subsystem@1a00000 {
1207 reg-names = "mdss_phys", "vbif_phys";
1210 interrupt-controller;
1215 clock-names = "iface",
1219 power-domains = <&gcc MDSS_GDSC>;
1221 #address-cells = <1>;
1222 #size-cells = <1>;
1223 #interrupt-cells = <1>;
1228 mdss_mdp: display-controller@1a01000 {
1231 reg-names = "mdp_phys";
1233 interrupt-parent = <&mdss>;
1240 clock-names = "iface",
1249 interconnect-names = "mdp0-mem", "mdp1-mem";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1258 remote-endpoint = <&mdss_dsi0_in>;
1265 remote-endpoint = <&mdss_dsi1_in>;
1272 compatible = "qcom,msm8916-dsi-ctrl",
1273 "qcom,mdss-dsi-ctrl";
1275 reg-names = "dsi_ctrl";
1277 interrupt-parent = <&mdss>;
1286 clock-names = "mdp_core",
1292 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1294 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1310 remote-endpoint = <&mdss_mdp_intf1_out>;
1323 compatible = "qcom,dsi-phy-28nm-lp";
1327 reg-names = "dsi_pll",
1333 clock-names = "iface", "ref";
1335 #clock-cells = <1>;
1336 #phy-cells = <0>;
1341 compatible = "qcom,msm8916-dsi-ctrl",
1342 "qcom,mdss-dsi-ctrl";
1344 reg-names = "dsi_ctrl";
1346 interrupt-parent = <&mdss>;
1355 clock-names = "mdp_core",
1361 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1363 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1375 remote-endpoint = <&mdss_mdp_intf2_out>;
1388 compatible = "qcom,dsi-phy-28nm-lp";
1392 reg-names = "dsi_pll",
1398 clock-names = "iface", "ref";
1400 #clock-cells = <1>;
1401 #phy-cells = <0>;
1407 compatible = "qcom,adreno-405.0", "qcom,adreno";
1409 reg-names = "kgsl_3d0_reg_memory";
1411 interrupt-names = "kgsl_3d0_irq";
1412 clock-names = "core",
1426 power-domains = <&gcc OXILI_GDSC>;
1427 operating-points-v2 = <&opp_table>;
1429 #cooling-cells = <2>;
1433 opp_table: opp-table {
1434 compatible = "operating-points-v2";
1436 opp-550000000 {
1437 opp-hz = /bits/ 64 <550000000>;
1440 opp-465000000 {
1441 opp-hz = /bits/ 64 <465000000>;
1444 opp-400000000 {
1445 opp-hz = /bits/ 64 <400000000>;
1448 opp-220000000 {
1449 opp-hz = /bits/ 64 <220000000>;
1452 opp-19200000 {
1453 opp-hz = /bits/ 64 <19200000>;
1459 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1464 clock-names = "iface", "bus";
1465 #address-cells = <1>;
1466 #size-cells = <1>;
1467 #iommu-cells = <1>;
1468 qcom,iommu-secure-id = <17>;
1471 iommu-ctx@4000 {
1472 compatible = "qcom,msm-iommu-v1-ns";
1478 iommu-ctx@5000 {
1479 compatible = "qcom,msm-iommu-v1-sec";
1486 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1491 clock-names = "iface", "bus", "tbu";
1492 #address-cells = <1>;
1493 #size-cells = <1>;
1494 #iommu-cells = <1>;
1495 qcom,iommu-secure-id = <18>;
1498 iommu-ctx@1000 {
1499 compatible = "qcom,msm-iommu-v1-ns";
1505 iommu-ctx@2000 {
1506 compatible = "qcom,msm-iommu-v1-ns";
1513 compatible = "qcom,spmi-pmic-arb";
1519 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1520 interrupt-names = "periph_irq";
1524 #address-cells = <2>;
1525 #size-cells = <0>;
1526 interrupt-controller;
1527 #interrupt-cells = <4>;
1530 bam_dmux_dma: dma-controller@4044000 {
1531 compatible = "qcom,bam-v1.7.0";
1534 #dma-cells = <1>;
1537 num-channels = <6>;
1538 qcom,num-ees = <1>;
1539 qcom,powered-remotely;
1545 compatible = "qcom,msm8916-mss-pil";
1547 reg-names = "qdsp6", "rmb";
1548 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1553 interrupt-names = "wdog",
1557 "stop-ack";
1562 clock-names = "iface",
1566 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1568 power-domain-names = "cx", "mx";
1569 qcom,smem-states = <&hexagon_smp2p_out 0>;
1570 qcom,smem-state-names = "stop";
1572 reset-names = "mss_restart";
1573 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1576 bam_dmux: bam-dmux {
1577 compatible = "qcom,bam-dmux";
1579 interrupt-parent = <&hexagon_smsm>;
1581 interrupt-names = "pc", "pc-ack";
1583 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1584 qcom,smem-state-names = "pc", "pc-ack";
1587 dma-names = "tx", "rx";
1593 memory-region = <&mba_mem>;
1597 memory-region = <&mpss_mem>;
1600 smd-edge {
1603 qcom,smd-edge = <0>;
1605 qcom,remote-pid = <1>;
1610 compatible = "qcom,apr-v2";
1611 qcom,smd-channels = "apr_audio_svc";
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1622 q6afe: service@4 { label
1623 compatible = "qcom,q6afe";
1626 q6afedai: dais {
1627 compatible = "qcom,q6afe-dais";
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1630 #sound-dai-cells = <1>;
1638 q6asmdai: dais {
1639 compatible = "qcom,q6asm-dais";
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642 #sound-dai-cells = <1>;
1651 compatible = "qcom,q6adm-routing";
1652 #sound-dai-cells = <0>;
1660 compatible = "qcom,apq8016-sbc-sndcard";
1663 reg-names = "mic-iomux", "spkr-iomux";
1667 lpass: audio-controller@7708000 {
1668 compatible = "qcom,apq8016-lpass-cpu";
1670 reg-names = "lpass-lpaif";
1672 interrupt-names = "lpass-irq-lpaif";
1680 clock-names = "ahbix-clk",
1681 "mi2s-bit-clk0",
1682 "mi2s-bit-clk1",
1683 "mi2s-bit-clk2",
1684 "mi2s-bit-clk3",
1685 "pcnoc-mport-clk",
1686 "pcnoc-sway-clk";
1687 #sound-dai-cells = <1>;
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1693 lpass_codec: audio-codec@771c000 {
1694 compatible = "qcom,msm8916-wcd-digital-codec";
1698 clock-names = "ahbix-clk", "mclk";
1699 #sound-dai-cells = <1>;
1704 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1706 reg-names = "hc", "core";
1710 interrupt-names = "hc_irq", "pwr_irq";
1714 clock-names = "iface", "core", "xo";
1716 pinctrl-0 = <&sdc1_default>;
1717 pinctrl-1 = <&sdc1_sleep>;
1718 pinctrl-names = "default", "sleep";
1719 mmc-ddr-1_8v;
1720 bus-width = <8>;
1721 non-removable;
1726 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1728 reg-names = "hc", "core";
1732 interrupt-names = "hc_irq", "pwr_irq";
1736 clock-names = "iface", "core", "xo";
1738 pinctrl-0 = <&sdc2_default>;
1739 pinctrl-1 = <&sdc2_sleep>;
1740 pinctrl-names = "default", "sleep";
1741 bus-width = <4>;
1745 blsp_dma: dma-controller@7884000 {
1746 compatible = "qcom,bam-v1.7.0";
1750 clock-names = "bam_clk";
1751 #dma-cells = <1>;
1753 qcom,controlled-remotely;
1757 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1761 clock-names = "core", "iface";
1763 dma-names = "tx", "rx";
1764 pinctrl-0 = <&blsp_uart1_default>;
1765 pinctrl-1 = <&blsp_uart1_sleep>;
1766 pinctrl-names = "default", "sleep";
1771 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1775 clock-names = "core", "iface";
1777 dma-names = "tx", "rx";
1778 pinctrl-0 = <&blsp_uart2_default>;
1779 pinctrl-1 = <&blsp_uart2_sleep>;
1780 pinctrl-names = "default", "sleep";
1785 compatible = "qcom,i2c-qup-v2.2.1";
1790 clock-names = "core", "iface";
1792 dma-names = "tx", "rx";
1793 pinctrl-0 = <&blsp_i2c1_default>;
1794 pinctrl-1 = <&blsp_i2c1_sleep>;
1795 pinctrl-names = "default", "sleep";
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1802 compatible = "qcom,spi-qup-v2.2.1";
1807 clock-names = "core", "iface";
1809 dma-names = "tx", "rx";
1810 pinctrl-0 = <&blsp_spi1_default>;
1811 pinctrl-1 = <&blsp_spi1_sleep>;
1812 pinctrl-names = "default", "sleep";
1813 #address-cells = <1>;
1814 #size-cells = <0>;
1819 compatible = "qcom,i2c-qup-v2.2.1";
1824 clock-names = "core", "iface";
1826 dma-names = "tx", "rx";
1827 pinctrl-0 = <&blsp_i2c2_default>;
1828 pinctrl-1 = <&blsp_i2c2_sleep>;
1829 pinctrl-names = "default", "sleep";
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1836 compatible = "qcom,spi-qup-v2.2.1";
1841 clock-names = "core", "iface";
1843 dma-names = "tx", "rx";
1844 pinctrl-0 = <&blsp_spi2_default>;
1845 pinctrl-1 = <&blsp_spi2_sleep>;
1846 pinctrl-names = "default", "sleep";
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1853 compatible = "qcom,i2c-qup-v2.2.1";
1858 clock-names = "core", "iface";
1860 dma-names = "tx", "rx";
1861 pinctrl-0 = <&blsp_i2c3_default>;
1862 pinctrl-1 = <&blsp_i2c3_sleep>;
1863 pinctrl-names = "default", "sleep";
1864 #address-cells = <1>;
1865 #size-cells = <0>;
1870 compatible = "qcom,spi-qup-v2.2.1";
1875 clock-names = "core", "iface";
1877 dma-names = "tx", "rx";
1878 pinctrl-0 = <&blsp_spi3_default>;
1879 pinctrl-1 = <&blsp_spi3_sleep>;
1880 pinctrl-names = "default", "sleep";
1881 #address-cells = <1>;
1882 #size-cells = <0>;
1887 compatible = "qcom,i2c-qup-v2.2.1";
1892 clock-names = "core", "iface";
1894 dma-names = "tx", "rx";
1895 pinctrl-0 = <&blsp_i2c4_default>;
1896 pinctrl-1 = <&blsp_i2c4_sleep>;
1897 pinctrl-names = "default", "sleep";
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1904 compatible = "qcom,spi-qup-v2.2.1";
1909 clock-names = "core", "iface";
1911 dma-names = "tx", "rx";
1912 pinctrl-0 = <&blsp_spi4_default>;
1913 pinctrl-1 = <&blsp_spi4_sleep>;
1914 pinctrl-names = "default", "sleep";
1915 #address-cells = <1>;
1916 #size-cells = <0>;
1921 compatible = "qcom,i2c-qup-v2.2.1";
1926 clock-names = "core", "iface";
1928 dma-names = "tx", "rx";
1929 pinctrl-0 = <&blsp_i2c5_default>;
1930 pinctrl-1 = <&blsp_i2c5_sleep>;
1931 pinctrl-names = "default", "sleep";
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1938 compatible = "qcom,spi-qup-v2.2.1";
1943 clock-names = "core", "iface";
1945 dma-names = "tx", "rx";
1946 pinctrl-0 = <&blsp_spi5_default>;
1947 pinctrl-1 = <&blsp_spi5_sleep>;
1948 pinctrl-names = "default", "sleep";
1949 #address-cells = <1>;
1950 #size-cells = <0>;
1955 compatible = "qcom,i2c-qup-v2.2.1";
1960 clock-names = "core", "iface";
1962 dma-names = "tx", "rx";
1963 pinctrl-0 = <&blsp_i2c6_default>;
1964 pinctrl-1 = <&blsp_i2c6_sleep>;
1965 pinctrl-names = "default", "sleep";
1966 #address-cells = <1>;
1967 #size-cells = <0>;
1972 compatible = "qcom,spi-qup-v2.2.1";
1977 clock-names = "core", "iface";
1979 dma-names = "tx", "rx";
1980 pinctrl-0 = <&blsp_spi6_default>;
1981 pinctrl-1 = <&blsp_spi6_sleep>;
1982 pinctrl-names = "default", "sleep";
1983 #address-cells = <1>;
1984 #size-cells = <0>;
1989 compatible = "qcom,ci-hdrc";
1996 clock-names = "iface", "core";
1997 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1998 assigned-clock-rates = <80000000>;
2000 reset-names = "core";
2001 #reset-cells = <1>;
2004 adp-disable;
2005 hnp-disable;
2006 srp-disable;
2007 ahb-burst-config = <0>;
2008 phy-names = "usb-phy";
2014 compatible = "qcom,usb-hs-phy-msm8916",
2015 "qcom,usb-hs-phy";
2018 clock-names = "ref", "sleep";
2020 reset-names = "phy", "por";
2021 #phy-cells = <0>;
2022 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2031 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2032 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2037 interrupt-names = "wdog",
2041 "stop-ack";
2045 reg-names = "ccu", "dxe", "pmu";
2047 memory-region = <&wcnss_mem>;
2049 power-domains = <&rpmpd MSM8939_VDDCX>,
2051 power-domain-names = "cx", "mx";
2053 qcom,smem-states = <&wcnss_smp2p_out 0>;
2054 qcom,smem-state-names = "stop";
2056 pinctrl-names = "default";
2057 pinctrl-0 = <&wcss_wlan_default>;
2062 /* Separate chip, compatible is board-specific */
2064 clock-names = "xo";
2067 smd-edge {
2070 qcom,smd-edge = <6>;
2071 qcom,remote-pid = <4>;
2077 qcom,smd-channels = "WCNSS_CTRL";
2082 compatible = "qcom,wcnss-bt";
2086 compatible = "qcom,wcnss-wlan";
2090 interrupt-names = "tx", "rx";
2092 qcom,smem-states = <&apps_smsm 10>,
2094 qcom,smem-state-names = "tx-enable",
2095 "tx-rings-empty";
2101 intc: interrupt-controller@b000000 {
2102 compatible = "qcom,msm-qgic2";
2105 interrupt-controller;
2106 #interrupt-cells = <3>;
2111 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2114 clock-names = "pll", "aux", "ref";
2115 #clock-cells = <0>;
2116 assigned-clocks = <&apcs2>;
2117 assigned-clock-rates = <297600000>;
2118 #mbox-cells = <1>;
2122 compatible = "qcom,msm8939-a53pll";
2124 #clock-cells = <0>;
2127 acc0: clock-controller@b088000 {
2128 compatible = "qcom,kpss-acc-v2";
2132 saw0: power-manager@b089000 {
2133 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2137 acc1: clock-controller@b098000 {
2138 compatible = "qcom,kpss-acc-v2";
2142 saw1: power-manager@b099000 {
2143 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2147 acc2: clock-controller@b0a8000 {
2148 compatible = "qcom,kpss-acc-v2";
2152 saw2: power-manager@b0a9000 {
2153 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2157 acc3: clock-controller@b0b8000 {
2158 compatible = "qcom,kpss-acc-v2";
2162 saw3: power-manager@b0b9000 {
2163 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2168 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2171 clock-names = "pll", "aux", "ref";
2172 #clock-cells = <0>;
2173 #mbox-cells = <1>;
2177 compatible = "qcom,msm8939-a53pll";
2179 #clock-cells = <0>;
2183 compatible = "arm,armv7-timer-mem";
2185 #address-cells = <1>;
2186 #size-cells = <1>;
2189 clock-frequency = <19200000>;
2196 frame-number = <0>;
2202 frame-number = <1>;
2209 frame-number = <2>;
2216 frame-number = <3>;
2223 frame-number = <4>;
2230 frame-number = <5>;
2237 frame-number = <6>;
2242 acc4: clock-controller@b188000 {
2243 compatible = "qcom,kpss-acc-v2";
2247 saw4: power-manager@b189000 {
2248 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2252 acc5: clock-controller@b198000 {
2253 compatible = "qcom,kpss-acc-v2";
2257 saw5: power-manager@b199000 {
2258 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2262 acc6: clock-controller@b1a8000 {
2263 compatible = "qcom,kpss-acc-v2";
2267 saw6: power-manager@b1a9000 {
2268 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2272 acc7: clock-controller@b1b8000 {
2273 compatible = "qcom,kpss-acc-v2";
2277 saw7: power-manager@b1b9000 {
2278 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2283 compatible = "qcom,msm8939-a53pll";
2285 #clock-cells = <0>;
2289 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2292 clock-names = "pll", "aux", "ref";
2293 #clock-cells = <0>;
2294 #mbox-cells = <1>;
2298 thermal_zones: thermal-zones {
2299 cpu0-thermal {
2300 polling-delay-passive = <250>;
2302 thermal-sensors = <&tsens 5>;
2318 cooling-maps {
2321 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2329 cpu1-thermal {
2330 polling-delay-passive = <250>;
2332 thermal-sensors = <&tsens 6>;
2348 cooling-maps {
2351 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2359 cpu2-thermal {
2360 polling-delay-passive = <250>;
2362 thermal-sensors = <&tsens 7>;
2378 cooling-maps {
2381 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2389 cpu3-thermal {
2390 polling-delay-passive = <250>;
2392 thermal-sensors = <&tsens 8>;
2408 cooling-maps {
2411 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2419 cpu4567-thermal {
2420 polling-delay-passive = <250>;
2422 thermal-sensors = <&tsens 9>;
2438 cooling-maps {
2441 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2449 gpu-thermal {
2450 polling-delay-passive = <250>;
2452 thermal-sensors = <&tsens 3>;
2454 cooling-maps {
2457 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2462 gpu_alert0: trip-point0 {
2468 gpu_crit: gpu-crit {
2476 modem1-thermal {
2477 polling-delay-passive = <250>;
2479 thermal-sensors = <&tsens 0>;
2482 modem1_alert0: trip-point0 {
2490 modem2-thermal {
2491 polling-delay-passive = <250>;
2493 thermal-sensors = <&tsens 2>;
2496 modem2_alert0: trip-point0 {
2504 camera-thermal {
2505 polling-delay-passive = <250>;
2507 thermal-sensors = <&tsens 1>;
2510 cam_alert0: trip-point0 {
2520 compatible = "arm,armv8-timer";