Lines Matching +full:gcc +full:- +full:msm8917
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
25 sleep_clk: sleep-clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 operating-points-v2 = <&cpu_opp_table_c0>;
41 next-level-cache = <&l2_0>;
42 #cooling-cells = <2>;
44 l2_0: l2-cache {
46 cache-level = <2>;
47 cache-size = <0x80000>;
48 cache-unified;
53 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 operating-points-v2 = <&cpu_opp_table_c0>;
58 next-level-cache = <&l2_0>;
59 #cooling-cells = <2>;
63 compatible = "arm,cortex-a53";
66 enable-method = "psci";
67 operating-points-v2 = <&cpu_opp_table_c0>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
73 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 operating-points-v2 = <&cpu_opp_table_c0>;
78 next-level-cache = <&l2_0>;
79 #cooling-cells = <2>;
83 compatible = "arm,cortex-a53";
86 next-level-cache = <&l2_1>;
87 enable-method = "psci";
88 operating-points-v2 = <&cpu_opp_table_c1>;
89 #cooling-cells = <2>;
91 l2_1: l2-cache {
93 cache-level = <2>;
94 cache-size = <0x100000>;
95 cache-unified;
100 compatible = "arm,cortex-a53";
103 next-level-cache = <&l2_1>;
104 enable-method = "psci";
105 operating-points-v2 = <&cpu_opp_table_c1>;
106 #cooling-cells = <2>;
110 compatible = "arm,cortex-a53";
113 next-level-cache = <&l2_1>;
114 enable-method = "psci";
115 operating-points-v2 = <&cpu_opp_table_c1>;
116 #cooling-cells = <2>;
120 compatible = "arm,cortex-a53";
123 next-level-cache = <&l2_1>;
124 enable-method = "psci";
125 operating-points-v2 = <&cpu_opp_table_c1>;
126 #cooling-cells = <2>;
129 cpu-map {
172 compatible = "qcom,scm-msm8937", "qcom,scm";
173 clocks = <&gcc GCC_CRYPTO_CLK>,
174 <&gcc GCC_CRYPTO_AXI_CLK>,
175 <&gcc GCC_CRYPTO_AHB_CLK>;
176 clock-names = "core",
179 #reset-cells = <1>;
181 qcom,dload-mode = <&tcsr 0x6100>;
191 reserved-memory {
193 #address-cells = <2>;
194 #size-cells = <2>;
198 no-map;
204 no-map;
207 qcom,rpm-msg-ram = <&rpm_msg_ram>;
212 no-map;
216 compatible = "qcom,rmtfs-mem";
218 no-map;
220 qcom,client-id = <1>;
226 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
227 no-map;
234 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
235 no-map;
242 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
243 no-map;
250 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
251 no-map;
256 cpu_opp_table_c0: opp-table-c0 {
257 compatible = "operating-points-v2";
258 opp-shared;
260 opp-768000000 {
261 opp-hz = /bits/ 64 <768000000>;
264 opp-902400000 {
265 opp-hz = /bits/ 64 <902400000>;
268 opp-998400000 {
269 opp-hz = /bits/ 64 <998400000>;
272 opp-1094400000 {
273 opp-hz = /bits/ 64 <1094400000>;
277 cpu_opp_table_c1: opp-table-c1 {
278 compatible = "operating-points-v2";
279 opp-shared;
281 opp-960000000 {
282 opp-hz = /bits/ 64 <960000000>;
285 opp-1094400000 {
286 opp-hz = /bits/ 64 <1094400000>;
289 opp-1209600000 {
290 opp-hz = /bits/ 64 <1209600000>;
293 opp-1248000000 {
294 opp-hz = /bits/ 64 <1248000000>;
297 opp-1344000000 {
298 opp-hz = /bits/ 64 <1344000000>;
301 opp-1401600000 {
302 opp-hz = /bits/ 64 <1401600000>;
307 compatible = "arm,cortex-a53-pmu";
312 compatible = "arm,psci-1.0";
317 compatible = "qcom,msm8937-rpm-proc", "qcom,rpm-proc";
319 smd-edge {
322 qcom,smd-edge = <15>;
324 rpm_requests: rpm-requests {
325 compatible = "qcom,rpm-msm8937", "qcom,smd-rpm";
326 qcom,smd-channels = "rpm_requests";
328 rpmcc: clock-controller {
329 compatible = "qcom,rpmcc-msm8937", "qcom,rpmcc";
330 #clock-cells = <1>;
332 clock-names = "xo";
335 rpmpd: power-controller {
336 compatible = "qcom,msm8937-rpmpd", "qcom,msm8917-rpmpd";
337 #power-domain-cells = <1>;
338 operating-points-v2 = <&rpmpd_opp_table>;
340 rpmpd_opp_table: opp-table {
341 compatible = "operating-points-v2";
344 opp-level = <RPM_SMD_LEVEL_RETENTION>;
348 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
352 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
356 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
360 opp-level = <RPM_SMD_LEVEL_SVS>;
364 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
368 opp-level = <RPM_SMD_LEVEL_NOM>;
372 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
376 opp-level = <RPM_SMD_LEVEL_TURBO>;
384 smp2p-adsp {
392 qcom,local-pid = <0>;
393 qcom,remote-pid = <2>;
395 adsp_smp2p_out: master-kernel {
396 qcom,entry-name = "master-kernel";
398 #qcom,smem-state-cells = <1>;
401 adsp_smp2p_in: slave-kernel {
402 qcom,entry-name = "slave-kernel";
404 interrupt-controller;
405 #interrupt-cells = <2>;
409 smp2p-modem {
417 qcom,local-pid = <0>;
418 qcom,remote-pid = <1>;
420 modem_smp2p_out: master-kernel {
421 qcom,entry-name = "master-kernel";
423 #qcom,smem-state-cells = <1>;
426 modem_smp2p_in: slave-kernel {
427 qcom,entry-name = "slave-kernel";
429 interrupt-controller;
430 #interrupt-cells = <2>;
434 smp2p-wcnss {
442 qcom,local-pid = <0>;
443 qcom,remote-pid = <4>;
445 wcnss_smp2p_out: master-kernel {
446 qcom,entry-name = "master-kernel";
448 #qcom,smem-state-cells = <1>;
451 wcnss_smp2p_in: slave-kernel {
452 qcom,entry-name = "slave-kernel";
454 interrupt-controller;
455 #interrupt-cells = <2>;
462 #address-cells = <1>;
463 #size-cells = <0>;
470 #qcom,smem-state-cells = <1>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
491 compatible = "simple-bus";
493 #address-cells = <1>;
494 #size-cells = <1>;
497 compatible = "qcom,msm8937-qfprom", "qcom,qfprom";
499 #address-cells = <1>;
500 #size-cells = <1>;
507 tsens_s5_p1: s5-p1@1d9 {
512 tsens_s5_p2: s5-p2@1d9 {
517 tsens_s6_p1: s6-p1@1da {
522 tsens_s6_p2: s6-p2@1db {
527 tsens_s7_p1: s7-p1@1dc {
532 tsens_s7_p2: s7-p2@1dc {
537 tsens_s8_p1: s8-p1@1dd {
542 tsens_s8_p2: s8-p2@1de {
557 tsens_s0_p1: s0-p1@210 {
562 tsens_s0_p2: s0-p2@211 {
567 tsens_s1_p1: s1-p1@211 {
572 tsens_s1_p2: s1-p2@212 {
577 tsens_s2_p1: s2-p1@213 {
582 tsens_s2_p2: s2-p2@214 {
587 tsens_s3_p1: s3-p1@214 {
592 tsens_s3_p2: s3-p2@215 {
597 tsens_s4_p1: s4-p1@216 {
602 tsens_s4_p2: s4-p2@217 {
607 tsens_s9_p1: s9-p1@230 {
612 tsens_s9_p2: s9-p2@230 {
617 tsens_s10_p1: s10-p1@231 {
622 tsens_s10_p2: s10-p2@232 {
627 gpu_speed_bin: gpu-speed-bin@201b {
634 compatible = "qcom,rpm-msg-ram";
639 compatible = "qcom,usb-hs-28nm-femtophy";
641 #phy-cells = <0>;
643 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
644 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
645 clock-names = "ref",
648 resets = <&gcc GCC_QUSB2_PHY_BCR>,
649 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
650 reset-names = "phy",
658 clocks = <&gcc GCC_PRNG_AHB_CLK>;
659 clock-names = "core";
662 tsens: thermal-sensor@4a9000 {
663 compatible = "qcom,msm8937-tsens", "qcom,tsens-v1";
667 interrupt-names = "uplow";
668 nvmem-cells = <&tsens_mode>,
681 nvmem-cell-names = "mode",
695 #thermal-sensor-cells = <1>;
704 compatible = "qcom,msm8917-pinctrl";
707 gpio-controller;
708 gpio-ranges = <&tlmm 0 0 134>;
709 #gpio-cells = <2>;
710 interrupt-controller;
711 #interrupt-cells = <2>;
713 blsp1_i2c2_default: blsp1-i2c2-default-state {
716 drive-strength = <2>;
717 bias-disable;
720 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
723 drive-strength = <2>;
724 bias-disable;
727 blsp1_i2c3_default: blsp1-i2c3-default-state {
730 drive-strength = <2>;
731 bias-disable;
734 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
737 drive-strength = <2>;
738 bias-disable;
741 blsp1_i2c4_default: blsp1-i2c4-default-state {
744 drive-strength = <2>;
745 bias-disable;
748 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
751 drive-strength = <2>;
752 bias-disable;
755 blsp2_i2c1_default: blsp2-i2c1-default-state {
758 drive-strength = <2>;
759 bias-disable;
762 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
765 drive-strength = <2>;
766 bias-disable;
769 blsp1_spi3_default: blsp1-spi3-default-state {
770 cs-pins {
773 drive-strength = <2>;
774 bias-disable;
777 spi-pins {
780 drive-strength = <12>;
781 bias-disable;
785 blsp1_spi3_sleep: blsp1-spi3-sleep-state {
786 cs-pins {
789 drive-strength = <2>;
790 bias-disable;
793 spi-pins {
796 drive-strength = <2>;
797 bias-pull-down;
801 blsp2_spi2_default: blsp2-spi2-default-state {
802 cs0-pins {
805 drive-strength = <16>;
806 bias-disable;
809 cs1-pins {
812 drive-strength = <16>;
813 bias-disable;
816 spi-pins {
819 drive-strength = <16>;
820 bias-disable;
824 blsp2_spi2_sleep: blsp2-spi2-sleep-state {
825 cs0-pins {
828 drive-strength = <2>;
829 bias-disable;
832 cs1-pins {
835 drive-strength = <2>;
836 bias-disable;
839 spi-pins {
842 drive-strength = <2>;
843 bias-pull-down;
847 blsp1_uart1_default: blsp1-uart1-default-state {
850 drive-strength = <2>;
851 bias-disable;
854 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
857 drive-strength = <2>;
858 bias-disable;
861 blsp1_uart2_default: blsp1-uart2-default-state {
864 drive-strength = <2>;
865 bias-disable;
868 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
871 drive-strength = <2>;
872 bias-pull-down;
875 sdc1_default: sdc1-default-state {
876 clk-pins {
878 drive-strength = <16>;
879 bias-disable;
882 cmd-pins {
884 drive-strength = <10>;
885 bias-pull-up;
888 data-pins {
890 drive-strength = <10>;
891 bias-pull-up;
894 rclk-pins {
896 bias-pull-down;
900 sdc1_sleep: sdc1-sleep-state {
901 clk-pins {
903 drive-strength = <2>;
904 bias-disable;
907 cmd-pins {
909 drive-strength = <2>;
910 bias-pull-up;
913 data-pins {
915 drive-strength = <2>;
916 bias-pull-up;
919 rclk-pins {
921 bias-pull-down;
925 sdc2_default: sdc2-default-state {
926 clk-pins {
928 drive-strength = <16>;
929 bias-disable;
932 sdc2_cmd_default: cmd-pins {
934 drive-strength = <16>;
935 bias-pull-up;
938 sdc2_data_default: data-pins {
940 drive-strength = <16>;
941 bias-pull-up;
945 sdc2_sleep: sdc2-sleep-state {
946 clk-pins {
948 drive-strength = <2>;
949 bias-disable;
952 cmd-pins {
954 drive-strength = <2>;
955 bias-pull-up;
958 data-pins {
960 drive-strength = <2>;
961 bias-pull-up;
965 wcnss_pin_a: wcnss-active-state {
966 wcss-wlan-pins {
969 drive-strength = <6>;
970 bias-pull-up;
974 wcss-wlan0-pins {
977 drive-strength = <6>;
978 bias-pull-up;
982 wcss-wlan1-pins {
985 drive-strength = <6>;
986 bias-pull-up;
990 wcss-wlan2-pins {
993 drive-strength = <6>;
994 bias-pull-up;
1000 gcc: clock-controller@1800000 { label
1001 compatible = "qcom,gcc-msm8937";
1003 #clock-cells = <1>;
1004 #reset-cells = <1>;
1005 #power-domain-cells = <1>;
1012 clock-names = "xo",
1021 compatible = "qcom,tcsr-mutex";
1023 #hwlock-cells = <1>;
1027 compatible = "qcom,tcsr-msm8937", "syscon";
1031 mdss: display-subsystem@1a00000 {
1035 reg-names = "mdss_phys",
1039 power-domains = <&gcc MDSS_GDSC>;
1041 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1042 <&gcc GCC_MDSS_AXI_CLK>,
1043 <&gcc GCC_MDSS_VSYNC_CLK>;
1044 clock-names = "iface",
1049 interrupt-controller;
1050 #interrupt-cells = <1>;
1052 #address-cells = <1>;
1053 #size-cells = <1>;
1057 mdp: display-controller@1a01000 {
1058 compatible = "qcom,msm8937-mdp5", "qcom,mdp5";
1060 reg-names = "mdp_phys";
1062 interrupt-parent = <&mdss>;
1065 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1066 <&gcc GCC_MDSS_AXI_CLK>,
1067 <&gcc GCC_MDSS_MDP_CLK>,
1068 <&gcc GCC_MDSS_VSYNC_CLK>;
1069 clock-names = "iface",
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1083 remote-endpoint = <&mdss_dsi0_in>;
1090 remote-endpoint = <&mdss_dsi1_in>;
1097 compatible = "qcom,mdss-dsi-ctrl";
1099 reg-names = "dsi_ctrl";
1101 interrupt-parent = <&mdss>;
1104 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1105 <&gcc PCLK0_CLK_SRC>;
1106 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1109 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1110 <&gcc GCC_MDSS_AHB_CLK>,
1111 <&gcc GCC_MDSS_AXI_CLK>,
1112 <&gcc GCC_MDSS_BYTE0_CLK>,
1113 <&gcc GCC_MDSS_PCLK0_CLK>,
1114 <&gcc GCC_MDSS_ESC0_CLK>;
1115 clock-names = "mdp_core",
1123 operating-points-v2 = <&mdss_dsi0_opp_table>;
1124 power-domains = <&rpmpd MSM8937_VDDCX>;
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1138 remote-endpoint = <&mdp5_intf1_out>;
1149 mdss_dsi0_opp_table: opp-table {
1150 compatible = "operating-points-v2";
1152 opp-125000000 {
1153 opp-hz = /bits/ 64 <125000000>;
1154 required-opps = <&rpmpd_opp_svs>;
1157 opp-187500000 {
1158 opp-hz = /bits/ 64 <187500000>;
1159 required-opps = <&rpmpd_opp_nom>;
1165 compatible = "qcom,dsi-phy-28nm-8937";
1169 reg-names = "dsi_pll",
1173 #clock-cells = <1>;
1174 #phy-cells = <0>;
1176 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1178 clock-names = "iface",
1185 compatible = "qcom,mdss-dsi-ctrl";
1187 reg-names = "dsi_ctrl";
1189 interrupt-parent = <&mdss>;
1192 assigned-clocks = <&gcc MSM8937_BYTE1_CLK_SRC>,
1193 <&gcc MSM8937_PCLK1_CLK_SRC>;
1194 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
1197 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1198 <&gcc GCC_MDSS_AHB_CLK>,
1199 <&gcc GCC_MDSS_AXI_CLK>,
1200 <&gcc MSM8937_GCC_MDSS_BYTE1_CLK>,
1201 <&gcc MSM8937_GCC_MDSS_PCLK1_CLK>,
1202 <&gcc MSM8937_GCC_MDSS_ESC1_CLK>;
1203 clock-names = "mdp_core",
1211 operating-points-v2 = <&mdss_dsi1_opp_table>;
1212 power-domains = <&rpmpd MSM8937_VDDCX>;
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1226 remote-endpoint = <&mdp5_intf2_out>;
1237 mdss_dsi1_opp_table: opp-table {
1238 compatible = "operating-points-v2";
1240 opp-125000000 {
1241 opp-hz = /bits/ 64 <125000000>;
1242 required-opps = <&rpmpd_opp_svs>;
1245 opp-187500000 {
1246 opp-hz = /bits/ 64 <187500000>;
1247 required-opps = <&rpmpd_opp_nom>;
1253 compatible = "qcom,dsi-phy-28nm-8937";
1257 reg-names = "dsi_pll",
1261 #clock-cells = <1>;
1262 #phy-cells = <0>;
1264 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1266 clock-names = "iface",
1274 compatible = "qcom,adreno-505.0", "qcom,adreno";
1276 reg-names = "kgsl_3d0_reg_memory";
1278 interrupt-names = "kgsl_3d0_irq";
1279 #cooling-cells = <2>;
1280 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1281 <&gcc GCC_OXILI_AHB_CLK>,
1282 <&gcc GCC_BIMC_GFX_CLK>,
1283 <&gcc GCC_BIMC_GPU_CLK>,
1284 <&gcc MSM8937_GCC_OXILI_TIMER_CLK>,
1285 <&gcc MSM8937_GCC_OXILI_AON_CLK>;
1286 clock-names = "core",
1292 operating-points-v2 = <&gpu_opp_table>;
1293 power-domains = <&gcc OXILI_GX_GDSC>;
1297 nvmem-cells = <&gpu_speed_bin>;
1298 nvmem-cell-names = "speed_bin";
1302 gpu_opp_table: opp-table {
1303 compatible = "operating-points-v2";
1305 opp-19200000 {
1306 opp-hz = /bits/ 64 <19200000>;
1307 opp-supported-hw = <0xff>;
1308 required-opps = <&rpmpd_opp_min_svs>;
1311 opp-216000000 {
1312 opp-hz = /bits/ 64 <216000000>;
1313 opp-supported-hw = <0xff>;
1314 required-opps = <&rpmpd_opp_svs>;
1317 opp-300000000 {
1318 opp-hz = /bits/ 64 <300000000>;
1319 opp-supported-hw = <0xff>;
1320 required-opps = <&rpmpd_opp_svs_plus>;
1323 opp-375000000 {
1324 opp-hz = /bits/ 64 <375000000>;
1325 opp-supported-hw = <0xff>;
1326 required-opps = <&rpmpd_opp_nom>;
1329 opp-400000000 {
1330 opp-hz = /bits/ 64 <400000000>;
1331 opp-supported-hw = <0xff>;
1332 required-opps = <&rpmpd_opp_nom_plus>;
1335 opp-450000000 {
1336 opp-hz = /bits/ 64 <450000000>;
1337 opp-supported-hw = <0xff>;
1338 required-opps = <&rpmpd_opp_turbo>;
1344 compatible = "qcom,msm8996-smmu-v2",
1345 "qcom,adreno-smmu",
1346 "qcom,smmu-v2";
1349 #global-interrupts = <1>;
1355 #iommu-cells = <1>;
1357 clocks = <&gcc GCC_BIMC_GFX_CLK>,
1358 <&gcc GCC_OXILI_AHB_CLK>;
1359 clock-names = "bus",
1362 power-domains = <&gcc MSM8937_OXILI_CX_GDSC>;
1366 compatible = "qcom,msm8937-iommu", "qcom,msm-iommu-v1";
1369 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1370 <&gcc GCC_APSS_TCU_CLK>;
1371 clock-names = "iface",
1374 qcom,iommu-secure-id = <17>;
1376 #address-cells = <1>;
1377 #iommu-cells = <1>;
1378 #size-cells = <1>;
1381 iommu-ctx@14000 {
1382 compatible = "qcom,msm-iommu-v1-ns";
1388 iommu-ctx@15000 {
1389 compatible = "qcom,msm-iommu-v1-ns";
1395 iommu-ctx@16000 {
1396 compatible = "qcom,msm-iommu-v1-ns";
1403 compatible = "qcom,spmi-pmic-arb";
1409 reg-names = "core",
1414 interrupt-names = "periph_irq";
1418 #address-cells = <2>;
1419 #size-cells = <0>;
1420 interrupt-controller;
1421 #interrupt-cells = <4>;
1424 bam_dmux_dma: dma-controller@4044000 {
1425 compatible = "qcom,bam-v1.7.0";
1428 #dma-cells = <1>;
1431 num-channels = <6>;
1432 qcom,num-ees = <1>;
1433 qcom,powered-remotely;
1439 compatible = "qcom,sdhci-msm-v4";
1442 reg-names = "hc",
1447 interrupt-names = "hc_irq",
1449 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1450 <&gcc GCC_SDCC1_APPS_CLK>,
1452 clock-names = "iface",
1455 pinctrl-0 = <&sdc1_default>;
1456 pinctrl-1 = <&sdc1_sleep>;
1457 pinctrl-names = "default",
1459 power-domains = <&rpmpd MSM8937_VDDCX>;
1460 mmc-hs200-1_8v;
1461 mmc-hs400-1_8v;
1462 mmc-ddr-1_8v;
1463 bus-width = <8>;
1464 non-removable;
1469 compatible = "qcom,sdhci-msm-v4";
1472 reg-names = "hc",
1477 interrupt-names = "hc_irq",
1479 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1480 <&gcc GCC_SDCC2_APPS_CLK>,
1482 clock-names = "iface",
1485 pinctrl-0 = <&sdc2_default>;
1486 pinctrl-1 = <&sdc2_sleep>;
1487 pinctrl-names = "default",
1489 power-domains = <&rpmpd MSM8937_VDDCX>;
1490 bus-width = <4>;
1494 blsp1_dma: dma-controller@7884000 {
1495 compatible = "qcom,bam-v1.7.0";
1498 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1499 clock-names = "bam_clk";
1500 qcom,controlled-remotely;
1501 #dma-cells = <1>;
1502 num-channels = <12>;
1503 qcom,num-ees = <4>;
1508 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1511 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1512 <&gcc GCC_BLSP1_AHB_CLK>;
1513 clock-names = "core",
1517 dma-names = "tx",
1519 pinctrl-0 = <&blsp1_uart2_default>;
1520 pinctrl-1 = <&blsp1_uart2_sleep>;
1521 pinctrl-names = "default",
1527 compatible = "qcom,i2c-qup-v2.2.1";
1530 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1531 <&gcc GCC_BLSP1_AHB_CLK>;
1532 clock-names = "core", "iface";
1535 dma-names = "tx",
1537 pinctrl-0 = <&blsp1_i2c2_default>;
1538 pinctrl-1 = <&blsp1_i2c2_sleep>;
1539 pinctrl-names = "default",
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1547 compatible = "qcom,i2c-qup-v2.2.1";
1550 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1551 <&gcc GCC_BLSP1_AHB_CLK>;
1552 clock-names = "core",
1556 dma-names = "tx",
1558 pinctrl-0 = <&blsp1_i2c3_default>;
1559 pinctrl-1 = <&blsp1_i2c3_sleep>;
1560 pinctrl-names = "default",
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1568 compatible = "qcom,spi-qup-v2.2.1";
1571 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1572 <&gcc GCC_BLSP1_AHB_CLK>;
1573 clock-names = "core",
1577 dma-names = "tx",
1579 pinctrl-0 = <&blsp1_spi3_default>;
1580 pinctrl-1 = <&blsp1_spi3_sleep>;
1581 pinctrl-names = "default",
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1589 compatible = "qcom,i2c-qup-v2.2.1";
1592 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1593 <&gcc GCC_BLSP1_AHB_CLK>;
1594 clock-names = "core",
1598 dma-names = "tx",
1600 pinctrl-0 = <&blsp1_i2c4_default>;
1601 pinctrl-1 = <&blsp1_i2c4_sleep>;
1602 pinctrl-names = "default",
1604 #address-cells = <1>;
1605 #size-cells = <0>;
1609 blsp2_dma: dma-controller@7ac4000 {
1610 compatible = "qcom,bam-v1.7.0";
1613 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1614 clock-names = "bam_clk";
1615 qcom,controlled-remotely;
1616 #dma-cells = <1>;
1617 num-channels = <10>;
1618 qcom,num-ees = <4>;
1623 compatible = "qcom,i2c-qup-v2.2.1";
1626 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1627 <&gcc GCC_BLSP2_AHB_CLK>;
1628 clock-names = "core",
1632 dma-names = "tx",
1634 pinctrl-0 = <&blsp2_i2c1_default>;
1635 pinctrl-1 = <&blsp2_i2c1_sleep>;
1636 pinctrl-names = "default",
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1644 compatible = "qcom,spi-qup-v2.2.1";
1647 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
1648 <&gcc GCC_BLSP2_AHB_CLK>;
1649 clock-names = "core",
1653 dma-names = "tx",
1655 pinctrl-0 = <&blsp2_spi2_default>;
1656 pinctrl-1 = <&blsp2_spi2_sleep>;
1657 pinctrl-names = "default",
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1665 compatible = "qcom,ci-hdrc";
1670 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1671 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1672 clock-names = "iface",
1674 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1675 assigned-clock-rates = <80000000>;
1676 resets = <&gcc GCC_USB_HS_BCR>;
1677 reset-names = "core";
1680 hnp-disable;
1681 srp-disable;
1682 adp-disable;
1683 ahb-burst-config = <0>;
1684 phy-names = "usb-phy";
1687 #reset-cells = <1>;
1691 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1695 reg-names = "ccu",
1699 memory-region = <&wcnss_mem>;
1701 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1706 interrupt-names = "wdog",
1710 "stop-ack";
1712 power-domains = <&rpmpd MSM8937_VDDCX>,
1714 power-domain-names = "cx",
1717 qcom,smem-states = <&wcnss_smp2p_out 0>;
1718 qcom,smem-state-names = "stop";
1720 pinctrl-0 = <&wcnss_pin_a>;
1721 pinctrl-names = "default";
1727 clock-names = "xo";
1730 smd-edge {
1734 qcom,smd-edge = <6>;
1735 qcom,remote-pid = <4>;
1741 qcom,smd-channels = "WCNSS_CTRL";
1746 compatible = "qcom,wcnss-bt";
1750 compatible = "qcom,wcnss-wlan";
1754 interrupt-names = "tx",
1757 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1758 qcom,smem-state-names = "tx-enable",
1759 "tx-rings-empty";
1765 intc: interrupt-controller@b000000 {
1766 compatible = "qcom,msm-qgic2";
1767 interrupt-controller;
1768 #interrupt-cells = <3>;
1774 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
1776 #mbox-cells = <1>;
1780 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1786 compatible = "arm,armv7-timer-mem";
1789 #address-cells = <1>;
1790 #size-cells = <1>;
1795 frame-number = <0>;
1802 frame-number = <1>;
1809 frame-number = <2>;
1816 frame-number = <3>;
1823 frame-number = <4>;
1830 frame-number = <5>;
1837 frame-number = <6>;
1844 thermal_zones: thermal-zones {
1845 aoss-thermal {
1846 thermal-sensors = <&tsens 0>;
1849 aoss_alert0: trip-point0 {
1857 mdm-core-thermal {
1858 thermal-sensors = <&tsens 1>;
1861 mdm_core_alert0: trip-point0 {
1869 q6-thermal {
1870 thermal-sensors = <&tsens 2>;
1873 q6_alert0: trip-point0 {
1881 camera-thermal {
1882 thermal-sensors = <&tsens 3>;
1885 camera_alert0: trip-point0 {
1893 cpuss1-thermal {
1894 thermal-sensors = <&tsens 4>;
1896 cooling-maps {
1899 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1907 cpuss1_alert0: trip-point0 {
1913 cpuss1_alert1: trip-point1 {
1919 cpuss1_crit: cpuss1-crit {
1927 cpu4-thermal {
1928 thermal-sensors = <&tsens 5>;
1930 cooling-maps {
1933 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1941 cpu4_alert0: trip-point0 {
1947 cpu4_alert1: trip-point1 {
1953 cpu4_crit: cpu-crit {
1961 cpu5-thermal {
1962 thermal-sensors = <&tsens 6>;
1964 cooling-maps {
1967 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1975 cpu5_alert0: trip-point0 {
1981 cpu5_alert1: trip-point1 {
1987 cpu5_crit: cpu-crit {
1995 cpu6-thermal {
1996 thermal-sensors = <&tsens 7>;
1998 cooling-maps {
2001 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2009 cpu6_alert0: trip-point0 {
2015 cpu6_alert1: trip-point1 {
2021 cpu6_crit: cpu-crit {
2029 cpu7-thermal {
2030 thermal-sensors = <&tsens 8>;
2032 cooling-maps {
2035 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2043 cpu7_alert0: trip-point0 {
2049 cpu7_alert1: trip-point1 {
2055 cpu7_crit: cpu-crit {
2063 cpuss0-thermal {
2064 thermal-sensors = <&tsens 9>;
2066 cooling-maps {
2069 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2077 cpuss0_alert0: trip-point0 {
2083 cpuss0_alert1: trip-point1 {
2089 cpuss0_crit: cpuss0-crit {
2097 gpu-thermal {
2098 polling-delay-passive = <250>;
2100 thermal-sensors = <&tsens 10>;
2102 cooling-maps {
2105 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2110 gpu_alert: trip-point0 {
2116 gpu_crit: gpu-crit {
2126 compatible = "arm,armv8-timer";