Lines Matching +full:opp +full:- +full:270000000
1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/thermal/thermal.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
38 next-level-cache = <&l2_0>;
39 enable-method = "psci";
41 operating-points-v2 = <&cpu_opp_table>;
42 #cooling-cells = <2>;
43 power-domains = <&cpu_pd0>;
44 power-domain-names = "psci";
46 l2_0: l2-cache {
48 cache-level = <2>;
49 cache-unified;
54 compatible = "arm,cortex-a53";
57 next-level-cache = <&l2_0>;
58 enable-method = "psci";
60 operating-points-v2 = <&cpu_opp_table>;
61 #cooling-cells = <2>;
62 power-domains = <&cpu_pd1>;
63 power-domain-names = "psci";
67 compatible = "arm,cortex-a53";
70 next-level-cache = <&l2_0>;
71 enable-method = "psci";
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>;
75 power-domains = <&cpu_pd2>;
76 power-domain-names = "psci";
80 compatible = "arm,cortex-a53";
83 next-level-cache = <&l2_0>;
84 enable-method = "psci";
86 operating-points-v2 = <&cpu_opp_table>;
87 #cooling-cells = <2>;
88 power-domains = <&cpu_pd3>;
89 power-domain-names = "psci";
92 cpu-map {
112 domain-idle-states {
113 cluster_sleep_0: cluster-sleep-0 {
114 compatible = "domain-idle-state";
115 arm,psci-suspend-param = <0x41000053>;
116 entry-latency-us = <700>;
117 exit-latency-us = <1000>;
118 min-residency-us = <6500>;
122 idle-states {
123 entry-method = "psci";
125 cpu_sleep_0: cpu-sleep-0 {
126 compatible = "arm,idle-state";
127 idle-state-name = "standalone-power-collapse";
128 arm,psci-suspend-param = <0x40000003>;
129 entry-latency-us = <125>;
130 exit-latency-us = <180>;
131 min-residency-us = <595>;
132 local-timer-stop;
136 cpu_opp_table: opp-table-cpu {
137 compatible = "operating-points-v2";
138 opp-shared;
140 opp-960000000 {
141 opp-hz = /bits/ 64 <960000000>;
144 opp-1094400000 {
145 opp-hz = /bits/ 64 <1094400000>;
148 opp-1248000000 {
149 opp-hz = /bits/ 64 <1248000000>;
152 opp-1401600000 {
153 opp-hz = /bits/ 64 <1401600000>;
160 compatible = "qcom,scm-msm8916", "qcom,scm";
164 clock-names = "core", "bus", "iface";
165 #reset-cells = <1>;
167 qcom,dload-mode = <&tcsr 0x6100>;
178 compatible = "arm,cortex-a53-pmu";
183 compatible = "arm,psci-1.0";
186 cluster_pd: power-domain-cluster {
187 #power-domain-cells = <0>;
188 domain-idle-states = <&cluster_sleep_0>;
191 cpu_pd0: power-domain-cpu0 {
192 #power-domain-cells = <0>;
193 power-domains = <&cluster_pd>;
194 domain-idle-states = <&cpu_sleep_0>;
197 cpu_pd1: power-domain-cpu1 {
198 #power-domain-cells = <0>;
199 power-domains = <&cluster_pd>;
200 domain-idle-states = <&cpu_sleep_0>;
203 cpu_pd2: power-domain-cpu2 {
204 #power-domain-cells = <0>;
205 power-domains = <&cluster_pd>;
206 domain-idle-states = <&cpu_sleep_0>;
209 cpu_pd3: power-domain-cpu3 {
210 #power-domain-cells = <0>;
211 power-domains = <&cluster_pd>;
212 domain-idle-states = <&cpu_sleep_0>;
217 compatible = "qcom,msm8917-rpm-proc", "qcom,rpm-proc";
219 smd-edge {
222 qcom,smd-edge = <15>;
224 rpm_requests: rpm-requests {
225 compatible = "qcom,rpm-msm8917", "qcom,smd-rpm";
226 qcom,smd-channels = "rpm_requests";
228 rpmcc: clock-controller {
229 compatible = "qcom,rpmcc-msm8917", "qcom,rpmcc";
230 #clock-cells = <1>;
232 clock-names = "xo";
235 rpmpd: power-controller {
236 compatible = "qcom,msm8917-rpmpd";
237 #power-domain-cells = <1>;
238 operating-points-v2 = <&rpmpd_opp_table>;
240 rpmpd_opp_table: opp-table {
241 compatible = "operating-points-v2";
244 opp-level = <RPM_SMD_LEVEL_RETENTION>;
248 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
252 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
256 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
260 opp-level = <RPM_SMD_LEVEL_SVS>;
264 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
268 opp-level = <RPM_SMD_LEVEL_NOM>;
272 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
276 opp-level = <RPM_SMD_LEVEL_TURBO>;
284 reserved-memory {
286 #address-cells = <2>;
287 #size-cells = <2>;
291 no-map;
297 no-map;
300 qcom,rpm-msg-ram = <&rpm_msg_ram>;
305 no-map;
309 compatible = "qcom,rmtfs-mem";
311 no-map;
313 qcom,client-id = <1>;
319 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
320 no-map;
327 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
328 no-map;
335 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
336 no-map;
343 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
344 no-map;
349 smp2p-adsp {
357 qcom,local-pid = <0>;
358 qcom,remote-pid = <2>;
360 adsp_smp2p_out: master-kernel {
361 qcom,entry-name = "master-kernel";
363 #qcom,smem-state-cells = <1>;
366 adsp_smp2p_in: slave-kernel {
367 qcom,entry-name = "slave-kernel";
369 interrupt-controller;
370 #interrupt-cells = <2>;
374 smp2p-modem {
382 qcom,local-pid = <0>;
383 qcom,remote-pid = <1>;
385 modem_smp2p_out: master-kernel {
386 qcom,entry-name = "master-kernel";
388 #qcom,smem-state-cells = <1>;
391 modem_smp2p_in: slave-kernel {
392 qcom,entry-name = "slave-kernel";
394 interrupt-controller;
395 #interrupt-cells = <2>;
399 smp2p-wcnss {
407 qcom,local-pid = <0>;
408 qcom,remote-pid = <4>;
410 wcnss_smp2p_out: master-kernel {
411 qcom,entry-name = "master-kernel";
413 #qcom,smem-state-cells = <1>;
416 wcnss_smp2p_in: slave-kernel {
417 qcom,entry-name = "slave-kernel";
419 interrupt-controller;
420 #interrupt-cells = <2>;
427 #address-cells = <1>;
428 #size-cells = <0>;
435 #qcom,smem-state-cells = <1>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
456 compatible = "simple-bus";
458 #address-cells = <1>;
459 #size-cells = <1>;
462 compatible = "qcom,rpm-msg-ram";
467 compatible = "qcom,usb-hs-28nm-femtophy";
469 #phy-cells = <0>;
473 clock-names = "ref", "ahb", "sleep";
476 reset-names = "phy", "por";
481 compatible = "qcom,msm8917-qfprom", "qcom,qfprom";
483 #address-cells = <1>;
484 #size-cells = <1>;
491 tsens_s5_p1: s5-p1@1d9 {
496 tsens_s5_p2: s5-p2@1d9 {
501 tsens_s6_p1: s6-p1@1da {
506 tsens_s6_p2: s6-p2@1db {
511 tsens_s7_p1: s7-p1@1dc {
516 tsens_s7_p2: s7-p2@1dc {
521 tsens_s8_p1: s8-p1@1dd {
526 tsens_s8_p2: s8-p2@1de {
541 tsens_s0_p1: s0-p1@210 {
546 tsens_s0_p2: s0-p2@211 {
551 tsens_s1_p1: s1-p1@211 {
556 tsens_s1_p2: s1-p2@212 {
561 tsens_s2_p1: s2-p1@213 {
566 tsens_s2_p2: s2-p2@214 {
571 tsens_s3_p1: s3-p1@214 {
576 tsens_s3_p2: s3-p2@215 {
581 tsens_s4_p1: s4-p1@216 {
586 tsens_s4_p2: s4-p2@217 {
591 tsens_s9_p1: s9-p1@230 {
596 tsens_s9_p2: s9-p2@230 {
601 tsens_s10_p1: s10-p1@231 {
606 tsens_s10_p2: s10-p2@232 {
616 clock-names = "core";
619 tsens: thermal-sensor@4a9000 {
620 compatible = "qcom,msm8937-tsens", "qcom,tsens-v1";
624 interrupt-names = "uplow";
625 nvmem-cells = <&tsens_mode>,
638 nvmem-cell-names = "mode",
652 #thermal-sensor-cells = <1>;
661 compatible = "qcom,msm8917-pinctrl";
664 gpio-controller;
665 gpio-ranges = <&tlmm 0 0 134>;
666 #gpio-cells = <2>;
667 interrupt-controller;
668 #interrupt-cells = <2>;
670 blsp1_i2c2_default: blsp1-i2c2-default-state {
673 drive-strength = <2>;
674 bias-disable;
677 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
680 drive-strength = <2>;
681 bias-disable;
684 blsp1_i2c3_default: blsp1-i2c3-default-state {
687 drive-strength = <2>;
688 bias-disable;
691 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
694 drive-strength = <2>;
695 bias-disable;
698 blsp1_i2c4_default: blsp1-i2c4-default-state {
701 drive-strength = <2>;
702 bias-disable;
705 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
708 drive-strength = <2>;
709 bias-disable;
712 blsp2_i2c1_default: blsp2-i2c1-default-state {
715 drive-strength = <2>;
716 bias-disable;
719 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
722 drive-strength = <2>;
723 bias-disable;
726 blsp1_spi3_default: blsp1-spi3-default-state {
727 cs-pins {
730 drive-strength = <2>;
731 bias-disable;
734 spi-pins {
737 drive-strength = <12>;
738 bias-disable;
742 blsp1_spi3_sleep: blsp1-spi3-sleep-state {
743 cs-pins {
746 drive-strength = <2>;
747 bias-disable;
750 spi-pins {
753 drive-strength = <2>;
754 bias-pull-down;
758 blsp2_spi2_default: blsp2-spi2-default-state {
759 cs0-pins {
762 drive-strength = <16>;
763 bias-disable;
766 cs1-pins {
769 drive-strength = <16>;
770 bias-disable;
773 spi-pins {
776 drive-strength = <16>;
777 bias-disable;
781 blsp2_spi2_sleep: blsp2-spi2-sleep-state {
782 cs0-pins {
785 drive-strength = <2>;
786 bias-disable;
789 cs1-pins {
792 drive-strength = <2>;
793 bias-disable;
796 spi-pins {
799 drive-strength = <2>;
800 bias-pull-down;
804 blsp1_uart1_default: blsp1-uart1-default-state {
807 drive-strength = <2>;
808 bias-disable;
811 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
814 drive-strength = <2>;
815 bias-disable;
818 blsp1_uart2_default: blsp1-uart2-default-state {
821 drive-strength = <2>;
822 bias-disable;
825 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
828 drive-strength = <2>;
829 bias-pull-down;
832 sdc1_default: sdc1-default-state {
833 clk-pins {
835 bias-disable;
836 drive-strength = <16>;
839 cmd-pins {
841 bias-pull-up;
842 drive-strength = <10>;
845 data-pins {
847 bias-pull-up;
848 drive-strength = <10>;
851 rclk-pins {
853 bias-pull-down;
857 sdc1_sleep: sdc1-sleep-state {
858 clk-pins {
860 bias-disable;
861 drive-strength = <2>;
864 cmd-pins {
866 bias-pull-up;
867 drive-strength = <2>;
870 data-pins {
872 bias-pull-up;
873 drive-strength = <2>;
876 rclk-pins {
878 bias-pull-down;
882 sdc2_default: sdc2-default-state {
883 clk-pins {
885 bias-disable;
886 drive-strength = <16>;
889 cmd-pins {
891 bias-pull-up;
892 drive-strength = <10>;
895 data-pins {
897 bias-pull-up;
898 drive-strength = <10>;
902 sdc2_sleep: sdc2-sleep-state {
903 clk-pins {
905 bias-disable;
906 drive-strength = <2>;
909 cmd-pins {
911 bias-pull-up;
912 drive-strength = <2>;
915 data-pins {
917 bias-pull-up;
918 drive-strength = <2>;
922 wcnss_pin_a: wcnss-active-state {
923 wcss-wlan-pins {
926 drive-strength = <6>;
927 bias-pull-up;
931 wcss-wlan0-pins {
934 drive-strength = <6>;
935 bias-pull-up;
939 wcss-wlan1-pins {
942 drive-strength = <6>;
943 bias-pull-up;
947 wcss-wlan2-pins {
950 drive-strength = <6>;
951 bias-pull-up;
957 gcc: clock-controller@1800000 {
958 compatible = "qcom,gcc-msm8917";
960 #clock-cells = <1>;
961 #reset-cells = <1>;
962 #power-domain-cells = <1>;
967 clock-names = "xo",
974 compatible = "qcom,tcsr-mutex";
976 #hwlock-cells = <1>;
980 compatible = "qcom,tcsr-msm8917", "syscon";
984 mdss: display-subsystem@1a00000 {
988 reg-names = "mdss_phys", "vbif_phys";
991 power-domains = <&gcc MDSS_GDSC>;
996 clock-names = "iface",
1002 interrupt-controller;
1003 #interrupt-cells = <1>;
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1010 mdp: display-controller@1a01000 {
1011 compatible = "qcom,msm8917-mdp5", "qcom,mdp5";
1013 reg-names = "mdp_phys";
1015 interrupt-parent = <&mdss>;
1018 power-domains = <&gcc MDSS_GDSC>;
1024 clock-names = "iface",
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1039 remote-endpoint = <&mdss_dsi0_in>;
1046 compatible = "qcom,mdss-dsi-ctrl";
1048 reg-names = "dsi_ctrl";
1050 interrupt-parent = <&mdss>;
1053 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1055 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1064 clock-names = "mdp_core",
1072 operating-points-v2 = <&mdss_dsi0_opp_table>;
1073 power-domains = <&rpmpd MSM8917_VDDCX>;
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1086 remote-endpoint = <&mdp5_intf1_out>;
1098 mdss_dsi0_opp_table: opp-table {
1099 compatible = "operating-points-v2";
1101 opp-125000000 {
1102 opp-hz = /bits/ 64 <125000000>;
1103 required-opps = <&rpmpd_opp_svs>;
1106 opp-187500000 {
1107 opp-hz = /bits/ 64 <187500000>;
1108 required-opps = <&rpmpd_opp_nom>;
1114 compatible = "qcom,dsi-phy-28nm-8937";
1118 reg-names = "dsi_pll",
1122 #clock-cells = <1>;
1123 #phy-cells = <0>;
1127 clock-names = "iface", "ref";
1132 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
1134 #address-cells = <1>;
1135 #size-cells = <1>;
1136 #iommu-cells = <1>;
1140 clock-names = "iface", "bus";
1142 qcom,iommu-secure-id = <17>;
1145 iommu-ctx@14000 {
1146 compatible = "qcom,msm-iommu-v1-ns";
1152 iommu-ctx@15000 {
1153 compatible = "qcom,msm-iommu-v1-ns";
1159 iommu-ctx@16000 {
1160 compatible = "qcom,msm-iommu-v1-ns";
1167 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
1170 #address-cells = <1>;
1171 #size-cells = <1>;
1172 #iommu-cells = <1>;
1176 clock-names = "iface", "bus";
1177 qcom,iommu-secure-id = <18>;
1179 iommu-ctx@0 {
1180 compatible = "qcom,msm-iommu-v2-ns";
1187 compatible = "qcom,adreno-306.32", "qcom,adreno";
1189 reg-names = "kgsl_3d0_reg_memory";
1191 interrupt-names = "kgsl_3d0_irq";
1192 clock-names = "core",
1202 power-domains = <&gcc OXILI_GX_GDSC>;
1203 operating-points-v2 = <&gpu_opp_table>;
1204 #cooling-cells = <2>;
1210 gpu_opp_table: opp-table {
1211 compatible = "operating-points-v2";
1213 opp-19200000 {
1214 opp-hz = /bits/ 64 <19200000>;
1217 opp-270000000 {
1218 opp-hz = /bits/ 64 <270000000>;
1221 opp-400000000 {
1222 opp-hz = /bits/ 64 <400000000>;
1225 opp-484800000 {
1226 opp-hz = /bits/ 64 <484800000>;
1229 opp-523200000 {
1230 opp-hz = /bits/ 64 <523200000>;
1233 opp-598000000 {
1234 opp-hz = /bits/ 64 <598000000>;
1240 compatible = "qcom,spmi-pmic-arb";
1246 reg-names = "core",
1251 interrupt-names = "periph_irq";
1255 #address-cells = <2>;
1256 #size-cells = <0>;
1257 interrupt-controller;
1258 #interrupt-cells = <4>;
1261 bam_dmux_dma: dma-controller@4044000 {
1262 compatible = "qcom,bam-v1.7.0";
1265 #dma-cells = <1>;
1268 num-channels = <6>;
1269 qcom,num-ees = <1>;
1270 qcom,powered-remotely;
1276 compatible = "qcom,sdhci-msm-v4";
1279 reg-names = "hc", "core";
1283 interrupt-names = "hc_irq", "pwr_irq";
1287 clock-names = "iface", "core", "xo";
1288 pinctrl-0 = <&sdc1_default>;
1289 pinctrl-1 = <&sdc1_sleep>;
1290 pinctrl-names = "default", "sleep";
1291 power-domains = <&rpmpd MSM8917_VDDCX>;
1292 mmc-hs200-1_8v;
1293 mmc-hs400-1_8v;
1294 mmc-ddr-1_8v;
1295 bus-width = <8>;
1296 non-removable;
1301 compatible = "qcom,sdhci-msm-v4";
1304 reg-names = "hc", "core";
1308 interrupt-names = "hc_irq", "pwr_irq";
1312 clock-names = "iface", "core", "xo";
1313 pinctrl-0 = <&sdc2_default>;
1314 pinctrl-1 = <&sdc2_sleep>;
1315 pinctrl-names = "default", "sleep";
1316 power-domains = <&rpmpd MSM8917_VDDCX>;
1317 bus-width = <4>;
1321 blsp1_dma: dma-controller@7884000 {
1322 compatible = "qcom,bam-v1.7.0";
1326 clock-names = "bam_clk";
1327 qcom,controlled-remotely;
1328 #dma-cells = <1>;
1329 num-channels = <12>;
1330 qcom,num-ees = <4>;
1334 blsp2_dma: dma-controller@7ac4000 {
1335 compatible = "qcom,bam-v1.7.0";
1339 clock-names = "bam_clk";
1340 qcom,controlled-remotely;
1341 #dma-cells = <1>;
1342 num-channels = <10>;
1343 qcom,num-ees = <4>;
1348 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1353 clock-names = "core", "iface";
1355 dma-names = "tx", "rx";
1356 pinctrl-0 = <&blsp1_uart1_default>;
1357 pinctrl-1 = <&blsp1_uart1_sleep>;
1358 pinctrl-names = "default", "sleep";
1363 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1368 clock-names = "core", "iface";
1370 dma-names = "tx", "rx";
1371 pinctrl-0 = <&blsp1_uart2_default>;
1372 pinctrl-1 = <&blsp1_uart2_sleep>;
1373 pinctrl-names = "default", "sleep";
1378 compatible = "qcom,i2c-qup-v2.2.1";
1383 clock-names = "core", "iface";
1385 dma-names = "tx", "rx";
1386 pinctrl-0 = <&blsp1_i2c2_default>;
1387 pinctrl-1 = <&blsp1_i2c2_sleep>;
1388 pinctrl-names = "default", "sleep";
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1395 compatible = "qcom,i2c-qup-v2.2.1";
1400 clock-names = "core", "iface";
1402 dma-names = "tx", "rx";
1403 pinctrl-0 = <&blsp1_i2c3_default>;
1404 pinctrl-1 = <&blsp1_i2c3_sleep>;
1405 pinctrl-names = "default", "sleep";
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1412 compatible = "qcom,spi-qup-v2.2.1";
1417 clock-names = "core", "iface";
1419 dma-names = "tx", "rx";
1420 pinctrl-0 = <&blsp1_spi3_default>;
1421 pinctrl-1 = <&blsp1_spi3_sleep>;
1422 pinctrl-names = "default", "sleep";
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1429 compatible = "qcom,i2c-qup-v2.2.1";
1434 clock-names = "core", "iface";
1436 dma-names = "tx", "rx";
1437 pinctrl-0 = <&blsp1_i2c4_default>;
1438 pinctrl-1 = <&blsp1_i2c4_sleep>;
1439 pinctrl-names = "default", "sleep";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1446 compatible = "qcom,i2c-qup-v2.2.1";
1451 clock-names = "core", "iface";
1453 dma-names = "tx", "rx";
1454 pinctrl-0 = <&blsp2_i2c1_default>;
1455 pinctrl-1 = <&blsp2_i2c1_sleep>;
1456 pinctrl-names = "default", "sleep";
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1463 compatible = "qcom,spi-qup-v2.2.1";
1468 clock-names = "core", "iface";
1470 dma-names = "tx", "rx";
1471 pinctrl-0 = <&blsp2_spi2_default>;
1472 pinctrl-1 = <&blsp2_spi2_sleep>;
1473 pinctrl-names = "default", "sleep";
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1480 compatible = "qcom,ci-hdrc";
1487 clock-names = "iface", "core";
1488 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1489 assigned-clock-rates = <80000000>;
1491 reset-names = "core";
1494 hnp-disable;
1495 srp-disable;
1496 adp-disable;
1497 ahb-burst-config = <0>;
1498 phy-names = "usb-phy";
1501 #reset-cells = <1>;
1505 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1509 reg-names = "ccu", "dxe", "pmu";
1511 memory-region = <&wcnss_mem>;
1513 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1518 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1520 power-domains = <&rpmpd MSM8917_VDDCX>,
1522 power-domain-names = "cx", "mx";
1524 qcom,smem-states = <&wcnss_smp2p_out 0>;
1525 qcom,smem-state-names = "stop";
1527 pinctrl-0 = <&wcnss_pin_a>;
1528 pinctrl-names = "default";
1534 clock-names = "xo";
1537 smd-edge {
1541 qcom,smd-edge = <6>;
1542 qcom,remote-pid = <4>;
1548 qcom,smd-channels = "WCNSS_CTRL";
1553 compatible = "qcom,wcnss-bt";
1557 compatible = "qcom,wcnss-wlan";
1561 interrupt-names = "tx", "rx";
1563 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1564 qcom,smem-state-names = "tx-enable",
1565 "tx-rings-empty";
1571 intc: interrupt-controller@b000000 {
1572 compatible = "qcom,msm-qgic2";
1575 interrupt-controller;
1576 #interrupt-cells = <3>;
1580 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
1582 #mbox-cells = <1>;
1584 clock-names = "pll", "aux", "ref";
1585 #clock-cells = <0>;
1589 compatible = "qcom,msm8939-a53pll";
1592 clock-names = "xo";
1593 #clock-cells = <0>;
1594 operating-points-v2 = <&pll_opp_table>;
1596 pll_opp_table: opp-table {
1597 compatible = "operating-points-v2";
1599 opp-960000000 {
1600 opp-hz = /bits/ 64 <960000000>;
1603 opp-1094400000 {
1604 opp-hz = /bits/ 64 <1094400000>;
1607 opp-1248000000 {
1608 opp-hz = /bits/ 64 <1248000000>;
1611 opp-1401600000 {
1612 opp-hz = /bits/ 64 <1401600000>;
1618 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1624 compatible = "arm,armv7-timer-mem";
1627 #address-cells = <1>;
1628 #size-cells = <1>;
1633 frame-number = <0>;
1640 frame-number = <1>;
1647 frame-number = <2>;
1654 frame-number = <3>;
1661 frame-number = <4>;
1668 frame-number = <5>;
1675 frame-number = <6>;
1683 compatible = "arm,armv8-timer";
1690 thermal_zones: thermal-zones {
1691 aoss-thermal {
1692 polling-delay-passive = <250>;
1694 thermal-sensors = <&tsens 0>;
1697 aoss_alert0: trip-point0 {
1705 camera-thermal {
1706 polling-delay-passive = <250>;
1708 thermal-sensors = <&tsens 3>;
1711 camera_alert0: trip-point0 {
1719 cpuss1-thermal {
1720 polling-delay-passive = <250>;
1722 thermal-sensors = <&tsens 4>;
1724 cooling-maps {
1727 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1735 cpuss1_alert0: trip-point0 {
1741 cpuss1_alert1: trip-point1 {
1747 cpuss1_crit: cpuss1-crit {
1755 cpu0-thermal {
1756 polling-delay-passive = <250>;
1758 thermal-sensors = <&tsens 5>;
1760 cooling-maps {
1763 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1771 cpu0_alert0: trip-point0 {
1777 cpu0_alert1: trip-point1 {
1783 cpu0_crit: cpu-crit {
1791 cpu1-thermal {
1792 polling-delay-passive = <250>;
1794 thermal-sensors = <&tsens 6>;
1796 cooling-maps {
1799 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1807 cpu1_alert0: trip-point0 {
1813 cpu1_alert1: trip-point1 {
1819 cpu1_crit: cpu-crit {
1827 cpu2-thermal {
1828 polling-delay-passive = <250>;
1830 thermal-sensors = <&tsens 7>;
1832 cooling-maps {
1835 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1843 cpu2_alert0: trip-point0 {
1849 cpu2_alert1: trip-point1 {
1855 cpu2_crit: cpu-crit {
1863 cpu3-thermal {
1864 polling-delay-passive = <250>;
1866 thermal-sensors = <&tsens 8>;
1868 cooling-maps {
1871 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1879 cpu3_alert0: trip-point0 {
1885 cpu3_alert1: trip-point1 {
1891 cpu3_crit: cpu-crit {
1899 gpu-thermal {
1900 polling-delay-passive = <250>;
1902 thermal-sensors = <&tsens 9>;
1904 cooling-maps {
1907 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1912 gpu_alert: trip-point0 {
1918 gpu_crit: gpu-crit {
1927 mdm-core-thermal {
1928 polling-delay-passive = <250>;
1930 thermal-sensors = <&tsens 1>;
1933 mdm_core_alert0: trip-point0 {
1941 q6-thermal {
1942 polling-delay-passive = <250>;
1944 thermal-sensors = <&tsens 2>;
1947 q6_alert0: trip-point0 {