Lines Matching +full:q6afe +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/soc/qcom,apr.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
35 tz-apps@86000000 {
37 no-map;
43 no-map;
46 qcom,rpm-msg-ram = <&rpm_msg_ram>;
51 no-map;
56 no-map;
61 no-map;
65 compatible = "qcom,rmtfs-mem";
67 no-map;
69 qcom,client-id = <1>;
74 no-map;
83 * define reliable alloc-ranges.
86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
88 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
89 no-map;
96 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
97 no-map;
104 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
105 no-map;
112 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
113 no-map;
118 clocks {
119 xo_board: xo-board {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <19200000>;
125 sleep_clk: sleep-clk {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <32768>;
133 #address-cells = <1>;
134 #size-cells = <0>;
138 compatible = "arm,cortex-a53";
140 next-level-cache = <&L2_0>;
141 enable-method = "psci";
142 clocks = <&apcs>;
143 operating-points-v2 = <&cpu_opp_table>;
144 #cooling-cells = <2>;
145 power-domains = <&CPU_PD0>;
146 power-domain-names = "psci";
153 compatible = "arm,cortex-a53";
155 next-level-cache = <&L2_0>;
156 enable-method = "psci";
157 clocks = <&apcs>;
158 operating-points-v2 = <&cpu_opp_table>;
159 #cooling-cells = <2>;
160 power-domains = <&CPU_PD1>;
161 power-domain-names = "psci";
168 compatible = "arm,cortex-a53";
170 next-level-cache = <&L2_0>;
171 enable-method = "psci";
172 clocks = <&apcs>;
173 operating-points-v2 = <&cpu_opp_table>;
174 #cooling-cells = <2>;
175 power-domains = <&CPU_PD2>;
176 power-domain-names = "psci";
183 compatible = "arm,cortex-a53";
185 next-level-cache = <&L2_0>;
186 enable-method = "psci";
187 clocks = <&apcs>;
188 operating-points-v2 = <&cpu_opp_table>;
189 #cooling-cells = <2>;
190 power-domains = <&CPU_PD3>;
191 power-domain-names = "psci";
196 L2_0: l2-cache {
198 cache-level = <2>;
199 cache-unified;
202 idle-states {
203 entry-method = "psci";
205 CPU_SLEEP_0: cpu-sleep-0 {
206 compatible = "arm,idle-state";
207 idle-state-name = "standalone-power-collapse";
208 arm,psci-suspend-param = <0x40000002>;
209 entry-latency-us = <130>;
210 exit-latency-us = <150>;
211 min-residency-us = <2000>;
212 local-timer-stop;
216 domain-idle-states {
218 CLUSTER_RET: cluster-retention {
219 compatible = "domain-idle-state";
220 arm,psci-suspend-param = <0x41000012>;
221 entry-latency-us = <500>;
222 exit-latency-us = <500>;
223 min-residency-us = <2000>;
226 CLUSTER_PWRDN: cluster-gdhs {
227 compatible = "domain-idle-state";
228 arm,psci-suspend-param = <0x41000032>;
229 entry-latency-us = <2000>;
230 exit-latency-us = <2000>;
231 min-residency-us = <6000>;
236 cpu_opp_table: opp-table-cpu {
237 compatible = "operating-points-v2";
238 opp-shared;
240 opp-200000000 {
241 opp-hz = /bits/ 64 <200000000>;
243 opp-400000000 {
244 opp-hz = /bits/ 64 <400000000>;
246 opp-800000000 {
247 opp-hz = /bits/ 64 <800000000>;
249 opp-998400000 {
250 opp-hz = /bits/ 64 <998400000>;
256 compatible = "qcom,scm-msm8916", "qcom,scm";
257 clocks = <&gcc GCC_CRYPTO_CLK>,
260 clock-names = "core", "bus", "iface";
261 #reset-cells = <1>;
263 qcom,dload-mode = <&tcsr 0x6100>;
268 compatible = "arm,cortex-a53-pmu";
273 compatible = "arm,psci-1.0";
276 CPU_PD0: power-domain-cpu0 {
277 #power-domain-cells = <0>;
278 power-domains = <&CLUSTER_PD>;
279 domain-idle-states = <&CPU_SLEEP_0>;
282 CPU_PD1: power-domain-cpu1 {
283 #power-domain-cells = <0>;
284 power-domains = <&CLUSTER_PD>;
285 domain-idle-states = <&CPU_SLEEP_0>;
288 CPU_PD2: power-domain-cpu2 {
289 #power-domain-cells = <0>;
290 power-domains = <&CLUSTER_PD>;
291 domain-idle-states = <&CPU_SLEEP_0>;
294 CPU_PD3: power-domain-cpu3 {
295 #power-domain-cells = <0>;
296 power-domains = <&CLUSTER_PD>;
297 domain-idle-states = <&CPU_SLEEP_0>;
300 CLUSTER_PD: power-domain-cluster {
301 #power-domain-cells = <0>;
302 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
307 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
309 smd-edge {
312 qcom,smd-edge = <15>;
314 rpm_requests: rpm-requests {
315 compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
316 qcom,smd-channels = "rpm_requests";
318 rpmcc: clock-controller {
319 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
320 #clock-cells = <1>;
321 clocks = <&xo_board>;
322 clock-names = "xo";
325 rpmpd: power-controller {
326 compatible = "qcom,msm8916-rpmpd";
327 #power-domain-cells = <1>;
328 operating-points-v2 = <&rpmpd_opp_table>;
330 rpmpd_opp_table: opp-table {
331 compatible = "operating-points-v2";
334 opp-level = <1>;
337 opp-level = <2>;
340 opp-level = <3>;
343 opp-level = <4>;
346 opp-level = <5>;
349 opp-level = <6>;
357 smp2p-hexagon {
365 qcom,local-pid = <0>;
366 qcom,remote-pid = <1>;
368 hexagon_smp2p_out: master-kernel {
369 qcom,entry-name = "master-kernel";
371 #qcom,smem-state-cells = <1>;
374 hexagon_smp2p_in: slave-kernel {
375 qcom,entry-name = "slave-kernel";
377 interrupt-controller;
378 #interrupt-cells = <2>;
382 smp2p-wcnss {
390 qcom,local-pid = <0>;
391 qcom,remote-pid = <4>;
393 wcnss_smp2p_out: master-kernel {
394 qcom,entry-name = "master-kernel";
396 #qcom,smem-state-cells = <1>;
399 wcnss_smp2p_in: slave-kernel {
400 qcom,entry-name = "slave-kernel";
402 interrupt-controller;
403 #interrupt-cells = <2>;
410 #address-cells = <1>;
411 #size-cells = <0>;
418 #qcom,smem-state-cells = <1>;
425 interrupt-controller;
426 #interrupt-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
439 #address-cells = <1>;
440 #size-cells = <1>;
442 compatible = "simple-bus";
447 clocks = <&gcc GCC_PRNG_AHB_CLK>;
448 clock-names = "core";
457 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
459 #address-cells = <1>;
460 #size-cells = <1>;
467 tsens_s0_p1: s0-p1@d0 {
472 tsens_s0_p2: s0-p2@d1 {
477 tsens_s1_p1: s1-p1@d2 {
481 tsens_s1_p2: s1-p2@d2 {
485 tsens_s2_p1: s2-p1@d3 {
490 tsens_s2_p2: s2-p2@d4 {
497 tsens_s4_p1: s4-p1@d4 {
502 tsens_s4_p2: s4-p2@d5 {
507 tsens_s5_p1: s5-p1@d5 {
512 tsens_s5_p2: s5-p2@d6 {
529 compatible = "qcom,rpm-msg-ram";
534 compatible = "qcom,msm8916-rpm-stats";
539 compatible = "qcom,msm8916-bimc";
541 #interconnect-cells = <1>;
544 tsens: thermal-sensor@4a9000 {
545 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
550 nvmem-cells = <&tsens_mode>,
557 nvmem-cell-names = "mode",
566 interrupt-names = "uplow";
567 #thermal-sensor-cells = <1>;
571 compatible = "qcom,msm8916-pcnoc";
573 #interconnect-cells = <1>;
577 compatible = "qcom,msm8916-snoc";
579 #interconnect-cells = <1>;
583 compatible = "arm,coresight-stm", "arm,primecell";
586 reg-names = "stm-base", "stm-stimulus-base";
588 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
589 clock-names = "apb_pclk", "atclk";
593 out-ports {
596 remote-endpoint = <&funnel0_in7>;
603 /* CTI 0 - TMC connections */
605 compatible = "arm,coresight-cti", "arm,primecell";
608 clocks = <&rpmcc RPM_QDSS_CLK>;
609 clock-names = "apb_pclk";
614 /* CTI 1 - TPIU connections */
616 compatible = "arm,coresight-cti", "arm,primecell";
619 clocks = <&rpmcc RPM_QDSS_CLK>;
620 clock-names = "apb_pclk";
625 /* CTIs 2-11 - no information - not instantiated */
628 compatible = "arm,coresight-tpiu", "arm,primecell";
631 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
632 clock-names = "apb_pclk", "atclk";
636 in-ports {
639 remote-endpoint = <&replicator_out1>;
646 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
649 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
650 clock-names = "apb_pclk", "atclk";
654 in-ports {
655 #address-cells = <1>;
656 #size-cells = <0>;
660 * 0 - connected to Resource and Power Manger CPU ETM
661 * 1 - not-connected
662 * 2 - connected to Modem CPU ETM
663 * 3 - not-connected
664 * 5 - not-connected
665 * 6 - connected trought funnel to Wireless CPU ETM
666 * 7 - connected to STM component
672 remote-endpoint = <&funnel1_out>;
679 remote-endpoint = <&stm_out>;
684 out-ports {
687 remote-endpoint = <&etf_in>;
694 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
697 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
698 clock-names = "apb_pclk", "atclk";
702 out-ports {
703 #address-cells = <1>;
704 #size-cells = <0>;
709 remote-endpoint = <&etr_in>;
715 remote-endpoint = <&tpiu_in>;
720 in-ports {
723 remote-endpoint = <&etf_out>;
730 compatible = "arm,coresight-tmc", "arm,primecell";
733 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
734 clock-names = "apb_pclk", "atclk";
738 in-ports {
741 remote-endpoint = <&funnel0_out>;
746 out-ports {
749 remote-endpoint = <&replicator_in>;
756 compatible = "arm,coresight-tmc", "arm,primecell";
759 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
760 clock-names = "apb_pclk", "atclk";
764 in-ports {
767 remote-endpoint = <&replicator_out0>;
774 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
777 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
778 clock-names = "apb_pclk", "atclk";
782 in-ports {
783 #address-cells = <1>;
784 #size-cells = <0>;
789 remote-endpoint = <&etm0_out>;
795 remote-endpoint = <&etm1_out>;
801 remote-endpoint = <&etm2_out>;
807 remote-endpoint = <&etm3_out>;
812 out-ports {
815 remote-endpoint = <&funnel0_in4>;
822 compatible = "arm,coresight-cpu-debug", "arm,primecell";
824 clocks = <&rpmcc RPM_QDSS_CLK>;
825 clock-names = "apb_pclk";
831 compatible = "arm,coresight-cpu-debug", "arm,primecell";
833 clocks = <&rpmcc RPM_QDSS_CLK>;
834 clock-names = "apb_pclk";
840 compatible = "arm,coresight-cpu-debug", "arm,primecell";
842 clocks = <&rpmcc RPM_QDSS_CLK>;
843 clock-names = "apb_pclk";
849 compatible = "arm,coresight-cpu-debug", "arm,primecell";
851 clocks = <&rpmcc RPM_QDSS_CLK>;
852 clock-names = "apb_pclk";
857 /* Core CTIs; CTIs 12-15 */
858 /* CTI - CPU-0 */
860 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
864 clocks = <&rpmcc RPM_QDSS_CLK>;
865 clock-names = "apb_pclk";
868 arm,cs-dev-assoc = <&etm0>;
873 /* CTI - CPU-1 */
875 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
879 clocks = <&rpmcc RPM_QDSS_CLK>;
880 clock-names = "apb_pclk";
883 arm,cs-dev-assoc = <&etm1>;
888 /* CTI - CPU-2 */
890 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
894 clocks = <&rpmcc RPM_QDSS_CLK>;
895 clock-names = "apb_pclk";
898 arm,cs-dev-assoc = <&etm2>;
903 /* CTI - CPU-3 */
905 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
909 clocks = <&rpmcc RPM_QDSS_CLK>;
910 clock-names = "apb_pclk";
913 arm,cs-dev-assoc = <&etm3>;
919 compatible = "arm,coresight-etm4x", "arm,primecell";
922 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
923 clock-names = "apb_pclk", "atclk";
924 arm,coresight-loses-context-with-cpu;
930 out-ports {
933 remote-endpoint = <&funnel1_in0>;
940 compatible = "arm,coresight-etm4x", "arm,primecell";
943 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
944 clock-names = "apb_pclk", "atclk";
945 arm,coresight-loses-context-with-cpu;
951 out-ports {
954 remote-endpoint = <&funnel1_in1>;
961 compatible = "arm,coresight-etm4x", "arm,primecell";
964 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
965 clock-names = "apb_pclk", "atclk";
966 arm,coresight-loses-context-with-cpu;
972 out-ports {
975 remote-endpoint = <&funnel1_in2>;
982 compatible = "arm,coresight-etm4x", "arm,primecell";
985 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
986 clock-names = "apb_pclk", "atclk";
987 arm,coresight-loses-context-with-cpu;
993 out-ports {
996 remote-endpoint = <&funnel1_in3>;
1003 compatible = "qcom,msm8916-pinctrl";
1006 gpio-controller;
1007 gpio-ranges = <&tlmm 0 0 122>;
1008 #gpio-cells = <2>;
1009 interrupt-controller;
1010 #interrupt-cells = <2>;
1012 blsp_i2c1_default: blsp-i2c1-default-state {
1015 drive-strength = <2>;
1016 bias-disable;
1019 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
1022 drive-strength = <2>;
1023 bias-disable;
1026 blsp_i2c2_default: blsp-i2c2-default-state {
1029 drive-strength = <2>;
1030 bias-disable;
1033 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
1036 drive-strength = <2>;
1037 bias-disable;
1040 blsp_i2c3_default: blsp-i2c3-default-state {
1043 drive-strength = <2>;
1044 bias-disable;
1047 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
1050 drive-strength = <2>;
1051 bias-disable;
1054 blsp_i2c4_default: blsp-i2c4-default-state {
1057 drive-strength = <2>;
1058 bias-disable;
1061 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
1064 drive-strength = <2>;
1065 bias-disable;
1068 blsp_i2c5_default: blsp-i2c5-default-state {
1071 drive-strength = <2>;
1072 bias-disable;
1075 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
1078 drive-strength = <2>;
1079 bias-disable;
1082 blsp_i2c6_default: blsp-i2c6-default-state {
1085 drive-strength = <2>;
1086 bias-disable;
1089 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
1092 drive-strength = <2>;
1093 bias-disable;
1096 blsp_spi1_default: blsp-spi1-default-state {
1097 spi-pins {
1100 drive-strength = <12>;
1101 bias-disable;
1103 cs-pins {
1106 drive-strength = <16>;
1107 bias-disable;
1108 output-high;
1112 blsp_spi1_sleep: blsp-spi1-sleep-state {
1115 drive-strength = <2>;
1116 bias-pull-down;
1119 blsp_spi2_default: blsp-spi2-default-state {
1120 spi-pins {
1123 drive-strength = <12>;
1124 bias-disable;
1126 cs-pins {
1129 drive-strength = <16>;
1130 bias-disable;
1131 output-high;
1135 blsp_spi2_sleep: blsp-spi2-sleep-state {
1138 drive-strength = <2>;
1139 bias-pull-down;
1142 blsp_spi3_default: blsp-spi3-default-state {
1143 spi-pins {
1146 drive-strength = <12>;
1147 bias-disable;
1149 cs-pins {
1152 drive-strength = <16>;
1153 bias-disable;
1154 output-high;
1158 blsp_spi3_sleep: blsp-spi3-sleep-state {
1161 drive-strength = <2>;
1162 bias-pull-down;
1165 blsp_spi4_default: blsp-spi4-default-state {
1166 spi-pins {
1169 drive-strength = <12>;
1170 bias-disable;
1172 cs-pins {
1175 drive-strength = <16>;
1176 bias-disable;
1177 output-high;
1181 blsp_spi4_sleep: blsp-spi4-sleep-state {
1184 drive-strength = <2>;
1185 bias-pull-down;
1188 blsp_spi5_default: blsp-spi5-default-state {
1189 spi-pins {
1192 drive-strength = <12>;
1193 bias-disable;
1195 cs-pins {
1198 drive-strength = <16>;
1199 bias-disable;
1200 output-high;
1204 blsp_spi5_sleep: blsp-spi5-sleep-state {
1207 drive-strength = <2>;
1208 bias-pull-down;
1211 blsp_spi6_default: blsp-spi6-default-state {
1212 spi-pins {
1215 drive-strength = <12>;
1216 bias-disable;
1218 cs-pins {
1221 drive-strength = <16>;
1222 bias-disable;
1223 output-high;
1227 blsp_spi6_sleep: blsp-spi6-sleep-state {
1230 drive-strength = <2>;
1231 bias-pull-down;
1234 blsp_uart1_default: blsp-uart1-default-state {
1238 drive-strength = <16>;
1239 bias-disable;
1242 blsp_uart1_sleep: blsp-uart1-sleep-state {
1245 drive-strength = <2>;
1246 bias-pull-down;
1249 blsp_uart2_default: blsp-uart2-default-state {
1252 drive-strength = <16>;
1253 bias-disable;
1256 blsp_uart2_sleep: blsp-uart2-sleep-state {
1259 drive-strength = <2>;
1260 bias-pull-down;
1263 camera_front_default: camera-front-default-state {
1264 pwdn-pins {
1267 drive-strength = <16>;
1268 bias-disable;
1270 rst-pins {
1273 drive-strength = <16>;
1274 bias-disable;
1276 mclk1-pins {
1279 drive-strength = <16>;
1280 bias-disable;
1284 camera_rear_default: camera-rear-default-state {
1285 pwdn-pins {
1288 drive-strength = <16>;
1289 bias-disable;
1291 rst-pins {
1294 drive-strength = <16>;
1295 bias-disable;
1297 mclk0-pins {
1300 drive-strength = <16>;
1301 bias-disable;
1305 cci0_default: cci0-default-state {
1308 drive-strength = <16>;
1309 bias-disable;
1312 cdc_dmic_default: cdc-dmic-default-state {
1313 clk-pins {
1316 drive-strength = <8>;
1318 data-pins {
1321 drive-strength = <8>;
1325 cdc_dmic_sleep: cdc-dmic-sleep-state {
1326 clk-pins {
1329 drive-strength = <2>;
1330 bias-disable;
1332 data-pins {
1335 drive-strength = <2>;
1336 bias-disable;
1340 cdc_pdm_default: cdc-pdm-default-state {
1344 drive-strength = <8>;
1345 bias-disable;
1348 cdc_pdm_sleep: cdc-pdm-sleep-state {
1352 drive-strength = <2>;
1353 bias-pull-down;
1356 pri_mi2s_default: mi2s-pri-default-state {
1359 drive-strength = <8>;
1360 bias-disable;
1363 pri_mi2s_sleep: mi2s-pri-sleep-state {
1366 drive-strength = <2>;
1367 bias-disable;
1370 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1373 drive-strength = <8>;
1374 bias-disable;
1377 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1380 drive-strength = <2>;
1381 bias-disable;
1384 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1387 drive-strength = <8>;
1388 bias-disable;
1391 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1394 drive-strength = <2>;
1395 bias-disable;
1398 sec_mi2s_default: mi2s-sec-default-state {
1401 drive-strength = <8>;
1402 bias-disable;
1405 sec_mi2s_sleep: mi2s-sec-sleep-state {
1408 drive-strength = <2>;
1409 bias-disable;
1412 sdc1_default: sdc1-default-state {
1413 clk-pins {
1415 bias-disable;
1416 drive-strength = <16>;
1418 cmd-pins {
1420 bias-pull-up;
1421 drive-strength = <10>;
1423 data-pins {
1425 bias-pull-up;
1426 drive-strength = <10>;
1430 sdc1_sleep: sdc1-sleep-state {
1431 clk-pins {
1433 bias-disable;
1434 drive-strength = <2>;
1436 cmd-pins {
1438 bias-pull-up;
1439 drive-strength = <2>;
1441 data-pins {
1443 bias-pull-up;
1444 drive-strength = <2>;
1448 sdc2_default: sdc2-default-state {
1449 clk-pins {
1451 bias-disable;
1452 drive-strength = <16>;
1454 cmd-pins {
1456 bias-pull-up;
1457 drive-strength = <10>;
1459 data-pins {
1461 bias-pull-up;
1462 drive-strength = <10>;
1466 sdc2_sleep: sdc2-sleep-state {
1467 clk-pins {
1469 bias-disable;
1470 drive-strength = <2>;
1472 cmd-pins {
1474 bias-pull-up;
1475 drive-strength = <2>;
1477 data-pins {
1479 bias-pull-up;
1480 drive-strength = <2>;
1484 wcss_wlan_default: wcss-wlan-default-state {
1487 drive-strength = <6>;
1488 bias-pull-up;
1492 gcc: clock-controller@1800000 {
1493 compatible = "qcom,gcc-msm8916";
1494 #clock-cells = <1>;
1495 #reset-cells = <1>;
1496 #power-domain-cells = <1>;
1498 clocks = <&xo_board>,
1505 clock-names = "xo",
1515 compatible = "qcom,tcsr-mutex";
1517 #hwlock-cells = <1>;
1521 compatible = "qcom,tcsr-msm8916", "syscon";
1525 mdss: display-subsystem@1a00000 {
1530 reg-names = "mdss_phys", "vbif_phys";
1532 power-domains = <&gcc MDSS_GDSC>;
1534 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1537 clock-names = "iface",
1543 interrupt-controller;
1544 #interrupt-cells = <1>;
1546 #address-cells = <1>;
1547 #size-cells = <1>;
1550 mdss_mdp: display-controller@1a01000 {
1551 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
1553 reg-names = "mdp_phys";
1555 interrupt-parent = <&mdss>;
1558 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1562 clock-names = "iface",
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1576 remote-endpoint = <&mdss_dsi0_in>;
1583 compatible = "qcom,msm8916-dsi-ctrl",
1584 "qcom,mdss-dsi-ctrl";
1586 reg-names = "dsi_ctrl";
1588 interrupt-parent = <&mdss>;
1591 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1593 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1596 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1602 clock-names = "mdp_core",
1610 #address-cells = <1>;
1611 #size-cells = <0>;
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1620 remote-endpoint = <&mdss_mdp_intf1_out>;
1633 compatible = "qcom,dsi-phy-28nm-lp";
1637 reg-names = "dsi_pll",
1641 #clock-cells = <1>;
1642 #phy-cells = <0>;
1644 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1646 clock-names = "iface", "ref";
1651 compatible = "qcom,msm8916-camss";
1661 reg-names = "csiphy0",
1676 interrupt-names = "csiphy0",
1682 power-domains = <&gcc VFE_GDSC>;
1683 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1702 clock-names = "top_ahb",
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1738 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1743 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1747 clock-names = "camss_top_ahb", "cci_ahb",
1749 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1751 assigned-clock-rates = <80000000>, <19200000>;
1752 pinctrl-names = "default";
1753 pinctrl-0 = <&cci0_default>;
1756 cci_i2c0: i2c-bus@0 {
1758 clock-frequency = <400000>;
1759 #address-cells = <1>;
1760 #size-cells = <0>;
1765 compatible = "qcom,adreno-306.0", "qcom,adreno";
1767 reg-names = "kgsl_3d0_reg_memory";
1769 interrupt-names = "kgsl_3d0_irq";
1770 clock-names =
1777 clocks =
1784 power-domains = <&gcc OXILI_GDSC>;
1785 operating-points-v2 = <&gpu_opp_table>;
1787 #cooling-cells = <2>;
1791 gpu_opp_table: opp-table {
1792 compatible = "operating-points-v2";
1794 opp-400000000 {
1795 opp-hz = /bits/ 64 <400000000>;
1797 opp-19200000 {
1798 opp-hz = /bits/ 64 <19200000>;
1803 venus: video-codec@1d00000 {
1804 compatible = "qcom,msm8916-venus";
1807 power-domains = <&gcc VENUS_GDSC>;
1808 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1811 clock-names = "core", "iface", "bus";
1813 memory-region = <&venus_mem>;
1816 video-decoder {
1817 compatible = "venus-decoder";
1820 video-encoder {
1821 compatible = "venus-encoder";
1826 #address-cells = <1>;
1827 #size-cells = <1>;
1828 #iommu-cells = <1>;
1829 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1832 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1834 clock-names = "iface", "bus";
1835 qcom,iommu-secure-id = <17>;
1838 iommu-ctx@3000 {
1839 compatible = "qcom,msm-iommu-v1-sec";
1845 iommu-ctx@4000 {
1846 compatible = "qcom,msm-iommu-v1-ns";
1852 iommu-ctx@5000 {
1853 compatible = "qcom,msm-iommu-v1-sec";
1860 #address-cells = <1>;
1861 #size-cells = <1>;
1862 #iommu-cells = <1>;
1863 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1865 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1867 clock-names = "iface", "bus";
1868 qcom,iommu-secure-id = <18>;
1871 iommu-ctx@1000 {
1872 compatible = "qcom,msm-iommu-v1-ns";
1878 iommu-ctx@2000 {
1879 compatible = "qcom,msm-iommu-v1-ns";
1886 compatible = "qcom,spmi-pmic-arb";
1892 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1893 interrupt-names = "periph_irq";
1897 #address-cells = <2>;
1898 #size-cells = <0>;
1899 interrupt-controller;
1900 #interrupt-cells = <4>;
1903 bam_dmux_dma: dma-controller@4044000 {
1904 compatible = "qcom,bam-v1.7.0";
1907 #dma-cells = <1>;
1910 num-channels = <6>;
1911 qcom,num-ees = <1>;
1912 qcom,powered-remotely;
1918 compatible = "qcom,msm8916-mss-pil";
1922 reg-names = "qdsp6", "rmb";
1924 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1929 interrupt-names = "wdog", "fatal", "ready",
1930 "handover", "stop-ack";
1932 power-domains = <&rpmpd MSM8916_VDDCX>,
1934 power-domain-names = "cx", "mx";
1936 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1940 clock-names = "iface", "bus", "mem", "xo";
1942 qcom,smem-states = <&hexagon_smp2p_out 0>;
1943 qcom,smem-state-names = "stop";
1946 reset-names = "mss_restart";
1948 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1953 memory-region = <&mba_mem>;
1957 memory-region = <&mpss_mem>;
1960 bam_dmux: bam-dmux {
1961 compatible = "qcom,bam-dmux";
1963 interrupt-parent = <&hexagon_smsm>;
1965 interrupt-names = "pc", "pc-ack";
1967 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1968 qcom,smem-state-names = "pc", "pc-ack";
1971 dma-names = "tx", "rx";
1976 smd-edge {
1979 qcom,smd-edge = <0>;
1981 qcom,remote-pid = <1>;
1986 compatible = "qcom,apr-v2";
1987 qcom,smd-channels = "apr_audio_svc";
1989 #address-cells = <1>;
1990 #size-cells = <0>;
1998 q6afe: service@4 { label
1999 compatible = "qcom,q6afe";
2003 compatible = "qcom,q6afe-dais";
2004 #address-cells = <1>;
2005 #size-cells = <0>;
2006 #sound-dai-cells = <1>;
2015 compatible = "qcom,q6asm-dais";
2016 #address-cells = <1>;
2017 #size-cells = <0>;
2018 #sound-dai-cells = <1>;
2027 compatible = "qcom,q6adm-routing";
2028 #sound-dai-cells = <0>;
2035 qcom,smd-channels = "fastrpcsmd-apps-dsp";
2037 qcom,non-secure-domain;
2039 #address-cells = <1>;
2040 #size-cells = <0>;
2043 compatible = "qcom,fastrpc-compute-cb";
2052 compatible = "qcom,apq8016-sbc-sndcard";
2054 reg-names = "mic-iomux", "spkr-iomux";
2057 lpass: audio-controller@7708000 {
2059 compatible = "qcom,apq8016-lpass-cpu";
2066 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2074 clock-names = "ahbix-clk",
2075 "mi2s-bit-clk0",
2076 "mi2s-bit-clk1",
2077 "mi2s-bit-clk2",
2078 "mi2s-bit-clk3",
2079 "pcnoc-mport-clk",
2080 "pcnoc-sway-clk";
2081 #sound-dai-cells = <1>;
2084 interrupt-names = "lpass-irq-lpaif";
2086 reg-names = "lpass-lpaif";
2088 #address-cells = <1>;
2089 #size-cells = <0>;
2092 lpass_codec: audio-codec@771c000 {
2093 compatible = "qcom,msm8916-wcd-digital-codec";
2095 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2097 clock-names = "ahbix-clk", "mclk";
2098 #sound-dai-cells = <1>;
2103 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2105 reg-names = "hc", "core";
2109 interrupt-names = "hc_irq", "pwr_irq";
2110 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2113 clock-names = "iface", "core", "xo";
2114 pinctrl-0 = <&sdc1_default>;
2115 pinctrl-1 = <&sdc1_sleep>;
2116 pinctrl-names = "default", "sleep";
2117 mmc-ddr-1_8v;
2118 bus-width = <8>;
2119 non-removable;
2124 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2126 reg-names = "hc", "core";
2130 interrupt-names = "hc_irq", "pwr_irq";
2131 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2134 clock-names = "iface", "core", "xo";
2135 pinctrl-0 = <&sdc2_default>;
2136 pinctrl-1 = <&sdc2_sleep>;
2137 pinctrl-names = "default", "sleep";
2138 bus-width = <4>;
2142 blsp_dma: dma-controller@7884000 {
2143 compatible = "qcom,bam-v1.7.0";
2146 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2147 clock-names = "bam_clk";
2148 #dma-cells = <1>;
2150 qcom,controlled-remotely;
2154 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2157 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2158 clock-names = "core", "iface";
2160 dma-names = "tx", "rx";
2161 pinctrl-names = "default", "sleep";
2162 pinctrl-0 = <&blsp_uart1_default>;
2163 pinctrl-1 = <&blsp_uart1_sleep>;
2168 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2171 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2172 clock-names = "core", "iface";
2174 dma-names = "tx", "rx";
2175 pinctrl-names = "default", "sleep";
2176 pinctrl-0 = <&blsp_uart2_default>;
2177 pinctrl-1 = <&blsp_uart2_sleep>;
2182 compatible = "qcom,i2c-qup-v2.2.1";
2185 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2187 clock-names = "core", "iface";
2189 dma-names = "tx", "rx";
2190 pinctrl-names = "default", "sleep";
2191 pinctrl-0 = <&blsp_i2c1_default>;
2192 pinctrl-1 = <&blsp_i2c1_sleep>;
2193 #address-cells = <1>;
2194 #size-cells = <0>;
2199 compatible = "qcom,spi-qup-v2.2.1";
2202 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2204 clock-names = "core", "iface";
2206 dma-names = "tx", "rx";
2207 pinctrl-names = "default", "sleep";
2208 pinctrl-0 = <&blsp_spi1_default>;
2209 pinctrl-1 = <&blsp_spi1_sleep>;
2210 #address-cells = <1>;
2211 #size-cells = <0>;
2216 compatible = "qcom,i2c-qup-v2.2.1";
2219 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2221 clock-names = "core", "iface";
2223 dma-names = "tx", "rx";
2224 pinctrl-names = "default", "sleep";
2225 pinctrl-0 = <&blsp_i2c2_default>;
2226 pinctrl-1 = <&blsp_i2c2_sleep>;
2227 #address-cells = <1>;
2228 #size-cells = <0>;
2233 compatible = "qcom,spi-qup-v2.2.1";
2236 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2238 clock-names = "core", "iface";
2240 dma-names = "tx", "rx";
2241 pinctrl-names = "default", "sleep";
2242 pinctrl-0 = <&blsp_spi2_default>;
2243 pinctrl-1 = <&blsp_spi2_sleep>;
2244 #address-cells = <1>;
2245 #size-cells = <0>;
2250 compatible = "qcom,i2c-qup-v2.2.1";
2253 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2255 clock-names = "core", "iface";
2257 dma-names = "tx", "rx";
2258 pinctrl-names = "default", "sleep";
2259 pinctrl-0 = <&blsp_i2c3_default>;
2260 pinctrl-1 = <&blsp_i2c3_sleep>;
2261 #address-cells = <1>;
2262 #size-cells = <0>;
2267 compatible = "qcom,spi-qup-v2.2.1";
2270 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2272 clock-names = "core", "iface";
2274 dma-names = "tx", "rx";
2275 pinctrl-names = "default", "sleep";
2276 pinctrl-0 = <&blsp_spi3_default>;
2277 pinctrl-1 = <&blsp_spi3_sleep>;
2278 #address-cells = <1>;
2279 #size-cells = <0>;
2284 compatible = "qcom,i2c-qup-v2.2.1";
2287 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2289 clock-names = "core", "iface";
2291 dma-names = "tx", "rx";
2292 pinctrl-names = "default", "sleep";
2293 pinctrl-0 = <&blsp_i2c4_default>;
2294 pinctrl-1 = <&blsp_i2c4_sleep>;
2295 #address-cells = <1>;
2296 #size-cells = <0>;
2301 compatible = "qcom,spi-qup-v2.2.1";
2304 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2306 clock-names = "core", "iface";
2308 dma-names = "tx", "rx";
2309 pinctrl-names = "default", "sleep";
2310 pinctrl-0 = <&blsp_spi4_default>;
2311 pinctrl-1 = <&blsp_spi4_sleep>;
2312 #address-cells = <1>;
2313 #size-cells = <0>;
2318 compatible = "qcom,i2c-qup-v2.2.1";
2321 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2323 clock-names = "core", "iface";
2325 dma-names = "tx", "rx";
2326 pinctrl-names = "default", "sleep";
2327 pinctrl-0 = <&blsp_i2c5_default>;
2328 pinctrl-1 = <&blsp_i2c5_sleep>;
2329 #address-cells = <1>;
2330 #size-cells = <0>;
2335 compatible = "qcom,spi-qup-v2.2.1";
2338 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2340 clock-names = "core", "iface";
2342 dma-names = "tx", "rx";
2343 pinctrl-names = "default", "sleep";
2344 pinctrl-0 = <&blsp_spi5_default>;
2345 pinctrl-1 = <&blsp_spi5_sleep>;
2346 #address-cells = <1>;
2347 #size-cells = <0>;
2352 compatible = "qcom,i2c-qup-v2.2.1";
2355 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2357 clock-names = "core", "iface";
2359 dma-names = "tx", "rx";
2360 pinctrl-names = "default", "sleep";
2361 pinctrl-0 = <&blsp_i2c6_default>;
2362 pinctrl-1 = <&blsp_i2c6_sleep>;
2363 #address-cells = <1>;
2364 #size-cells = <0>;
2369 compatible = "qcom,spi-qup-v2.2.1";
2372 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2374 clock-names = "core", "iface";
2376 dma-names = "tx", "rx";
2377 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp_spi6_default>;
2379 pinctrl-1 = <&blsp_spi6_sleep>;
2380 #address-cells = <1>;
2381 #size-cells = <0>;
2386 compatible = "qcom,ci-hdrc";
2391 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2393 clock-names = "iface", "core";
2394 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2395 assigned-clock-rates = <80000000>;
2397 reset-names = "core";
2400 hnp-disable;
2401 srp-disable;
2402 adp-disable;
2403 ahb-burst-config = <0>;
2404 phy-names = "usb-phy";
2407 #reset-cells = <1>;
2411 compatible = "qcom,usb-hs-phy-msm8916",
2412 "qcom,usb-hs-phy";
2413 #phy-cells = <0>;
2414 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2415 clock-names = "ref", "sleep";
2417 reset-names = "phy", "por";
2418 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2427 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2429 reg-names = "ccu", "dxe", "pmu";
2431 memory-region = <&wcnss_mem>;
2433 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2438 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2440 power-domains = <&rpmpd MSM8916_VDDCX>,
2442 power-domain-names = "cx", "mx";
2444 qcom,smem-states = <&wcnss_smp2p_out 0>;
2445 qcom,smem-state-names = "stop";
2447 pinctrl-names = "default";
2448 pinctrl-0 = <&wcss_wlan_default>;
2453 /* Separate chip, compatible is board-specific */
2454 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2455 clock-names = "xo";
2458 smd-edge {
2462 qcom,smd-edge = <6>;
2463 qcom,remote-pid = <4>;
2469 qcom,smd-channels = "WCNSS_CTRL";
2474 compatible = "qcom,wcnss-bt";
2478 compatible = "qcom,wcnss-wlan";
2482 interrupt-names = "tx", "rx";
2484 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
2485 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
2491 intc: interrupt-controller@b000000 {
2492 compatible = "qcom,msm-qgic2";
2493 interrupt-controller;
2494 #interrupt-cells = <3>;
2501 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
2503 #mbox-cells = <1>;
2504 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
2505 clock-names = "pll", "aux";
2506 #clock-cells = <0>;
2510 compatible = "qcom,msm8916-a53pll";
2512 #clock-cells = <0>;
2513 clocks = <&xo_board>;
2514 clock-names = "xo";
2518 #address-cells = <1>;
2519 #size-cells = <1>;
2521 compatible = "arm,armv7-timer-mem";
2523 clock-frequency = <19200000>;
2526 frame-number = <0>;
2534 frame-number = <1>;
2541 frame-number = <2>;
2548 frame-number = <3>;
2555 frame-number = <4>;
2562 frame-number = <5>;
2569 frame-number = <6>;
2576 cpu0_acc: power-manager@b088000 {
2577 compatible = "qcom,msm8916-acc";
2582 cpu0_saw: power-manager@b089000 {
2583 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2588 cpu1_acc: power-manager@b098000 {
2589 compatible = "qcom,msm8916-acc";
2594 cpu1_saw: power-manager@b099000 {
2595 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2600 cpu2_acc: power-manager@b0a8000 {
2601 compatible = "qcom,msm8916-acc";
2606 cpu2_saw: power-manager@b0a9000 {
2607 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2612 cpu3_acc: power-manager@b0b8000 {
2613 compatible = "qcom,msm8916-acc";
2618 cpu3_saw: power-manager@b0b9000 {
2619 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2625 thermal-zones {
2626 cpu0-1-thermal {
2627 polling-delay-passive = <250>;
2629 thermal-sensors = <&tsens 5>;
2632 cpu0_1_alert0: trip-point0 {
2637 cpu0_1_crit: cpu-crit {
2644 cooling-maps {
2647 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2655 cpu2-3-thermal {
2656 polling-delay-passive = <250>;
2658 thermal-sensors = <&tsens 4>;
2661 cpu2_3_alert0: trip-point0 {
2666 cpu2_3_crit: cpu-crit {
2673 cooling-maps {
2676 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2684 gpu-thermal {
2685 polling-delay-passive = <250>;
2687 thermal-sensors = <&tsens 2>;
2689 cooling-maps {
2692 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2697 gpu_alert0: trip-point0 {
2702 gpu_crit: gpu-crit {
2710 camera-thermal {
2711 polling-delay-passive = <250>;
2713 thermal-sensors = <&tsens 1>;
2716 cam_alert0: trip-point0 {
2724 modem-thermal {
2725 polling-delay-passive = <250>;
2727 thermal-sensors = <&tsens 0>;
2730 modem_alert0: trip-point0 {
2740 compatible = "arm,armv8-timer";