Lines Matching +full:gcc +full:- +full:msm8996
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/interconnect/qcom,icc.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
12 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
13 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
14 #include <dt-bindings/clock/qcom,sa8775p-videocc.h>
15 #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
16 #include <dt-bindings/dma/qcom-gpi.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/firmware/qcom,scm.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/soc/qcom,gpr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
32 xo_board_clk: xo-board-clk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
44 #address-cells = <2>;
45 #size-cells = <0>;
51 enable-method = "psci";
52 power-domains = <&cpu_pd0>;
53 power-domain-names = "psci";
54 qcom,freq-domain = <&cpufreq_hw 0>;
55 next-level-cache = <&l2_0>;
56 capacity-dmips-mhz = <1024>;
57 dynamic-power-coefficient = <100>;
58 operating-points-v2 = <&cpu0_opp_table>;
63 l2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&l3_0>;
68 l3_0: l3-cache {
70 cache-level = <3>;
71 cache-unified;
80 enable-method = "psci";
81 power-domains = <&cpu_pd1>;
82 power-domain-names = "psci";
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 next-level-cache = <&l2_1>;
85 capacity-dmips-mhz = <1024>;
86 dynamic-power-coefficient = <100>;
87 operating-points-v2 = <&cpu0_opp_table>;
92 l2_1: l2-cache {
94 cache-level = <2>;
95 cache-unified;
96 next-level-cache = <&l3_0>;
104 enable-method = "psci";
105 power-domains = <&cpu_pd2>;
106 power-domain-names = "psci";
107 qcom,freq-domain = <&cpufreq_hw 0>;
108 next-level-cache = <&l2_2>;
109 capacity-dmips-mhz = <1024>;
110 dynamic-power-coefficient = <100>;
111 operating-points-v2 = <&cpu0_opp_table>;
116 l2_2: l2-cache {
118 cache-level = <2>;
119 cache-unified;
120 next-level-cache = <&l3_0>;
128 enable-method = "psci";
129 power-domains = <&cpu_pd3>;
130 power-domain-names = "psci";
131 qcom,freq-domain = <&cpufreq_hw 0>;
132 next-level-cache = <&l2_3>;
133 capacity-dmips-mhz = <1024>;
134 dynamic-power-coefficient = <100>;
135 operating-points-v2 = <&cpu0_opp_table>;
140 l2_3: l2-cache {
142 cache-level = <2>;
143 cache-unified;
144 next-level-cache = <&l3_0>;
152 enable-method = "psci";
153 power-domains = <&cpu_pd4>;
154 power-domain-names = "psci";
155 qcom,freq-domain = <&cpufreq_hw 1>;
156 next-level-cache = <&l2_4>;
157 capacity-dmips-mhz = <1024>;
158 dynamic-power-coefficient = <100>;
159 operating-points-v2 = <&cpu4_opp_table>;
164 l2_4: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&l3_1>;
169 l3_1: l3-cache {
171 cache-level = <3>;
172 cache-unified;
182 enable-method = "psci";
183 power-domains = <&cpu_pd5>;
184 power-domain-names = "psci";
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 next-level-cache = <&l2_5>;
187 capacity-dmips-mhz = <1024>;
188 dynamic-power-coefficient = <100>;
189 operating-points-v2 = <&cpu4_opp_table>;
194 l2_5: l2-cache {
196 cache-level = <2>;
197 cache-unified;
198 next-level-cache = <&l3_1>;
206 enable-method = "psci";
207 power-domains = <&cpu_pd6>;
208 power-domain-names = "psci";
209 qcom,freq-domain = <&cpufreq_hw 1>;
210 next-level-cache = <&l2_6>;
211 capacity-dmips-mhz = <1024>;
212 dynamic-power-coefficient = <100>;
213 operating-points-v2 = <&cpu4_opp_table>;
218 l2_6: l2-cache {
220 cache-level = <2>;
221 cache-unified;
222 next-level-cache = <&l3_1>;
230 enable-method = "psci";
231 power-domains = <&cpu_pd7>;
232 power-domain-names = "psci";
233 qcom,freq-domain = <&cpufreq_hw 1>;
234 next-level-cache = <&l2_7>;
235 capacity-dmips-mhz = <1024>;
236 dynamic-power-coefficient = <100>;
237 operating-points-v2 = <&cpu4_opp_table>;
242 l2_7: l2-cache {
244 cache-level = <2>;
245 cache-unified;
246 next-level-cache = <&l3_1>;
250 cpu-map {
288 idle-states {
289 entry-method = "psci";
291 gold_cpu_sleep_0: cpu-sleep-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "gold-power-collapse";
294 arm,psci-suspend-param = <0x40000003>;
295 entry-latency-us = <549>;
296 exit-latency-us = <901>;
297 min-residency-us = <1774>;
298 local-timer-stop;
301 gold_rail_cpu_sleep_0: cpu-sleep-1 {
302 compatible = "arm,idle-state";
303 idle-state-name = "gold-rail-power-collapse";
304 arm,psci-suspend-param = <0x40000004>;
305 entry-latency-us = <702>;
306 exit-latency-us = <1061>;
307 min-residency-us = <4488>;
308 local-timer-stop;
312 domain-idle-states {
313 cluster_sleep_gold: cluster-sleep-0 {
314 compatible = "domain-idle-state";
315 arm,psci-suspend-param = <0x41000044>;
316 entry-latency-us = <2752>;
317 exit-latency-us = <3048>;
318 min-residency-us = <6118>;
321 cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
322 compatible = "domain-idle-state";
323 arm,psci-suspend-param = <0x42000144>;
324 entry-latency-us = <3263>;
325 exit-latency-us = <6562>;
326 min-residency-us = <9987>;
331 cpu0_opp_table: opp-table-cpu0 {
332 compatible = "operating-points-v2";
333 opp-shared;
335 opp-1267200000 {
336 opp-hz = /bits/ 64 <1267200000>;
337 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
340 opp-1363200000 {
341 opp-hz = /bits/ 64 <1363200000>;
342 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
345 opp-1459200000 {
346 opp-hz = /bits/ 64 <1459200000>;
347 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
350 opp-1536000000 {
351 opp-hz = /bits/ 64 <1536000000>;
352 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
355 opp-1632000000 {
356 opp-hz = /bits/ 64 <1632000000>;
357 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
360 opp-1708800000 {
361 opp-hz = /bits/ 64 <1708800000>;
362 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
365 opp-1785600000 {
366 opp-hz = /bits/ 64 <1785600000>;
367 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
370 opp-1862400000 {
371 opp-hz = /bits/ 64 <1862400000>;
372 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
375 opp-1939200000 {
376 opp-hz = /bits/ 64 <1939200000>;
377 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
380 opp-2016000000 {
381 opp-hz = /bits/ 64 <2016000000>;
382 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
385 opp-2112000000 {
386 opp-hz = /bits/ 64 <2112000000>;
387 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
390 opp-2188800000 {
391 opp-hz = /bits/ 64 <2188800000>;
392 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
395 opp-2265600000 {
396 opp-hz = /bits/ 64 <2265600000>;
397 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
400 opp-2361600000 {
401 opp-hz = /bits/ 64 <2361600000>;
402 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
405 opp-2457600000 {
406 opp-hz = /bits/ 64 <2457600000>;
407 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
410 opp-2553600000 {
411 opp-hz = /bits/ 64 <2553600000>;
412 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
416 cpu4_opp_table: opp-table-cpu4 {
417 compatible = "operating-points-v2";
418 opp-shared;
420 opp-1267200000 {
421 opp-hz = /bits/ 64 <1267200000>;
422 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
425 opp-1363200000 {
426 opp-hz = /bits/ 64 <1363200000>;
427 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
430 opp-1459200000 {
431 opp-hz = /bits/ 64 <1459200000>;
432 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
435 opp-1536000000 {
436 opp-hz = /bits/ 64 <1536000000>;
437 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
440 opp-1632000000 {
441 opp-hz = /bits/ 64 <1632000000>;
442 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
445 opp-1708800000 {
446 opp-hz = /bits/ 64 <1708800000>;
447 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
450 opp-1785600000 {
451 opp-hz = /bits/ 64 <1785600000>;
452 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
455 opp-1862400000 {
456 opp-hz = /bits/ 64 <1862400000>;
457 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
460 opp-1939200000 {
461 opp-hz = /bits/ 64 <1939200000>;
462 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
465 opp-2016000000 {
466 opp-hz = /bits/ 64 <2016000000>;
467 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
470 opp-2112000000 {
471 opp-hz = /bits/ 64 <2112000000>;
472 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
475 opp-2188800000 {
476 opp-hz = /bits/ 64 <2188800000>;
477 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
480 opp-2265600000 {
481 opp-hz = /bits/ 64 <2265600000>;
482 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
485 opp-2361600000 {
486 opp-hz = /bits/ 64 <2361600000>;
487 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
490 opp-2457600000 {
491 opp-hz = /bits/ 64 <2457600000>;
492 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
495 opp-2553600000 {
496 opp-hz = /bits/ 64 <2553600000>;
497 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
501 dummy-sink {
502 compatible = "arm,coresight-dummy-sink";
504 in-ports {
507 remote-endpoint =
516 compatible = "qcom,scm-sa8775p", "qcom,scm";
517 qcom,dload-mode = <&tcsr 0x13000>;
521 aggre1_noc: interconnect-aggre1-noc {
522 compatible = "qcom,sa8775p-aggre1-noc";
523 #interconnect-cells = <2>;
524 qcom,bcm-voters = <&apps_bcm_voter>;
527 aggre2_noc: interconnect-aggre2-noc {
528 compatible = "qcom,sa8775p-aggre2-noc";
529 #interconnect-cells = <2>;
530 qcom,bcm-voters = <&apps_bcm_voter>;
533 clk_virt: interconnect-clk-virt {
534 compatible = "qcom,sa8775p-clk-virt";
535 #interconnect-cells = <2>;
536 qcom,bcm-voters = <&apps_bcm_voter>;
539 config_noc: interconnect-config-noc {
540 compatible = "qcom,sa8775p-config-noc";
541 #interconnect-cells = <2>;
542 qcom,bcm-voters = <&apps_bcm_voter>;
545 dc_noc: interconnect-dc-noc {
546 compatible = "qcom,sa8775p-dc-noc";
547 #interconnect-cells = <2>;
548 qcom,bcm-voters = <&apps_bcm_voter>;
551 gem_noc: interconnect-gem-noc {
552 compatible = "qcom,sa8775p-gem-noc";
553 #interconnect-cells = <2>;
554 qcom,bcm-voters = <&apps_bcm_voter>;
557 gpdsp_anoc: interconnect-gpdsp-anoc {
558 compatible = "qcom,sa8775p-gpdsp-anoc";
559 #interconnect-cells = <2>;
560 qcom,bcm-voters = <&apps_bcm_voter>;
563 lpass_ag_noc: interconnect-lpass-ag-noc {
564 compatible = "qcom,sa8775p-lpass-ag-noc";
565 #interconnect-cells = <2>;
566 qcom,bcm-voters = <&apps_bcm_voter>;
569 mc_virt: interconnect-mc-virt {
570 compatible = "qcom,sa8775p-mc-virt";
571 #interconnect-cells = <2>;
572 qcom,bcm-voters = <&apps_bcm_voter>;
575 mmss_noc: interconnect-mmss-noc {
576 compatible = "qcom,sa8775p-mmss-noc";
577 #interconnect-cells = <2>;
578 qcom,bcm-voters = <&apps_bcm_voter>;
581 nspa_noc: interconnect-nspa-noc {
582 compatible = "qcom,sa8775p-nspa-noc";
583 #interconnect-cells = <2>;
584 qcom,bcm-voters = <&apps_bcm_voter>;
587 nspb_noc: interconnect-nspb-noc {
588 compatible = "qcom,sa8775p-nspb-noc";
589 #interconnect-cells = <2>;
590 qcom,bcm-voters = <&apps_bcm_voter>;
593 pcie_anoc: interconnect-pcie-anoc {
594 compatible = "qcom,sa8775p-pcie-anoc";
595 #interconnect-cells = <2>;
596 qcom,bcm-voters = <&apps_bcm_voter>;
599 system_noc: interconnect-system-noc {
600 compatible = "qcom,sa8775p-system-noc";
601 #interconnect-cells = <2>;
602 qcom,bcm-voters = <&apps_bcm_voter>;
611 qup_opp_table_100mhz: opp-table-qup100mhz {
612 compatible = "operating-points-v2";
614 opp-100000000 {
615 opp-hz = /bits/ 64 <100000000>;
616 required-opps = <&rpmhpd_opp_svs_l1>;
621 compatible = "arm,armv8-pmuv3";
626 compatible = "arm,psci-1.0";
629 cpu_pd0: power-domain-cpu0 {
630 #power-domain-cells = <0>;
631 power-domains = <&cluster_0_pd>;
632 domain-idle-states = <&gold_cpu_sleep_0>,
636 cpu_pd1: power-domain-cpu1 {
637 #power-domain-cells = <0>;
638 power-domains = <&cluster_0_pd>;
639 domain-idle-states = <&gold_cpu_sleep_0>,
643 cpu_pd2: power-domain-cpu2 {
644 #power-domain-cells = <0>;
645 power-domains = <&cluster_0_pd>;
646 domain-idle-states = <&gold_cpu_sleep_0>,
650 cpu_pd3: power-domain-cpu3 {
651 #power-domain-cells = <0>;
652 power-domains = <&cluster_0_pd>;
653 domain-idle-states = <&gold_cpu_sleep_0>,
657 cpu_pd4: power-domain-cpu4 {
658 #power-domain-cells = <0>;
659 power-domains = <&cluster_1_pd>;
660 domain-idle-states = <&gold_cpu_sleep_0>,
664 cpu_pd5: power-domain-cpu5 {
665 #power-domain-cells = <0>;
666 power-domains = <&cluster_1_pd>;
667 domain-idle-states = <&gold_cpu_sleep_0>,
671 cpu_pd6: power-domain-cpu6 {
672 #power-domain-cells = <0>;
673 power-domains = <&cluster_1_pd>;
674 domain-idle-states = <&gold_cpu_sleep_0>,
678 cpu_pd7: power-domain-cpu7 {
679 #power-domain-cells = <0>;
680 power-domains = <&cluster_1_pd>;
681 domain-idle-states = <&gold_cpu_sleep_0>,
685 cluster_0_pd: power-domain-cluster0 {
686 #power-domain-cells = <0>;
687 domain-idle-states = <&cluster_sleep_gold>;
688 power-domains = <&system_pd>;
691 cluster_1_pd: power-domain-cluster1 {
692 #power-domain-cells = <0>;
693 domain-idle-states = <&cluster_sleep_gold>;
694 power-domains = <&system_pd>;
697 system_pd: power-domain-system {
698 #power-domain-cells = <0>;
699 domain-idle-states = <&cluster_sleep_apss_rsc_pc>;
703 reserved-memory {
704 #address-cells = <2>;
705 #size-cells = <2>;
708 sail_ss_mem: sail-ss@80000000 {
710 no-map;
715 no-map;
718 xbl_boot_mem: xbl-boot@90600000 {
720 no-map;
723 aop_image_mem: aop-image@90800000 {
725 no-map;
728 aop_cmd_db_mem: aop-cmd-db@90860000 {
729 compatible = "qcom,cmd-db";
731 no-map;
734 uefi_log: uefi-log@908b0000 {
736 no-map;
739 ddr_training_checksum: ddr-training-checksum@908c0000 {
741 no-map;
746 no-map;
749 secdata_apss_mem: secdata-apss@908fe000 {
751 no-map;
757 no-map;
761 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
763 no-map;
766 sail_mailbox_mem: sail-ss@90d00000 {
768 no-map;
771 sail_ota_mem: sail-ss@90e00000 {
773 no-map;
776 gunyah_md_mem: gunyah-md@91a80000 {
778 no-map;
781 aoss_backup_mem: aoss-backup@91b00000 {
783 no-map;
786 cpucp_backup_mem: cpucp-backup@91b40000 {
788 no-map;
791 tz_config_backup_mem: tz-config-backup@91b80000 {
793 no-map;
796 ddr_training_data_mem: ddr-training-data@91b90000 {
798 no-map;
801 cdt_data_backup_mem: cdt-data-backup@91ba0000 {
803 no-map;
806 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
808 no-map;
811 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
813 no-map;
816 pil_camera_mem: pil-camera@95200000 {
818 no-map;
821 pil_adsp_mem: pil-adsp@95900000 {
823 no-map;
826 q6_adsp_dtb_mem: q6-adsp-dtb@97700000 {
828 no-map;
831 q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 {
833 no-map;
836 pil_gdsp0_mem: pil-gdsp0@97800000 {
838 no-map;
841 pil_gdsp1_mem: pil-gdsp1@99600000 {
843 no-map;
846 q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 {
848 no-map;
851 q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 {
853 no-map;
856 pil_cdsp0_mem: pil-cdsp0@9b500000 {
858 no-map;
861 pil_gpu_mem: pil-gpu@9d300000 {
863 no-map;
866 q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 {
868 no-map;
871 pil_cdsp1_mem: pil-cdsp1@9d400000 {
873 no-map;
876 pil_cvp_mem: pil-cvp@9f200000 {
878 no-map;
881 pil_video_mem: pil-video@9f900000 {
883 no-map;
886 firmware_mem: firmware-region@b0000000 {
888 no-map;
891 scmi_mem: scmi-region@d0000000 {
893 no-map;
896 firmware_logs_mem: firmware-logs@d0040000 {
898 no-map;
901 firmware_audio_mem: firmware-audio@d0050000 {
903 no-map;
906 firmware_reserved_mem: firmware-reserved@d0054000 {
908 no-map;
911 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
913 no-map;
918 no-map;
923 no-map;
926 deepsleep_backup_mem: deepsleep-backup@d1800000 {
928 no-map;
931 trusted_apps_mem: trusted-apps@d1900000 {
933 no-map;
936 tz_stat_mem: tz-stat@db100000 {
938 no-map;
941 cpucp_fw_mem: cpucp-fw@db200000 {
943 no-map;
947 smp2p-adsp {
950 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
955 qcom,local-pid = <0>;
956 qcom,remote-pid = <2>;
958 smp2p_adsp_out: master-kernel {
959 qcom,entry-name = "master-kernel";
960 #qcom,smem-state-cells = <1>;
963 smp2p_adsp_in: slave-kernel {
964 qcom,entry-name = "slave-kernel";
965 interrupt-controller;
966 #interrupt-cells = <2>;
970 smp2p-cdsp0 {
973 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
978 qcom,local-pid = <0>;
979 qcom,remote-pid = <5>;
981 smp2p_cdsp0_out: master-kernel {
982 qcom,entry-name = "master-kernel";
983 #qcom,smem-state-cells = <1>;
986 smp2p_cdsp0_in: slave-kernel {
987 qcom,entry-name = "slave-kernel";
988 interrupt-controller;
989 #interrupt-cells = <2>;
993 smp2p-cdsp1 {
996 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
1001 qcom,local-pid = <0>;
1002 qcom,remote-pid = <12>;
1004 smp2p_cdsp1_out: master-kernel {
1005 qcom,entry-name = "master-kernel";
1006 #qcom,smem-state-cells = <1>;
1009 smp2p_cdsp1_in: slave-kernel {
1010 qcom,entry-name = "slave-kernel";
1011 interrupt-controller;
1012 #interrupt-cells = <2>;
1016 smp2p-gpdsp0 {
1019 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
1024 qcom,local-pid = <0>;
1025 qcom,remote-pid = <17>;
1027 smp2p_gpdsp0_out: master-kernel {
1028 qcom,entry-name = "master-kernel";
1029 #qcom,smem-state-cells = <1>;
1032 smp2p_gpdsp0_in: slave-kernel {
1033 qcom,entry-name = "slave-kernel";
1034 interrupt-controller;
1035 #interrupt-cells = <2>;
1039 smp2p-gpdsp1 {
1042 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
1047 qcom,local-pid = <0>;
1048 qcom,remote-pid = <18>;
1050 smp2p_gpdsp1_out: master-kernel {
1051 qcom,entry-name = "master-kernel";
1052 #qcom,smem-state-cells = <1>;
1055 smp2p_gpdsp1_in: slave-kernel {
1056 qcom,entry-name = "slave-kernel";
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1063 compatible = "simple-bus";
1064 #address-cells = <2>;
1065 #size-cells = <2>;
1068 gcc: clock-controller@100000 { label
1069 compatible = "qcom,sa8775p-gcc";
1071 #clock-cells = <1>;
1072 #reset-cells = <1>;
1073 #power-domain-cells = <1>;
1089 power-domains = <&rpmhpd SA8775P_CX>;
1093 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
1096 interrupt-controller;
1097 #interrupt-cells = <3>;
1098 #mbox-cells = <2>;
1101 gpi_dma2: dma-controller@800000 {
1102 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
1104 #dma-cells = <3>;
1117 dma-channels = <12>;
1118 dma-channel-mask = <0xfff>;
1124 compatible = "qcom,geni-se-qup";
1127 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1128 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1129 clock-names = "m-ahb", "s-ahb";
1131 #address-cells = <2>;
1132 #size-cells = <2>;
1136 compatible = "qcom,geni-i2c";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1141 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1142 clock-names = "se";
1143 pinctrl-0 = <&qup_i2c14_default>;
1144 pinctrl-names = "default";
1151 interconnect-names = "qup-core",
1152 "qup-config",
1153 "qup-memory";
1154 power-domains = <&rpmhpd SA8775P_CX>;
1157 dma-names = "tx",
1163 compatible = "qcom,geni-spi";
1165 #address-cells = <1>;
1166 #size-cells = <0>;
1168 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1169 clock-names = "se";
1170 pinctrl-0 = <&qup_spi14_default>;
1171 pinctrl-names = "default";
1178 interconnect-names = "qup-core",
1179 "qup-config",
1180 "qup-memory";
1181 power-domains = <&rpmhpd SA8775P_CX>;
1184 dma-names = "tx",
1190 compatible = "qcom,geni-uart";
1193 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1194 clock-names = "se";
1195 pinctrl-0 = <&qup_uart14_default>;
1196 pinctrl-names = "default";
1201 interconnect-names = "qup-core", "qup-config";
1202 power-domains = <&rpmhpd SA8775P_CX>;
1207 compatible = "qcom,geni-i2c";
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1212 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1213 clock-names = "se";
1214 pinctrl-0 = <&qup_i2c15_default>;
1215 pinctrl-names = "default";
1222 interconnect-names = "qup-core",
1223 "qup-config",
1224 "qup-memory";
1225 power-domains = <&rpmhpd SA8775P_CX>;
1228 dma-names = "tx",
1234 compatible = "qcom,geni-spi";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1239 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1240 clock-names = "se";
1241 pinctrl-0 = <&qup_spi15_default>;
1242 pinctrl-names = "default";
1249 interconnect-names = "qup-core",
1250 "qup-config",
1251 "qup-memory";
1252 power-domains = <&rpmhpd SA8775P_CX>;
1255 dma-names = "tx",
1261 compatible = "qcom,geni-uart";
1264 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1265 clock-names = "se";
1266 pinctrl-0 = <&qup_uart15_default>;
1267 pinctrl-names = "default";
1272 interconnect-names = "qup-core", "qup-config";
1273 power-domains = <&rpmhpd SA8775P_CX>;
1278 compatible = "qcom,geni-i2c";
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1283 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1284 clock-names = "se";
1285 pinctrl-0 = <&qup_i2c16_default>;
1286 pinctrl-names = "default";
1293 interconnect-names = "qup-core",
1294 "qup-config",
1295 "qup-memory";
1296 power-domains = <&rpmhpd SA8775P_CX>;
1299 dma-names = "tx",
1305 compatible = "qcom,geni-spi";
1308 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1309 clock-names = "se";
1310 pinctrl-0 = <&qup_spi16_default>;
1311 pinctrl-names = "default";
1318 interconnect-names = "qup-core",
1319 "qup-config",
1320 "qup-memory";
1321 power-domains = <&rpmhpd SA8775P_CX>;
1324 dma-names = "tx",
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1332 compatible = "qcom,geni-uart";
1335 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1336 clock-names = "se";
1337 pinctrl-0 = <&qup_uart16_default>;
1338 pinctrl-names = "default";
1343 interconnect-names = "qup-core", "qup-config";
1344 power-domains = <&rpmhpd SA8775P_CX>;
1349 compatible = "qcom,geni-i2c";
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1354 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1355 clock-names = "se";
1356 pinctrl-0 = <&qup_i2c17_default>;
1357 pinctrl-names = "default";
1364 interconnect-names = "qup-core",
1365 "qup-config",
1366 "qup-memory";
1367 power-domains = <&rpmhpd SA8775P_CX>;
1370 dma-names = "tx",
1376 compatible = "qcom,geni-spi";
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1381 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1382 clock-names = "se";
1383 pinctrl-0 = <&qup_spi17_default>;
1384 pinctrl-names = "default";
1391 interconnect-names = "qup-core",
1392 "qup-config",
1393 "qup-memory";
1394 power-domains = <&rpmhpd SA8775P_CX>;
1397 dma-names = "tx",
1403 compatible = "qcom,geni-uart";
1406 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1407 clock-names = "se";
1408 pinctrl-0 = <&qup_uart17_default>;
1409 pinctrl-names = "default";
1414 interconnect-names = "qup-core", "qup-config";
1415 power-domains = <&rpmhpd SA8775P_CX>;
1420 compatible = "qcom,geni-i2c";
1423 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1424 clock-names = "se";
1425 pinctrl-0 = <&qup_i2c18_default>;
1426 pinctrl-names = "default";
1433 interconnect-names = "qup-core",
1434 "qup-config",
1435 "qup-memory";
1436 power-domains = <&rpmhpd SA8775P_CX>;
1439 dma-names = "tx",
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1447 compatible = "qcom,geni-spi";
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1452 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1453 clock-names = "se";
1454 pinctrl-0 = <&qup_spi18_default>;
1455 pinctrl-names = "default";
1462 interconnect-names = "qup-core",
1463 "qup-config",
1464 "qup-memory";
1465 power-domains = <&rpmhpd SA8775P_CX>;
1468 dma-names = "tx",
1474 compatible = "qcom,geni-uart";
1477 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1478 clock-names = "se";
1479 pinctrl-0 = <&qup_uart18_default>;
1480 pinctrl-names = "default";
1485 interconnect-names = "qup-core", "qup-config";
1486 power-domains = <&rpmhpd SA8775P_CX>;
1491 compatible = "qcom,geni-i2c";
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1496 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1497 clock-names = "se";
1498 pinctrl-0 = <&qup_i2c19_default>;
1499 pinctrl-names = "default";
1506 interconnect-names = "qup-core",
1507 "qup-config",
1508 "qup-memory";
1509 power-domains = <&rpmhpd SA8775P_CX>;
1512 dma-names = "tx",
1518 compatible = "qcom,geni-spi";
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1523 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1524 clock-names = "se";
1525 pinctrl-0 = <&qup_spi19_default>;
1526 pinctrl-names = "default";
1533 interconnect-names = "qup-core",
1534 "qup-config",
1535 "qup-memory";
1536 power-domains = <&rpmhpd SA8775P_CX>;
1539 dma-names = "tx",
1545 compatible = "qcom,geni-uart";
1548 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1549 clock-names = "se";
1550 pinctrl-0 = <&qup_uart19_default>;
1551 pinctrl-names = "default";
1556 interconnect-names = "qup-core", "qup-config";
1557 power-domains = <&rpmhpd SA8775P_CX>;
1562 compatible = "qcom,geni-i2c";
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1567 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1568 clock-names = "se";
1569 pinctrl-0 = <&qup_i2c20_default>;
1570 pinctrl-names = "default";
1577 interconnect-names = "qup-core",
1578 "qup-config",
1579 "qup-memory";
1580 power-domains = <&rpmhpd SA8775P_CX>;
1583 dma-names = "tx",
1589 compatible = "qcom,geni-spi";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1594 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1595 clock-names = "se";
1596 pinctrl-0 = <&qup_spi20_default>;
1597 pinctrl-names = "default";
1604 interconnect-names = "qup-core",
1605 "qup-config",
1606 "qup-memory";
1607 power-domains = <&rpmhpd SA8775P_CX>;
1610 dma-names = "tx",
1616 compatible = "qcom,geni-uart";
1619 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1620 clock-names = "se";
1621 pinctrl-0 = <&qup_uart20_default>;
1622 pinctrl-names = "default";
1627 interconnect-names = "qup-core", "qup-config";
1628 power-domains = <&rpmhpd SA8775P_CX>;
1634 gpi_dma0: dma-controller@900000 {
1635 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
1637 #dma-cells = <3>;
1650 dma-channels = <12>;
1651 dma-channel-mask = <0xfff>;
1657 compatible = "qcom,geni-se-qup";
1659 #address-cells = <2>;
1660 #size-cells = <2>;
1662 clock-names = "m-ahb", "s-ahb";
1663 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1664 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1669 compatible = "qcom,geni-i2c";
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1674 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1675 clock-names = "se";
1676 pinctrl-0 = <&qup_i2c0_default>;
1677 pinctrl-names = "default";
1684 interconnect-names = "qup-core",
1685 "qup-config",
1686 "qup-memory";
1687 power-domains = <&rpmhpd SA8775P_CX>;
1690 dma-names = "tx",
1696 compatible = "qcom,geni-spi";
1698 #address-cells = <1>;
1699 #size-cells = <0>;
1701 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1702 clock-names = "se";
1703 pinctrl-0 = <&qup_spi0_default>;
1704 pinctrl-names = "default";
1711 interconnect-names = "qup-core",
1712 "qup-config",
1713 "qup-memory";
1714 power-domains = <&rpmhpd SA8775P_CX>;
1717 dma-names = "tx",
1723 compatible = "qcom,geni-uart";
1726 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1727 clock-names = "se";
1728 pinctrl-0 = <&qup_uart0_default>;
1729 pinctrl-names = "default";
1734 interconnect-names = "qup-core", "qup-config";
1735 power-domains = <&rpmhpd SA8775P_CX>;
1740 compatible = "qcom,geni-i2c";
1742 #address-cells = <1>;
1743 #size-cells = <0>;
1745 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1746 clock-names = "se";
1747 pinctrl-0 = <&qup_i2c1_default>;
1748 pinctrl-names = "default";
1755 interconnect-names = "qup-core",
1756 "qup-config",
1757 "qup-memory";
1758 power-domains = <&rpmhpd SA8775P_CX>;
1761 dma-names = "tx",
1767 compatible = "qcom,geni-spi";
1769 #address-cells = <1>;
1770 #size-cells = <0>;
1772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1773 clock-names = "se";
1774 pinctrl-0 = <&qup_spi1_default>;
1775 pinctrl-names = "default";
1782 interconnect-names = "qup-core",
1783 "qup-config",
1784 "qup-memory";
1785 power-domains = <&rpmhpd SA8775P_CX>;
1788 dma-names = "tx",
1794 compatible = "qcom,geni-uart";
1797 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1798 clock-names = "se";
1799 pinctrl-0 = <&qup_uart1_default>;
1800 pinctrl-names = "default";
1805 interconnect-names = "qup-core", "qup-config";
1806 power-domains = <&rpmhpd SA8775P_CX>;
1811 compatible = "qcom,geni-i2c";
1813 #address-cells = <1>;
1814 #size-cells = <0>;
1816 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1817 clock-names = "se";
1818 pinctrl-0 = <&qup_i2c2_default>;
1819 pinctrl-names = "default";
1826 interconnect-names = "qup-core",
1827 "qup-config",
1828 "qup-memory";
1829 power-domains = <&rpmhpd SA8775P_CX>;
1832 dma-names = "tx",
1838 compatible = "qcom,geni-spi";
1840 #address-cells = <1>;
1841 #size-cells = <0>;
1843 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1844 clock-names = "se";
1845 pinctrl-0 = <&qup_spi2_default>;
1846 pinctrl-names = "default";
1853 interconnect-names = "qup-core",
1854 "qup-config",
1855 "qup-memory";
1856 power-domains = <&rpmhpd SA8775P_CX>;
1859 dma-names = "tx",
1865 compatible = "qcom,geni-uart";
1868 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1869 clock-names = "se";
1870 pinctrl-0 = <&qup_uart2_default>;
1871 pinctrl-names = "default";
1876 interconnect-names = "qup-core", "qup-config";
1877 power-domains = <&rpmhpd SA8775P_CX>;
1882 compatible = "qcom,geni-i2c";
1884 #address-cells = <1>;
1885 #size-cells = <0>;
1887 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1888 clock-names = "se";
1889 pinctrl-0 = <&qup_i2c3_default>;
1890 pinctrl-names = "default";
1897 interconnect-names = "qup-core",
1898 "qup-config",
1899 "qup-memory";
1900 power-domains = <&rpmhpd SA8775P_CX>;
1903 dma-names = "tx",
1909 compatible = "qcom,geni-spi";
1911 #address-cells = <1>;
1912 #size-cells = <0>;
1914 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1915 clock-names = "se";
1916 pinctrl-0 = <&qup_spi3_default>;
1917 pinctrl-names = "default";
1924 interconnect-names = "qup-core",
1925 "qup-config",
1926 "qup-memory";
1927 power-domains = <&rpmhpd SA8775P_CX>;
1930 dma-names = "tx",
1936 compatible = "qcom,geni-uart";
1939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1940 clock-names = "se";
1941 pinctrl-0 = <&qup_uart3_default>;
1942 pinctrl-names = "default";
1947 interconnect-names = "qup-core", "qup-config";
1948 power-domains = <&rpmhpd SA8775P_CX>;
1953 compatible = "qcom,geni-i2c";
1955 #address-cells = <1>;
1956 #size-cells = <0>;
1958 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1959 clock-names = "se";
1960 pinctrl-0 = <&qup_i2c4_default>;
1961 pinctrl-names = "default";
1968 interconnect-names = "qup-core",
1969 "qup-config",
1970 "qup-memory";
1971 power-domains = <&rpmhpd SA8775P_CX>;
1974 dma-names = "tx",
1980 compatible = "qcom,geni-spi";
1982 #address-cells = <1>;
1983 #size-cells = <0>;
1985 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1986 clock-names = "se";
1987 pinctrl-0 = <&qup_spi4_default>;
1988 pinctrl-names = "default";
1995 interconnect-names = "qup-core",
1996 "qup-config",
1997 "qup-memory";
1998 power-domains = <&rpmhpd SA8775P_CX>;
2001 dma-names = "tx",
2007 compatible = "qcom,geni-uart";
2010 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2011 clock-names = "se";
2012 pinctrl-0 = <&qup_uart4_default>;
2013 pinctrl-names = "default";
2018 interconnect-names = "qup-core", "qup-config";
2019 power-domains = <&rpmhpd SA8775P_CX>;
2024 compatible = "qcom,geni-i2c";
2026 #address-cells = <1>;
2027 #size-cells = <0>;
2029 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2030 clock-names = "se";
2031 pinctrl-0 = <&qup_i2c5_default>;
2032 pinctrl-names = "default";
2039 interconnect-names = "qup-core",
2040 "qup-config",
2041 "qup-memory";
2042 power-domains = <&rpmhpd SA8775P_CX>;
2045 dma-names = "tx",
2051 compatible = "qcom,geni-spi";
2053 #address-cells = <1>;
2054 #size-cells = <0>;
2056 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2057 clock-names = "se";
2058 pinctrl-0 = <&qup_spi5_default>;
2059 pinctrl-names = "default";
2066 interconnect-names = "qup-core",
2067 "qup-config",
2068 "qup-memory";
2069 power-domains = <&rpmhpd SA8775P_CX>;
2072 dma-names = "tx",
2078 compatible = "qcom,geni-uart";
2081 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2082 clock-names = "se";
2083 pinctrl-0 = <&qup_uart5_default>;
2084 pinctrl-names = "default";
2089 interconnect-names = "qup-core", "qup-config";
2090 power-domains = <&rpmhpd SA8775P_CX>;
2095 gpi_dma1: dma-controller@a00000 {
2096 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
2098 #dma-cells = <3>;
2112 dma-channels = <12>;
2113 dma-channel-mask = <0xfff>;
2118 compatible = "qcom,geni-se-qup";
2120 #address-cells = <2>;
2121 #size-cells = <2>;
2123 clock-names = "m-ahb", "s-ahb";
2124 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
2125 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
2130 compatible = "qcom,geni-i2c";
2132 #address-cells = <1>;
2133 #size-cells = <0>;
2135 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
2136 clock-names = "se";
2137 pinctrl-0 = <&qup_i2c7_default>;
2138 pinctrl-names = "default";
2145 interconnect-names = "qup-core",
2146 "qup-config",
2147 "qup-memory";
2148 power-domains = <&rpmhpd SA8775P_CX>;
2151 dma-names = "tx",
2157 compatible = "qcom,geni-spi";
2159 #address-cells = <1>;
2160 #size-cells = <0>;
2162 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
2163 clock-names = "se";
2164 pinctrl-0 = <&qup_spi7_default>;
2165 pinctrl-names = "default";
2172 interconnect-names = "qup-core",
2173 "qup-config",
2174 "qup-memory";
2175 power-domains = <&rpmhpd SA8775P_CX>;
2178 dma-names = "tx",
2184 compatible = "qcom,geni-uart";
2187 clock-names = "se";
2188 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
2189 pinctrl-0 = <&qup_uart7_default>;
2190 pinctrl-names = "default";
2191 interconnect-names = "qup-core", "qup-config";
2196 power-domains = <&rpmhpd SA8775P_CX>;
2197 operating-points-v2 = <&qup_opp_table_100mhz>;
2202 compatible = "qcom,geni-i2c";
2204 #address-cells = <1>;
2205 #size-cells = <0>;
2207 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
2208 clock-names = "se";
2209 pinctrl-0 = <&qup_i2c8_default>;
2210 pinctrl-names = "default";
2217 interconnect-names = "qup-core",
2218 "qup-config",
2219 "qup-memory";
2220 power-domains = <&rpmhpd SA8775P_CX>;
2223 dma-names = "tx",
2229 compatible = "qcom,geni-spi";
2231 #address-cells = <1>;
2232 #size-cells = <0>;
2234 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
2235 clock-names = "se";
2236 pinctrl-0 = <&qup_spi8_default>;
2237 pinctrl-names = "default";
2244 interconnect-names = "qup-core",
2245 "qup-config",
2246 "qup-memory";
2247 power-domains = <&rpmhpd SA8775P_CX>;
2250 dma-names = "tx",
2256 compatible = "qcom,geni-uart";
2259 clock-names = "se";
2260 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
2261 pinctrl-0 = <&qup_uart8_default>;
2262 pinctrl-names = "default";
2263 interconnect-names = "qup-core", "qup-config";
2268 power-domains = <&rpmhpd SA8775P_CX>;
2269 operating-points-v2 = <&qup_opp_table_100mhz>;
2274 compatible = "qcom,geni-i2c";
2276 #address-cells = <1>;
2277 #size-cells = <0>;
2279 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
2280 clock-names = "se";
2281 pinctrl-0 = <&qup_i2c9_default>;
2282 pinctrl-names = "default";
2289 interconnect-names = "qup-core",
2290 "qup-config",
2291 "qup-memory";
2292 power-domains = <&rpmhpd SA8775P_CX>;
2295 dma-names = "tx",
2301 compatible = "qcom,geni-spi";
2303 #address-cells = <1>;
2304 #size-cells = <0>;
2306 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
2307 clock-names = "se";
2308 pinctrl-0 = <&qup_spi9_default>;
2309 pinctrl-names = "default";
2316 interconnect-names = "qup-core",
2317 "qup-config",
2318 "qup-memory";
2319 power-domains = <&rpmhpd SA8775P_CX>;
2322 dma-names = "tx",
2328 compatible = "qcom,geni-uart";
2331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
2332 clock-names = "se";
2333 pinctrl-0 = <&qup_uart9_default>;
2334 pinctrl-names = "default";
2339 interconnect-names = "qup-core", "qup-config";
2340 power-domains = <&rpmhpd SA8775P_CX>;
2345 compatible = "qcom,geni-i2c";
2347 #address-cells = <1>;
2348 #size-cells = <0>;
2350 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
2351 clock-names = "se";
2352 pinctrl-0 = <&qup_i2c10_default>;
2353 pinctrl-names = "default";
2360 interconnect-names = "qup-core",
2361 "qup-config",
2362 "qup-memory";
2363 power-domains = <&rpmhpd SA8775P_CX>;
2366 dma-names = "tx",
2372 compatible = "qcom,geni-spi";
2374 #address-cells = <1>;
2375 #size-cells = <0>;
2377 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
2378 clock-names = "se";
2379 pinctrl-0 = <&qup_spi10_default>;
2380 pinctrl-names = "default";
2387 interconnect-names = "qup-core",
2388 "qup-config",
2389 "qup-memory";
2390 power-domains = <&rpmhpd SA8775P_CX>;
2393 dma-names = "tx",
2399 compatible = "qcom,geni-uart";
2402 clock-names = "se";
2403 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
2404 pinctrl-0 = <&qup_uart10_default>;
2405 pinctrl-names = "default";
2406 interconnect-names = "qup-core", "qup-config";
2411 power-domains = <&rpmhpd SA8775P_CX>;
2412 operating-points-v2 = <&qup_opp_table_100mhz>;
2417 compatible = "qcom,geni-i2c";
2419 #address-cells = <1>;
2420 #size-cells = <0>;
2422 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2423 clock-names = "se";
2424 pinctrl-0 = <&qup_i2c11_default>;
2425 pinctrl-names = "default";
2432 interconnect-names = "qup-core",
2433 "qup-config",
2434 "qup-memory";
2435 power-domains = <&rpmhpd SA8775P_CX>;
2438 dma-names = "tx",
2444 compatible = "qcom,geni-spi";
2446 #address-cells = <1>;
2447 #size-cells = <0>;
2449 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2450 clock-names = "se";
2451 pinctrl-0 = <&qup_spi11_default>;
2452 pinctrl-names = "default";
2459 interconnect-names = "qup-core",
2460 "qup-config",
2461 "qup-memory";
2462 power-domains = <&rpmhpd SA8775P_CX>;
2465 dma-names = "tx",
2471 compatible = "qcom,geni-uart";
2474 clock-names = "se";
2475 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2476 pinctrl-0 = <&qup_uart11_default>;
2477 pinctrl-names = "default";
2478 interconnect-names = "qup-core", "qup-config";
2483 power-domains = <&rpmhpd SA8775P_CX>;
2484 operating-points-v2 = <&qup_opp_table_100mhz>;
2489 compatible = "qcom,geni-i2c";
2491 #address-cells = <1>;
2492 #size-cells = <0>;
2494 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2495 clock-names = "se";
2496 pinctrl-0 = <&qup_i2c12_default>;
2497 pinctrl-names = "default";
2504 interconnect-names = "qup-core",
2505 "qup-config",
2506 "qup-memory";
2507 power-domains = <&rpmhpd SA8775P_CX>;
2510 dma-names = "tx",
2516 compatible = "qcom,geni-spi";
2518 #address-cells = <1>;
2519 #size-cells = <0>;
2521 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2522 clock-names = "se";
2523 pinctrl-0 = <&qup_spi12_default>;
2524 pinctrl-names = "default";
2531 interconnect-names = "qup-core",
2532 "qup-config",
2533 "qup-memory";
2534 power-domains = <&rpmhpd SA8775P_CX>;
2537 dma-names = "tx",
2543 compatible = "qcom,geni-uart";
2546 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2547 clock-names = "se";
2548 pinctrl-0 = <&qup_uart12_default>;
2549 pinctrl-names = "default";
2554 interconnect-names = "qup-core", "qup-config";
2555 power-domains = <&rpmhpd SA8775P_CX>;
2560 compatible = "qcom,geni-i2c";
2562 #address-cells = <1>;
2563 #size-cells = <0>;
2565 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2566 clock-names = "se";
2567 pinctrl-0 = <&qup_i2c13_default>;
2568 pinctrl-names = "default";
2575 interconnect-names = "qup-core",
2576 "qup-config",
2577 "qup-memory";
2578 power-domains = <&rpmhpd SA8775P_CX>;
2581 dma-names = "tx",
2588 gpi_dma3: dma-controller@b00000 {
2589 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
2591 #dma-cells = <3>;
2597 dma-channels = <4>;
2598 dma-channel-mask = <0xf>;
2603 compatible = "qcom,geni-se-qup";
2605 #address-cells = <2>;
2606 #size-cells = <2>;
2608 clock-names = "m-ahb", "s-ahb";
2609 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
2610 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
2615 compatible = "qcom,geni-i2c";
2617 #address-cells = <1>;
2618 #size-cells = <0>;
2620 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
2621 clock-names = "se";
2622 pinctrl-0 = <&qup_i2c21_default>;
2623 pinctrl-names = "default";
2630 interconnect-names = "qup-core",
2631 "qup-config",
2632 "qup-memory";
2633 power-domains = <&rpmhpd SA8775P_CX>;
2636 dma-names = "tx",
2642 compatible = "qcom,geni-spi";
2644 #address-cells = <1>;
2645 #size-cells = <0>;
2647 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
2648 clock-names = "se";
2649 pinctrl-0 = <&qup_spi21_default>;
2650 pinctrl-names = "default";
2657 interconnect-names = "qup-core",
2658 "qup-config",
2659 "qup-memory";
2660 power-domains = <&rpmhpd SA8775P_CX>;
2663 dma-names = "tx",
2669 compatible = "qcom,geni-uart";
2672 clock-names = "se";
2673 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
2674 interconnect-names = "qup-core", "qup-config";
2675 pinctrl-0 = <&qup_uart21_default>;
2676 pinctrl-names = "default";
2681 power-domains = <&rpmhpd SA8775P_CX>;
2682 operating-points-v2 = <&qup_opp_table_100mhz>;
2688 compatible = "qcom,sa8775p-trng", "qcom,trng";
2693 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2697 phy-names = "ufsphy";
2698 lanes-per-direction = <2>;
2699 #reset-cells = <1>;
2700 resets = <&gcc GCC_UFS_PHY_BCR>;
2701 reset-names = "rst";
2702 power-domains = <&gcc UFS_PHY_GDSC>;
2703 required-opps = <&rpmhpd_opp_nom>;
2705 dma-coherent;
2706 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2707 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2708 <&gcc GCC_UFS_PHY_AHB_CLK>,
2709 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2711 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2712 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2713 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2714 clock-names = "core_clk",
2722 freq-table-hz = <75000000 300000000>,
2735 compatible = "qcom,sa8775p-qmp-ufs-phy";
2742 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2743 <&gcc GCC_EDP_REF_CLKREF_EN>;
2744 clock-names = "ref", "ref_aux", "qref";
2745 power-domains = <&gcc UFS_PHY_GDSC>;
2747 reset-names = "ufsphy";
2748 #phy-cells = <0>;
2753 compatible = "qcom,sa8775p-inline-crypto-engine",
2754 "qcom,inline-crypto-engine";
2756 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2759 cryptobam: dma-controller@1dc4000 {
2760 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2763 #dma-cells = <1>;
2765 qcom,num-ees = <4>;
2766 num-channels = <20>;
2767 qcom,controlled-remotely;
2773 compatible = "qcom,sa8775p-ctcu";
2777 clock-names = "apb";
2779 in-ports {
2780 #address-cells = <1>;
2781 #size-cells = <0>;
2787 remote-endpoint = <&etr0_out>;
2795 remote-endpoint = <&etr1_out>;
2802 compatible = "arm,coresight-stm", "arm,primecell";
2805 reg-names = "stm-base", "stm-stimulus-base";
2808 clock-names = "apb_pclk";
2810 out-ports {
2813 remote-endpoint =
2821 compatible = "qcom,coresight-tpdm", "arm,primecell";
2825 clock-names = "apb_pclk";
2827 qcom,cmb-element-bits = <32>;
2828 qcom,cmb-msrs-num = <32>;
2831 out-ports {
2834 remote-endpoint =
2842 compatible = "qcom,coresight-tpda", "arm,primecell";
2846 clock-names = "apb_pclk";
2848 out-ports {
2851 remote-endpoint =
2857 in-ports {
2858 #address-cells = <1>;
2859 #size-cells = <0>;
2864 remote-endpoint =
2872 remote-endpoint =
2880 compatible = "qcom,coresight-tpdm", "arm,primecell";
2884 clock-names = "apb_pclk";
2886 qcom,cmb-element-bits = <32>;
2887 qcom,cmb-msrs-num = <32>;
2889 out-ports {
2892 remote-endpoint =
2900 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2904 clock-names = "apb_pclk";
2906 out-ports {
2909 remote-endpoint =
2915 in-ports {
2916 #address-cells = <1>;
2917 #size-cells = <0>;
2922 remote-endpoint =
2930 remote-endpoint =
2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2942 clock-names = "apb_pclk";
2944 out-ports {
2947 remote-endpoint =
2953 in-ports {
2954 #address-cells = <1>;
2955 #size-cells = <0>;
2960 remote-endpoint =
2968 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2972 clock-names = "apb_pclk";
2974 out-ports {
2977 remote-endpoint =
2983 in-ports {
2984 #address-cells = <1>;
2985 #size-cells = <0>;
2990 remote-endpoint =
2998 remote-endpoint =
3006 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3010 clock-names = "apb_pclk";
3012 in-ports {
3015 remote-endpoint = <&swao_rep_out0>;
3020 out-ports {
3023 remote-endpoint = <&etr_rep_in>;
3030 compatible = "arm,coresight-tmc", "arm,primecell";
3034 clock-names = "apb_pclk";
3037 arm,scatter-gather;
3039 in-ports {
3042 remote-endpoint = <&etr_rep_out0>;
3047 out-ports {
3050 remote-endpoint = <&ctcu_in0>;
3057 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3061 clock-names = "apb_pclk";
3063 in-ports {
3066 remote-endpoint = <&qdss_rep_out0>;
3071 out-ports {
3072 #address-cells = <1>;
3073 #size-cells = <0>;
3079 remote-endpoint = <&etr0_in>;
3087 remote-endpoint = <&etr1_in>;
3094 compatible = "arm,coresight-tmc", "arm,primecell";
3098 clock-names = "apb_pclk";
3101 arm,scatter-gather;
3102 arm,buffer-size = <0x400000>;
3104 in-ports {
3107 remote-endpoint = <&etr_rep_out1>;
3112 out-ports {
3115 remote-endpoint = <&ctcu_in1>;
3122 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3126 clock-names = "apb_pclk";
3128 out-ports {
3131 remote-endpoint =
3137 in-ports {
3138 #address-cells = <1>;
3139 #size-cells = <0>;
3144 remote-endpoint =
3152 remote-endpoint =
3160 compatible = "arm,coresight-tmc", "arm,primecell";
3164 clock-names = "apb_pclk";
3166 out-ports {
3169 remote-endpoint =
3175 in-ports {
3178 remote-endpoint =
3186 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3190 clock-names = "apb_pclk";
3192 out-ports {
3193 #address-cells = <1>;
3194 #size-cells = <0>;
3200 remote-endpoint = <&qdss_rep_in>;
3207 remote-endpoint =
3213 in-ports {
3216 remote-endpoint =
3224 compatible = "qcom,coresight-tpda", "arm,primecell";
3228 clock-names = "apb_pclk";
3230 out-ports {
3233 remote-endpoint =
3239 in-ports {
3240 #address-cells = <1>;
3241 #size-cells = <0>;
3246 remote-endpoint =
3254 remote-endpoint =
3262 remote-endpoint =
3270 remote-endpoint =
3278 remote-endpoint =
3286 compatible = "qcom,coresight-tpdm", "arm,primecell";
3290 clock-names = "apb_pclk";
3292 qcom,cmb-element-bits = <64>;
3293 qcom,cmb-msrs-num = <32>;
3295 out-ports {
3298 remote-endpoint =
3306 compatible = "qcom,coresight-tpdm", "arm,primecell";
3310 clock-names = "apb_pclk";
3312 qcom,cmb-element-bits = <64>;
3313 qcom,cmb-msrs-num = <32>;
3315 out-ports {
3318 remote-endpoint =
3326 compatible = "qcom,coresight-tpdm", "arm,primecell";
3330 clock-names = "apb_pclk";
3332 qcom,cmb-element-bits = <64>;
3333 qcom,cmb-msrs-num = <32>;
3335 out-ports {
3338 remote-endpoint =
3346 compatible = "qcom,coresight-tpdm", "arm,primecell";
3350 clock-names = "apb_pclk";
3352 qcom,cmb-element-bits = <64>;
3353 qcom,cmb-msrs-num = <32>;
3355 out-ports {
3358 remote-endpoint =
3366 compatible = "qcom,coresight-tpdm", "arm,primecell";
3370 clock-names = "apb_pclk";
3372 qcom,dsb-element-bits = <32>;
3373 qcom,dsb-msrs-num = <32>;
3375 out-ports {
3378 remote-endpoint =
3386 compatible = "arm,coresight-cti", "arm,primecell";
3390 clock-names = "apb_pclk";
3399 clock-names = "apb_pclk";
3400 arm,coresight-loses-context-with-cpu;
3401 qcom,skip-power-up;
3403 out-ports {
3406 remote-endpoint =
3419 clock-names = "apb_pclk";
3420 arm,coresight-loses-context-with-cpu;
3421 qcom,skip-power-up;
3423 out-ports {
3426 remote-endpoint =
3439 clock-names = "apb_pclk";
3440 arm,coresight-loses-context-with-cpu;
3441 qcom,skip-power-up;
3443 out-ports {
3446 remote-endpoint =
3459 clock-names = "apb_pclk";
3460 arm,coresight-loses-context-with-cpu;
3461 qcom,skip-power-up;
3463 out-ports {
3466 remote-endpoint =
3479 clock-names = "apb_pclk";
3480 arm,coresight-loses-context-with-cpu;
3481 qcom,skip-power-up;
3483 out-ports {
3486 remote-endpoint =
3499 clock-names = "apb_pclk";
3500 arm,coresight-loses-context-with-cpu;
3501 qcom,skip-power-up;
3503 out-ports {
3506 remote-endpoint =
3519 clock-names = "apb_pclk";
3520 arm,coresight-loses-context-with-cpu;
3521 qcom,skip-power-up;
3523 out-ports {
3526 remote-endpoint =
3539 clock-names = "apb_pclk";
3540 arm,coresight-loses-context-with-cpu;
3541 qcom,skip-power-up;
3543 out-ports {
3546 remote-endpoint =
3554 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3558 clock-names = "apb_pclk";
3560 out-ports {
3563 remote-endpoint =
3569 in-ports {
3570 #address-cells = <1>;
3571 #size-cells = <0>;
3576 remote-endpoint =
3584 remote-endpoint =
3592 remote-endpoint =
3600 remote-endpoint =
3608 remote-endpoint =
3616 remote-endpoint =
3624 remote-endpoint =
3632 remote-endpoint =
3640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3644 clock-names = "apb_pclk";
3646 out-ports {
3649 remote-endpoint =
3655 in-ports {
3656 #address-cells = <1>;
3657 #size-cells = <0>;
3662 remote-endpoint =
3670 remote-endpoint =
3678 compatible = "qcom,coresight-tpdm", "arm,primecell";
3682 clock-names = "apb_pclk";
3684 qcom,cmb-element-bits = <64>;
3685 qcom,cmb-msrs-num = <32>;
3687 out-ports {
3690 remote-endpoint =
3698 compatible = "qcom,coresight-tpdm", "arm,primecell";
3702 clock-names = "apb_pclk";
3704 qcom,dsb-element-bits = <32>;
3705 qcom,dsb-msrs-num = <32>;
3707 out-ports {
3710 remote-endpoint =
3718 compatible = "qcom,coresight-tpda", "arm,primecell";
3722 clock-names = "apb_pclk";
3724 out-ports {
3727 remote-endpoint =
3733 in-ports {
3734 #address-cells = <1>;
3735 #size-cells = <0>;
3740 remote-endpoint =
3748 remote-endpoint =
3756 remote-endpoint =
3764 remote-endpoint =
3772 remote-endpoint =
3780 compatible = "qcom,coresight-tpdm", "arm,primecell";
3784 clock-names = "apb_pclk";
3786 qcom,cmb-element-bits = <32>;
3787 qcom,cmb-msrs-num = <32>;
3789 out-ports {
3792 remote-endpoint =
3800 compatible = "qcom,coresight-tpdm", "arm,primecell";
3804 clock-names = "apb_pclk";
3806 qcom,cmb-element-bits = <32>;
3807 qcom,cmb-msrs-num = <32>;
3809 out-ports {
3812 remote-endpoint =
3820 compatible = "qcom,coresight-tpdm", "arm,primecell";
3824 clock-names = "apb_pclk";
3826 qcom,dsb-element-bits = <32>;
3827 qcom,dsb-msrs-num = <32>;
3829 out-ports {
3832 remote-endpoint =
3840 compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5";
3845 interrupt-names = "hc_irq",
3848 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3849 <&gcc GCC_SDCC1_APPS_CLK>;
3850 clock-names = "iface",
3857 interconnect-names = "sdhc-ddr",
3858 "cpu-sdhc";
3861 dma-coherent;
3863 operating-points-v2 = <&sdhc_opp_table>;
3864 power-domains = <&rpmhpd SA8775P_CX>;
3865 resets = <&gcc GCC_SDCC1_BCR>;
3867 qcom,dll-config = <0x0007642c>;
3868 qcom,ddr-config = <0x80040868>;
3872 sdhc_opp_table: opp-table {
3873 compatible = "operating-points-v2";
3875 opp-100000000 {
3876 opp-hz = /bits/ 64 <100000000>;
3877 required-opps = <&rpmhpd_opp_low_svs>;
3878 opp-peak-kBps = <1800000 400000>;
3879 opp-avg-kBps = <100000 0>;
3882 opp-384000000 {
3883 opp-hz = /bits/ 64 <384000000>;
3884 required-opps = <&rpmhpd_opp_nom>;
3885 opp-peak-kBps = <5400000 1600000>;
3886 opp-avg-kBps = <390000 0>;
3892 compatible = "qcom,sa8775p-usb-hs-phy",
3893 "qcom,usb-snps-hs-5nm-phy";
3896 clock-names = "ref";
3897 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
3899 #phy-cells = <0>;
3905 compatible = "qcom,sa8775p-usb-hs-phy",
3906 "qcom,usb-snps-hs-5nm-phy";
3908 clocks = <&gcc GCC_USB_CLKREF_EN>;
3909 clock-names = "ref";
3910 resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
3912 #phy-cells = <0>;
3918 compatible = "qcom,sa8775p-usb-hs-phy",
3919 "qcom,usb-snps-hs-5nm-phy";
3921 clocks = <&gcc GCC_USB_CLKREF_EN>;
3922 clock-names = "ref";
3923 resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
3925 #phy-cells = <0>;
3931 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
3934 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3935 <&gcc GCC_USB_CLKREF_EN>,
3936 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3937 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3938 clock-names = "aux", "ref", "com_aux", "pipe";
3940 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3941 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
3942 reset-names = "phy", "phy_phy";
3944 power-domains = <&gcc USB30_PRIM_GDSC>;
3946 #clock-cells = <0>;
3947 clock-output-names = "usb3_prim_phy_pipe_clk_src";
3949 #phy-cells = <0>;
3955 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
3958 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3959 <&gcc GCC_USB_CLKREF_EN>,
3960 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3961 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3962 clock-names = "aux", "ref", "com_aux", "pipe";
3964 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3965 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3966 reset-names = "phy", "phy_phy";
3968 power-domains = <&gcc USB30_SEC_GDSC>;
3970 #clock-cells = <0>;
3971 clock-output-names = "usb3_sec_phy_pipe_clk_src";
3973 #phy-cells = <0>;
3979 compatible = "qcom,sa8775p-refgen-regulator",
3980 "qcom,sm8250-refgen-regulator";
3985 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
3988 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3989 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3990 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3991 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3992 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3993 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
3995 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3996 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3997 assigned-clock-rates = <19200000>, <200000000>;
3999 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
4005 interrupt-names = "dwc_usb3",
4012 power-domains = <&gcc USB30_PRIM_GDSC>;
4013 required-opps = <&rpmhpd_opp_nom>;
4015 resets = <&gcc GCC_USB30_PRIM_BCR>;
4019 interconnect-names = "usb-ddr", "apps-usb";
4021 wakeup-source;
4025 phy-names = "usb2-phy", "usb3-phy";
4026 snps,dis-u1-entry-quirk;
4027 snps,dis-u2-entry-quirk;
4033 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
4036 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4037 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4038 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4039 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4040 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4041 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
4043 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4044 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4045 assigned-clock-rates = <19200000>, <200000000>;
4047 interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
4053 interrupt-names = "dwc_usb3",
4060 power-domains = <&gcc USB30_SEC_GDSC>;
4061 required-opps = <&rpmhpd_opp_nom>;
4063 resets = <&gcc GCC_USB30_SEC_BCR>;
4067 interconnect-names = "usb-ddr", "apps-usb";
4069 wakeup-source;
4073 phy-names = "usb2-phy", "usb3-phy";
4074 snps,dis-u1-entry-quirk;
4075 snps,dis-u2-entry-quirk;
4081 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
4084 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
4085 <&gcc GCC_USB20_MASTER_CLK>,
4086 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
4087 <&gcc GCC_USB20_SLEEP_CLK>,
4088 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
4089 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
4091 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4092 <&gcc GCC_USB20_MASTER_CLK>;
4093 assigned-clock-rates = <19200000>, <200000000>;
4095 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
4100 interrupt-names = "dwc_usb3",
4106 power-domains = <&gcc USB20_PRIM_GDSC>;
4107 required-opps = <&rpmhpd_opp_nom>;
4109 resets = <&gcc GCC_USB20_PRIM_BCR>;
4113 interconnect-names = "usb-ddr", "apps-usb";
4115 qcom,select-utmi-as-pipe-clk;
4116 wakeup-source;
4120 phy-names = "usb2-phy";
4121 snps,dis-u1-entry-quirk;
4122 snps,dis-u2-entry-quirk;
4128 compatible = "qcom,tcsr-mutex";
4130 #hwlock-cells = <1>;
4134 compatible = "qcom,sa8775p-tcsr", "syscon";
4138 gpucc: clock-controller@3d90000 {
4139 compatible = "qcom,sa8775p-gpucc";
4142 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
4143 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
4144 clock-names = "bi_tcxo",
4147 #clock-cells = <1>;
4148 #reset-cells = <1>;
4149 #power-domain-cells = <1>;
4153 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
4154 "qcom,smmu-500", "arm,mmu-500";
4156 #iommu-cells = <2>;
4157 #global-interrupts = <2>;
4158 dma-coherent;
4159 power-domains = <&gpucc GPU_CC_CX_GDSC>;
4160 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4161 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
4167 clock-names = "gcc_gpu_memnoc_gfx_clk",
4189 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
4191 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
4192 clock-names = "sgmi_ref";
4193 #phy-cells = <0>;
4198 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
4200 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
4201 clock-names = "sgmi_ref";
4202 #phy-cells = <0>;
4207 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4213 operating-points-v2 = <&llcc_bwmon_opp_table>;
4215 llcc_bwmon_opp_table: opp-table {
4216 compatible = "operating-points-v2";
4218 opp-0 {
4219 opp-peak-kBps = <762000>;
4222 opp-1 {
4223 opp-peak-kBps = <1720000>;
4226 opp-2 {
4227 opp-peak-kBps = <2086000>;
4230 opp-3 {
4231 opp-peak-kBps = <2601000>;
4234 opp-4 {
4235 opp-peak-kBps = <2929000>;
4238 opp-5 {
4239 opp-peak-kBps = <5931000>;
4242 opp-6 {
4243 opp-peak-kBps = <6515000>;
4246 opp-7 {
4247 opp-peak-kBps = <7984000>;
4250 opp-8 {
4251 opp-peak-kBps = <10437000>;
4254 opp-9 {
4255 opp-peak-kBps = <12195000>;
4261 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
4267 operating-points-v2 = <&cpu_bwmon_opp_table>;
4269 cpu_bwmon_opp_table: opp-table {
4270 compatible = "operating-points-v2";
4272 opp-0 {
4273 opp-peak-kBps = <9155000>;
4276 opp-1 {
4277 opp-peak-kBps = <12298000>;
4280 opp-2 {
4281 opp-peak-kBps = <14236000>;
4284 opp-3 {
4285 opp-peak-kBps = <16265000>;
4292 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
4298 operating-points-v2 = <&cpu_bwmon_opp_table>;
4301 llcc: system-cache-controller@9200000 {
4302 compatible = "qcom,sa8775p-llcc";
4310 reg-names = "llcc0_base",
4320 iris: video-codec@aa00000 {
4321 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris";
4326 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
4330 power-domain-names = "venus",
4334 operating-points-v2 = <&iris_opp_table>;
4336 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4339 clock-names = "iface",
4347 interconnect-names = "cpu-cfg",
4348 "video-mem";
4350 memory-region = <&pil_video_mem>;
4352 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
4353 reset-names = "bus";
4357 dma-coherent;
4361 iris_opp_table: opp-table {
4362 compatible = "operating-points-v2";
4364 opp-366000000 {
4365 opp-hz = /bits/ 64 <366000000>;
4366 required-opps = <&rpmhpd_opp_svs_l1>,
4370 opp-444000000 {
4371 opp-hz = /bits/ 64 <444000000>;
4372 required-opps = <&rpmhpd_opp_nom>,
4376 opp-533000000 {
4377 opp-hz = /bits/ 64 <533000000>;
4378 required-opps = <&rpmhpd_opp_turbo>,
4382 opp-560000000 {
4383 opp-hz = /bits/ 64 <560000000>;
4384 required-opps = <&rpmhpd_opp_turbo_l1>,
4390 videocc: clock-controller@abf0000 {
4391 compatible = "qcom,sa8775p-videocc";
4393 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4397 power-domains = <&rpmhpd SA8775P_MMCX>;
4398 #clock-cells = <1>;
4399 #reset-cells = <1>;
4400 #power-domain-cells = <1>;
4404 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
4409 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4414 clock-names = "camnoc_axi",
4418 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
4419 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
4420 pinctrl-names = "default", "sleep";
4422 #address-cells = <1>;
4423 #size-cells = <0>;
4427 cci0_i2c0: i2c-bus@0 {
4429 clock-frequency = <1000000>;
4430 #address-cells = <1>;
4431 #size-cells = <0>;
4434 cci0_i2c1: i2c-bus@1 {
4436 clock-frequency = <1000000>;
4437 #address-cells = <1>;
4438 #size-cells = <0>;
4443 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
4448 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4453 clock-names = "camnoc_axi",
4457 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
4458 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
4459 pinctrl-names = "default", "sleep";
4461 #address-cells = <1>;
4462 #size-cells = <0>;
4466 cci1_i2c0: i2c-bus@0 {
4468 clock-frequency = <1000000>;
4469 #address-cells = <1>;
4470 #size-cells = <0>;
4473 cci1_i2c1: i2c-bus@1 {
4475 clock-frequency = <1000000>;
4476 #address-cells = <1>;
4477 #size-cells = <0>;
4482 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
4487 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4492 clock-names = "camnoc_axi",
4496 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
4497 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
4498 pinctrl-names = "default", "sleep";
4500 #address-cells = <1>;
4501 #size-cells = <0>;
4505 cci2_i2c0: i2c-bus@0 {
4507 clock-frequency = <1000000>;
4508 #address-cells = <1>;
4509 #size-cells = <0>;
4512 cci2_i2c1: i2c-bus@1 {
4514 clock-frequency = <1000000>;
4515 #address-cells = <1>;
4516 #size-cells = <0>;
4521 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
4526 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4531 clock-names = "camnoc_axi",
4535 pinctrl-0 = <&cci3_0_default &cci3_1_default>;
4536 pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>;
4537 pinctrl-names = "default", "sleep";
4539 #address-cells = <1>;
4540 #size-cells = <0>;
4544 cci3_i2c0: i2c-bus@0 {
4546 clock-frequency = <1000000>;
4547 #address-cells = <1>;
4548 #size-cells = <0>;
4551 cci3_i2c1: i2c-bus@1 {
4553 clock-frequency = <1000000>;
4554 #address-cells = <1>;
4555 #size-cells = <0>;
4560 compatible = "qcom,sa8775p-camss";
4584 reg-names = "csid_wrapper",
4624 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4625 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4635 clock-names = "camnoc_axi",
4685 interrupt-names = "csid0",
4711 interconnect-names = "ahb",
4716 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4717 power-domain-names = "top";
4722 #address-cells = <1>;
4723 #size-cells = <0>;
4743 camcc: clock-controller@ade0000 {
4744 compatible = "qcom,sa8775p-camcc";
4746 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4750 power-domains = <&rpmhpd SA8775P_MMCX>;
4751 #clock-cells = <1>;
4752 #reset-cells = <1>;
4753 #power-domain-cells = <1>;
4756 mdss0: display-subsystem@ae00000 {
4757 compatible = "qcom,sa8775p-mdss";
4759 reg-names = "mdss";
4768 interconnect-names = "mdp0-mem",
4769 "mdp1-mem",
4770 "cpu-cfg";
4774 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
4777 <&gcc GCC_DISP_HF_AXI_CLK>,
4781 interrupt-controller;
4782 #interrupt-cells = <1>;
4786 #address-cells = <2>;
4787 #size-cells = <2>;
4792 mdss0_mdp: display-controller@ae01000 {
4793 compatible = "qcom,sa8775p-dpu";
4796 reg-names = "mdp", "vbif";
4798 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4803 clock-names = "nrt_bus",
4809 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
4810 assigned-clock-rates = <19200000>;
4812 operating-points-v2 = <&mdss0_mdp_opp_table>;
4813 power-domains = <&rpmhpd SA8775P_MMCX>;
4815 interrupt-parent = <&mdss0>;
4819 #address-cells = <1>;
4820 #size-cells = <0>;
4826 remote-endpoint = <&mdss0_dp0_in>;
4834 remote-endpoint = <&mdss0_dp1_in>;
4842 remote-endpoint = <&mdss0_dsi0_in>;
4850 remote-endpoint = <&mdss0_dsi1_in>;
4855 mdss0_mdp_opp_table: opp-table {
4856 compatible = "operating-points-v2";
4858 opp-375000000 {
4859 opp-hz = /bits/ 64 <375000000>;
4860 required-opps = <&rpmhpd_opp_svs_l1>;
4863 opp-500000000 {
4864 opp-hz = /bits/ 64 <500000000>;
4865 required-opps = <&rpmhpd_opp_nom>;
4868 opp-575000000 {
4869 opp-hz = /bits/ 64 <575000000>;
4870 required-opps = <&rpmhpd_opp_turbo>;
4873 opp-650000000 {
4874 opp-hz = /bits/ 64 <650000000>;
4875 required-opps = <&rpmhpd_opp_turbo_l1>;
4881 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4883 reg-names = "dsi_ctrl";
4885 interrupt-parent = <&mdss0>;
4893 <&gcc GCC_DISP_HF_AXI_CLK>;
4894 clock-names = "byte",
4900 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
4902 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
4906 operating-points-v2 = <&mdss_dsi_opp_table>;
4907 power-domains = <&rpmhpd SA8775P_MMCX>;
4909 refgen-supply = <&refgen>;
4911 #address-cells = <1>;
4912 #size-cells = <0>;
4917 #address-cells = <1>;
4918 #size-cells = <0>;
4924 remote-endpoint = <&dpu_intf1_out>;
4935 mdss_dsi_opp_table: opp-table {
4936 compatible = "operating-points-v2";
4938 opp-358000000 {
4939 opp-hz = /bits/ 64 <358000000>;
4940 required-opps = <&rpmhpd_opp_svs_l1>;
4946 compatible = "qcom,sa8775p-dsi-phy-5nm";
4950 reg-names = "dsi_phy",
4954 #clock-cells = <1>;
4955 #phy-cells = <0>;
4959 clock-names = "iface", "ref";
4965 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4967 reg-names = "dsi_ctrl";
4969 interrupt-parent = <&mdss0>;
4977 <&gcc GCC_DISP_HF_AXI_CLK>;
4978 clock-names = "byte",
4984 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>,
4986 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
4990 operating-points-v2 = <&mdss_dsi_opp_table>;
4991 power-domains = <&rpmhpd SA8775P_MMCX>;
4993 refgen-supply = <&refgen>;
4995 #address-cells = <1>;
4996 #size-cells = <0>;
5001 #address-cells = <1>;
5002 #size-cells = <0>;
5008 remote-endpoint = <&dpu_intf2_out>;
5021 compatible = "qcom,sa8775p-dsi-phy-5nm";
5025 reg-names = "dsi_phy",
5029 #clock-cells = <1>;
5030 #phy-cells = <0>;
5034 clock-names = "iface", "ref";
5040 compatible = "qcom,sa8775p-edp-phy";
5049 clock-names = "aux",
5052 #clock-cells = <1>;
5053 #phy-cells = <0>;
5059 compatible = "qcom,sa8775p-edp-phy";
5068 clock-names = "aux",
5071 #clock-cells = <1>;
5072 #phy-cells = <0>;
5077 mdss0_dp0: displayport-controller@af54000 {
5078 compatible = "qcom,sa8775p-dp";
5090 interrupt-parent = <&mdss0>;
5101 clock-names = "core_iface",
5109 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5114 assigned-clock-parents = <&mdss0_dp0_phy 0>,
5120 phy-names = "dp";
5122 operating-points-v2 = <&dp_opp_table>;
5123 power-domains = <&rpmhpd SA8775P_MMCX>;
5125 #sound-dai-cells = <0>;
5130 #address-cells = <1>;
5131 #size-cells = <0>;
5137 remote-endpoint = <&dpu_intf0_out>;
5148 dp_opp_table: opp-table {
5149 compatible = "operating-points-v2";
5151 opp-160000000 {
5152 opp-hz = /bits/ 64 <160000000>;
5153 required-opps = <&rpmhpd_opp_low_svs>;
5156 opp-270000000 {
5157 opp-hz = /bits/ 64 <270000000>;
5158 required-opps = <&rpmhpd_opp_svs>;
5161 opp-540000000 {
5162 opp-hz = /bits/ 64 <540000000>;
5163 required-opps = <&rpmhpd_opp_svs_l1>;
5166 opp-810000000 {
5167 opp-hz = /bits/ 64 <810000000>;
5168 required-opps = <&rpmhpd_opp_nom>;
5173 mdss0_dp1: displayport-controller@af5c000 {
5174 compatible = "qcom,sa8775p-dp";
5186 interrupt-parent = <&mdss0>;
5195 clock-names = "core_iface",
5201 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5204 assigned-clock-parents = <&mdss0_dp1_phy 0>,
5208 phy-names = "dp";
5210 operating-points-v2 = <&dp1_opp_table>;
5211 power-domains = <&rpmhpd SA8775P_MMCX>;
5213 #sound-dai-cells = <0>;
5218 #address-cells = <1>;
5219 #size-cells = <0>;
5225 remote-endpoint = <&dpu_intf4_out>;
5236 dp1_opp_table: opp-table {
5237 compatible = "operating-points-v2";
5239 opp-160000000 {
5240 opp-hz = /bits/ 64 <160000000>;
5241 required-opps = <&rpmhpd_opp_low_svs>;
5244 opp-270000000 {
5245 opp-hz = /bits/ 64 <270000000>;
5246 required-opps = <&rpmhpd_opp_svs>;
5249 opp-540000000 {
5250 opp-hz = /bits/ 64 <540000000>;
5251 required-opps = <&rpmhpd_opp_svs_l1>;
5254 opp-810000000 {
5255 opp-hz = /bits/ 64 <810000000>;
5256 required-opps = <&rpmhpd_opp_nom>;
5262 dispcc0: clock-controller@af00000 {
5263 compatible = "qcom,sa8775p-dispcc0";
5265 clocks = <&gcc GCC_DISP_AHB_CLK>,
5275 power-domains = <&rpmhpd SA8775P_MMCX>;
5276 #clock-cells = <1>;
5277 #reset-cells = <1>;
5278 #power-domain-cells = <1>;
5281 pdc: interrupt-controller@b220000 {
5282 compatible = "qcom,sa8775p-pdc", "qcom,pdc";
5285 qcom,pdc-ranges = <0 480 40>,
5323 #interrupt-cells = <2>;
5324 interrupt-parent = <&intc>;
5325 interrupt-controller;
5328 tsens2: thermal-sensor@c251000 {
5329 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
5335 interrupt-names = "uplow", "critical";
5336 #thermal-sensor-cells = <1>;
5339 tsens3: thermal-sensor@c252000 {
5340 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
5346 interrupt-names = "uplow", "critical";
5347 #thermal-sensor-cells = <1>;
5350 tsens0: thermal-sensor@c263000 {
5351 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
5357 interrupt-names = "uplow", "critical";
5358 #thermal-sensor-cells = <1>;
5361 tsens1: thermal-sensor@c265000 {
5362 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
5368 interrupt-names = "uplow", "critical";
5369 #thermal-sensor-cells = <1>;
5372 aoss_qmp: power-management@c300000 {
5373 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
5375 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5379 #clock-cells = <0>;
5383 compatible = "qcom,rpmh-stats";
5388 compatible = "qcom,spmi-pmic-arb";
5394 reg-names = "core",
5401 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5402 interrupt-names = "periph_irq";
5403 interrupt-controller;
5404 #interrupt-cells = <4>;
5405 #address-cells = <2>;
5406 #size-cells = <0>;
5410 compatible = "qcom,sa8775p-tlmm";
5413 gpio-controller;
5414 #gpio-cells = <2>;
5415 interrupt-controller;
5416 #interrupt-cells = <2>;
5417 gpio-ranges = <&tlmm 0 0 149>;
5418 wakeup-parent = <&pdc>;
5420 dp0_hot_plug_det: dp0-hot-plug-det-state {
5423 bias-disable;
5426 dp1_hot_plug_det: dp1-hot-plug-det-state {
5429 bias-disable;
5432 hs0_mi2s_active: hs0-mi2s-active-state {
5435 drive-strength = <8>;
5436 bias-disable;
5439 hs2_mi2s_active: hs2-mi2s-active-state {
5442 drive-strength = <8>;
5443 bias-disable;
5446 cci0_0_default: cci0-0-default-state {
5449 drive-strength = <2>;
5450 bias-pull-up = <2200>;
5453 cci0_0_sleep: cci0-0-sleep-state {
5456 drive-strength = <2>;
5457 bias-pull-down;
5460 cci0_1_default: cci0-1-default-state {
5463 drive-strength = <2>;
5464 bias-pull-up = <2200>;
5467 cci0_1_sleep: cci0-1-sleep-state {
5470 drive-strength = <2>;
5471 bias-pull-down;
5474 cci1_0_default: cci1-0-default-state {
5477 drive-strength = <2>;
5478 bias-pull-up = <2200>;
5481 cci1_0_sleep: cci1-0-sleep-state {
5484 drive-strength = <2>;
5485 bias-pull-down;
5488 cci1_1_default: cci1-1-default-state {
5491 drive-strength = <2>;
5492 bias-pull-up = <2200>;
5495 cci1_1_sleep: cci1-1-sleep-state {
5498 drive-strength = <2>;
5499 bias-pull-down;
5502 cci2_0_default: cci2-0-default-state {
5505 drive-strength = <2>;
5506 bias-pull-up = <2200>;
5509 cci2_0_sleep: cci2-0-sleep-state {
5512 drive-strength = <2>;
5513 bias-pull-down;
5516 cci2_1_default: cci2-1-default-state {
5519 drive-strength = <2>;
5520 bias-pull-up = <2200>;
5523 cci2_1_sleep: cci2-1-sleep-state {
5526 drive-strength = <2>;
5527 bias-pull-down;
5530 cci3_0_default: cci3-0-default-state {
5533 drive-strength = <2>;
5534 bias-pull-up = <2200>;
5537 cci3_0_sleep: cci3-0-sleep-state {
5540 drive-strength = <2>;
5541 bias-pull-down;
5544 cci3_1_default: cci3-1-default-state {
5547 drive-strength = <2>;
5548 bias-pull-up = <2200>;
5551 cci3_1_sleep: cci3-1-sleep-state {
5554 drive-strength = <2>;
5555 bias-pull-down;
5558 qup_i2c0_default: qup-i2c0-state {
5563 qup_i2c1_default: qup-i2c1-state {
5568 qup_i2c2_default: qup-i2c2-state {
5573 qup_i2c3_default: qup-i2c3-state {
5578 qup_i2c4_default: qup-i2c4-state {
5583 qup_i2c5_default: qup-i2c5-state {
5588 qup_i2c7_default: qup-i2c7-state {
5593 qup_i2c8_default: qup-i2c8-state {
5598 qup_i2c9_default: qup-i2c9-state {
5603 qup_i2c10_default: qup-i2c10-state {
5608 qup_i2c11_default: qup-i2c11-state {
5613 qup_i2c12_default: qup-i2c12-state {
5618 qup_i2c13_default: qup-i2c13-state {
5623 qup_i2c14_default: qup-i2c14-state {
5628 qup_i2c15_default: qup-i2c15-state {
5633 qup_i2c16_default: qup-i2c16-state {
5638 qup_i2c17_default: qup-i2c17-state {
5643 qup_i2c18_default: qup-i2c18-state {
5648 qup_i2c19_default: qup-i2c19-state {
5653 qup_i2c20_default: qup-i2c20-state {
5658 qup_i2c21_default: qup-i2c21-state {
5663 qup_spi0_default: qup-spi0-state {
5668 qup_spi1_default: qup-spi1-state {
5673 qup_spi2_default: qup-spi2-state {
5678 qup_spi3_default: qup-spi3-state {
5683 qup_spi4_default: qup-spi4-state {
5688 qup_spi5_default: qup-spi5-state {
5693 qup_spi7_default: qup-spi7-state {
5698 qup_spi8_default: qup-spi8-state {
5703 qup_spi9_default: qup-spi9-state {
5708 qup_spi10_default: qup-spi10-state {
5713 qup_spi11_default: qup-spi11-state {
5718 qup_spi12_default: qup-spi12-state {
5723 qup_spi14_default: qup-spi14-state {
5728 qup_spi15_default: qup-spi15-state {
5733 qup_spi16_default: qup-spi16-state {
5738 qup_spi17_default: qup-spi17-state {
5743 qup_spi18_default: qup-spi18-state {
5748 qup_spi19_default: qup-spi19-state {
5753 qup_spi20_default: qup-spi20-state {
5758 qup_spi21_default: qup-spi21-state {
5763 qup_uart0_default: qup-uart0-state {
5764 qup_uart0_cts: qup-uart0-cts-pins {
5769 qup_uart0_rts: qup-uart0-rts-pins {
5774 qup_uart0_tx: qup-uart0-tx-pins {
5779 qup_uart0_rx: qup-uart0-rx-pins {
5785 qup_uart1_default: qup-uart1-state {
5786 qup_uart1_cts: qup-uart1-cts-pins {
5791 qup_uart1_rts: qup-uart1-rts-pins {
5796 qup_uart1_tx: qup-uart1-tx-pins {
5801 qup_uart1_rx: qup-uart1-rx-pins {
5807 qup_uart2_default: qup-uart2-state {
5808 qup_uart2_cts: qup-uart2-cts-pins {
5813 qup_uart2_rts: qup-uart2-rts-pins {
5818 qup_uart2_tx: qup-uart2-tx-pins {
5823 qup_uart2_rx: qup-uart2-rx-pins {
5829 qup_uart3_default: qup-uart3-state {
5830 qup_uart3_cts: qup-uart3-cts-pins {
5835 qup_uart3_rts: qup-uart3-rts-pins {
5840 qup_uart3_tx: qup-uart3-tx-pins {
5845 qup_uart3_rx: qup-uart3-rx-pins {
5851 qup_uart4_default: qup-uart4-state {
5852 qup_uart4_cts: qup-uart4-cts-pins {
5857 qup_uart4_rts: qup-uart4-rts-pins {
5862 qup_uart4_tx: qup-uart4-tx-pins {
5867 qup_uart4_rx: qup-uart4-rx-pins {
5873 qup_uart5_default: qup-uart5-state {
5874 qup_uart5_cts: qup-uart5-cts-pins {
5879 qup_uart5_rts: qup-uart5-rts-pins {
5884 qup_uart5_tx: qup-uart5-tx-pins {
5889 qup_uart5_rx: qup-uart5-rx-pins {
5895 qup_uart7_default: qup-uart7-state {
5896 qup_uart7_cts: qup-uart7-cts-pins {
5901 qup_uart7_rts: qup-uart7-rts-pins {
5906 qup_uart7_tx: qup-uart7-tx-pins {
5911 qup_uart7_rx: qup-uart7-rx-pins {
5917 qup_uart8_default: qup-uart8-state {
5918 qup_uart8_cts: qup-uart8-cts-pins {
5923 qup_uart8_rts: qup-uart8-rts-pins {
5928 qup_uart8_tx: qup-uart8-tx-pins {
5933 qup_uart8_rx: qup-uart8-rx-pins {
5939 qup_uart9_default: qup-uart9-state {
5940 qup_uart9_cts: qup-uart9-cts-pins {
5945 qup_uart9_rts: qup-uart9-rts-pins {
5950 qup_uart9_tx: qup-uart9-tx-pins {
5955 qup_uart9_rx: qup-uart9-rx-pins {
5961 qup_uart10_default: qup-uart10-state {
5966 qup_uart11_default: qup-uart11-state {
5967 qup_uart11_cts: qup-uart11-cts-pins {
5972 qup_uart11_rts: qup-uart11-rts-pins {
5977 qup_uart11_tx: qup-uart11-tx-pins {
5982 qup_uart11_rx: qup-uart11-rx-pins {
5988 qup_uart12_default: qup-uart12-state {
5989 qup_uart12_cts: qup-uart12-cts-pins {
5994 qup_uart12_rts: qup-uart12-rts-pins {
5999 qup_uart12_tx: qup-uart12-tx-pins {
6004 qup_uart12_rx: qup-uart12-rx-pins {
6010 qup_uart14_default: qup-uart14-state {
6011 qup_uart14_cts: qup-uart14-cts-pins {
6016 qup_uart14_rts: qup-uart14-rts-pins {
6021 qup_uart14_tx: qup-uart14-tx-pins {
6026 qup_uart14_rx: qup-uart14-rx-pins {
6032 qup_uart15_default: qup-uart15-state {
6033 qup_uart15_cts: qup-uart15-cts-pins {
6038 qup_uart15_rts: qup-uart15-rts-pins {
6043 qup_uart15_tx: qup-uart15-tx-pins {
6048 qup_uart15_rx: qup-uart15-rx-pins {
6054 qup_uart16_default: qup-uart16-state {
6055 qup_uart16_cts: qup-uart16-cts-pins {
6060 qup_uart16_rts: qup-uart16-rts-pins {
6065 qup_uart16_tx: qup-uart16-tx-pins {
6070 qup_uart16_rx: qup-uart16-rx-pins {
6076 qup_uart17_default: qup-uart17-state {
6077 qup_uart17_cts: qup-uart17-cts-pins {
6082 qup_uart17_rts: qup0-uart17-rts-pins {
6087 qup_uart17_tx: qup0-uart17-tx-pins {
6092 qup_uart17_rx: qup0-uart17-rx-pins {
6098 qup_uart18_default: qup-uart18-state {
6099 qup_uart18_cts: qup-uart18-cts-pins {
6104 qup_uart18_rts: qup-uart18-rts-pins {
6109 qup_uart18_tx: qup-uart18-tx-pins {
6114 qup_uart18_rx: qup-uart18-rx-pins {
6120 qup_uart19_default: qup-uart19-state {
6121 qup_uart19_cts: qup-uart19-cts-pins {
6126 qup_uart19_rts: qup-uart19-rts-pins {
6131 qup_uart19_tx: qup-uart19-tx-pins {
6136 qup_uart19_rx: qup-uart19-rx-pins {
6142 qup_uart20_default: qup-uart20-state {
6143 qup_uart20_cts: qup-uart20-cts-pins {
6148 qup_uart20_rts: qup-uart20-rts-pins {
6153 qup_uart20_tx: qup-uart20-tx-pins {
6158 qup_uart20_rx: qup-uart20-rx-pins {
6164 qup_uart21_default: qup-uart21-state {
6165 qup_uart21_cts: qup-uart21-cts-pins {
6170 qup_uart21_rts: qup-uart21-rts-pins {
6175 qup_uart21_tx: qup-uart21-tx-pins {
6180 qup_uart21_rx: qup-uart21-rx-pins {
6186 sdc_default: sdc-default-state {
6187 clk-pins {
6189 drive-strength = <16>;
6190 bias-disable;
6193 cmd-pins {
6195 drive-strength = <10>;
6196 bias-pull-up;
6199 data-pins {
6201 drive-strength = <10>;
6202 bias-pull-up;
6206 sdc_sleep: sdc-sleep-state {
6207 clk-pins {
6209 drive-strength = <2>;
6210 bias-bus-hold;
6213 cmd-pins {
6215 drive-strength = <2>;
6216 bias-bus-hold;
6219 data-pins {
6221 drive-strength = <2>;
6222 bias-bus-hold;
6228 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd";
6232 #address-cells = <1>;
6233 #size-cells = <1>;
6235 pil-reloc@94c {
6236 compatible = "qcom,pil-reloc-info";
6242 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
6244 #iommu-cells = <2>;
6245 #global-interrupts = <2>;
6246 dma-coherent;
6381 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
6383 #iommu-cells = <2>;
6384 #global-interrupts = <2>;
6385 dma-coherent;
6455 intc: interrupt-controller@17a00000 {
6456 compatible = "arm,gic-v3";
6459 interrupt-controller;
6460 #address-cells = <0>;
6461 #interrupt-cells = <3>;
6463 #redistributor-regions = <1>;
6464 redistributor-stride = <0x0 0x20000>;
6468 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
6475 compatible = "arm,armv7-timer-mem";
6478 #address-cells = <1>;
6479 #size-cells = <1>;
6486 frame-number = <0>;
6492 frame-number = <1>;
6499 frame-number = <2>;
6506 frame-number = <3>;
6513 frame-number = <4>;
6520 frame-number = <5>;
6527 frame-number = <6>;
6533 compatible = "qcom,rpmh-rsc";
6537 reg-names = "drv-0", "drv-1", "drv-2";
6541 qcom,tcs-offset = <0xd00>;
6542 qcom,drv-id = <2>;
6543 qcom,tcs-config = <ACTIVE_TCS 2>,
6548 power-domains = <&system_pd>;
6550 apps_bcm_voter: bcm-voter {
6551 compatible = "qcom,bcm-voter";
6554 rpmhcc: clock-controller {
6555 compatible = "qcom,sa8775p-rpmh-clk";
6556 #clock-cells = <1>;
6557 clock-names = "xo";
6561 rpmhpd: power-controller {
6562 compatible = "qcom,sa8775p-rpmhpd";
6563 #power-domain-cells = <1>;
6564 operating-points-v2 = <&rpmhpd_opp_table>;
6566 rpmhpd_opp_table: opp-table {
6567 compatible = "operating-points-v2";
6569 rpmhpd_opp_ret: opp-0 {
6570 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6573 rpmhpd_opp_min_svs: opp-1 {
6574 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6578 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6582 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6585 rpmhpd_opp_svs_l1: opp-4 {
6586 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6589 rpmhpd_opp_nom: opp-5 {
6590 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6593 rpmhpd_opp_nom_l1: opp-6 {
6594 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6597 rpmhpd_opp_nom_l2: opp-7 {
6598 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6601 rpmhpd_opp_turbo: opp-8 {
6602 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6605 rpmhpd_opp_turbo_l1: opp-9 {
6606 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6613 compatible = "qcom,sa8775p-epss-l3",
6614 "qcom,epss-l3";
6616 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
6617 clock-names = "xo", "alternate";
6618 #interconnect-cells = <1>;
6622 compatible = "qcom,sa8775p-cpufreq-epss",
6623 "qcom,cpufreq-epss";
6626 reg-names = "freq-domain0", "freq-domain1";
6630 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
6632 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
6633 clock-names = "xo", "alternate";
6635 #freq-domain-cells = <1>;
6639 compatible = "qcom,sa8775p-epss-l3",
6640 "qcom,epss-l3";
6642 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
6643 clock-names = "xo", "alternate";
6644 #interconnect-cells = <1>;
6648 compatible = "qcom,sa8775p-gpdsp0-pas";
6651 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
6656 interrupt-names = "wdog", "fatal", "ready",
6657 "handover", "stop-ack";
6660 clock-names = "xo";
6662 power-domains = <&rpmhpd SA8775P_CX>,
6664 power-domain-names = "cx", "mxc";
6669 memory-region = <&pil_gdsp0_mem>;
6673 qcom,smem-states = <&smp2p_gpdsp0_out 0>;
6674 qcom,smem-state-names = "stop";
6678 glink-edge {
6679 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
6686 qcom,remote-pid = <17>;
6690 qcom,glink-channels = "fastrpcglink-apps-dsp";
6692 #address-cells = <1>;
6693 #size-cells = <0>;
6695 compute-cb@1 {
6696 compatible = "qcom,fastrpc-compute-cb";
6699 dma-coherent;
6702 compute-cb@2 {
6703 compatible = "qcom,fastrpc-compute-cb";
6706 dma-coherent;
6709 compute-cb@3 {
6710 compatible = "qcom,fastrpc-compute-cb";
6713 dma-coherent;
6720 compatible = "qcom,sa8775p-gpdsp1-pas";
6723 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
6728 interrupt-names = "wdog", "fatal", "ready",
6729 "handover", "stop-ack";
6732 clock-names = "xo";
6734 power-domains = <&rpmhpd SA8775P_CX>,
6736 power-domain-names = "cx", "mxc";
6741 memory-region = <&pil_gdsp1_mem>;
6745 qcom,smem-states = <&smp2p_gpdsp1_out 0>;
6746 qcom,smem-state-names = "stop";
6750 glink-edge {
6751 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
6758 qcom,remote-pid = <18>;
6762 qcom,glink-channels = "fastrpcglink-apps-dsp";
6764 #address-cells = <1>;
6765 #size-cells = <0>;
6767 compute-cb@1 {
6768 compatible = "qcom,fastrpc-compute-cb";
6771 dma-coherent;
6774 compute-cb@2 {
6775 compatible = "qcom,fastrpc-compute-cb";
6778 dma-coherent;
6781 compute-cb@3 {
6782 compatible = "qcom,fastrpc-compute-cb";
6785 dma-coherent;
6791 dispcc1: clock-controller@22100000 {
6792 compatible = "qcom,sa8775p-dispcc1";
6794 clocks = <&gcc GCC_DISP_AHB_CLK>,
6800 power-domains = <&rpmhpd SA8775P_MMCX>;
6801 #clock-cells = <1>;
6802 #reset-cells = <1>;
6803 #power-domain-cells = <1>;
6808 compatible = "qcom,sa8775p-ethqos";
6811 reg-names = "stmmaceth", "rgmii";
6815 interrupt-names = "macirq", "sfty";
6817 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
6818 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
6819 <&gcc GCC_EMAC1_PTP_CLK>,
6820 <&gcc GCC_EMAC1_PHY_AUX_CLK>;
6821 clock-names = "stmmaceth",
6830 interconnect-names = "cpu-mac",
6831 "mac-mem";
6833 power-domains = <&gcc EMAC1_GDSC>;
6836 phy-names = "serdes";
6839 dma-coherent;
6843 rx-fifo-depth = <16384>;
6844 tx-fifo-depth = <16384>;
6850 compatible = "qcom,sa8775p-ethqos";
6853 reg-names = "stmmaceth", "rgmii";
6857 interrupt-names = "macirq", "sfty";
6859 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
6860 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
6861 <&gcc GCC_EMAC0_PTP_CLK>,
6862 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
6863 clock-names = "stmmaceth",
6872 interconnect-names = "cpu-mac",
6873 "mac-mem";
6875 power-domains = <&gcc EMAC0_GDSC>;
6878 phy-names = "serdes";
6881 dma-coherent;
6885 rx-fifo-depth = <16384>;
6886 tx-fifo-depth = <16384>;
6892 compatible = "qcom,sa8775p-cdsp0-pas";
6895 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6900 interrupt-names = "wdog", "fatal", "ready",
6901 "handover", "stop-ack";
6904 clock-names = "xo";
6906 power-domains = <&rpmhpd SA8775P_CX>,
6909 power-domain-names = "cx", "mxc", "nsp";
6914 memory-region = <&pil_cdsp0_mem>;
6918 qcom,smem-states = <&smp2p_cdsp0_out 0>;
6919 qcom,smem-state-names = "stop";
6923 glink-edge {
6924 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6931 qcom,remote-pid = <5>;
6935 qcom,glink-channels = "fastrpcglink-apps-dsp";
6937 #address-cells = <1>;
6938 #size-cells = <0>;
6940 compute-cb@1 {
6941 compatible = "qcom,fastrpc-compute-cb";
6945 dma-coherent;
6948 compute-cb@2 {
6949 compatible = "qcom,fastrpc-compute-cb";
6953 dma-coherent;
6956 compute-cb@3 {
6957 compatible = "qcom,fastrpc-compute-cb";
6961 dma-coherent;
6964 compute-cb@4 {
6965 compatible = "qcom,fastrpc-compute-cb";
6969 dma-coherent;
6972 compute-cb@5 {
6973 compatible = "qcom,fastrpc-compute-cb";
6977 dma-coherent;
6980 compute-cb@6 {
6981 compatible = "qcom,fastrpc-compute-cb";
6985 dma-coherent;
6988 compute-cb@7 {
6989 compatible = "qcom,fastrpc-compute-cb";
6993 dma-coherent;
6996 compute-cb@8 {
6997 compatible = "qcom,fastrpc-compute-cb";
7001 dma-coherent;
7004 compute-cb@9 {
7005 compatible = "qcom,fastrpc-compute-cb";
7009 dma-coherent;
7012 compute-cb@11 {
7013 compatible = "qcom,fastrpc-compute-cb";
7017 dma-coherent;
7024 compatible = "qcom,sa8775p-cdsp1-pas";
7027 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
7032 interrupt-names = "wdog", "fatal", "ready",
7033 "handover", "stop-ack";
7036 clock-names = "xo";
7038 power-domains = <&rpmhpd SA8775P_CX>,
7041 power-domain-names = "cx", "mxc", "nsp";
7046 memory-region = <&pil_cdsp1_mem>;
7050 qcom,smem-states = <&smp2p_cdsp1_out 0>;
7051 qcom,smem-state-names = "stop";
7055 glink-edge {
7056 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
7063 qcom,remote-pid = <12>;
7067 qcom,glink-channels = "fastrpcglink-apps-dsp";
7069 #address-cells = <1>;
7070 #size-cells = <0>;
7072 compute-cb@1 {
7073 compatible = "qcom,fastrpc-compute-cb";
7077 dma-coherent;
7080 compute-cb@2 {
7081 compatible = "qcom,fastrpc-compute-cb";
7085 dma-coherent;
7088 compute-cb@3 {
7089 compatible = "qcom,fastrpc-compute-cb";
7093 dma-coherent;
7096 compute-cb@4 {
7097 compatible = "qcom,fastrpc-compute-cb";
7101 dma-coherent;
7104 compute-cb@5 {
7105 compatible = "qcom,fastrpc-compute-cb";
7109 dma-coherent;
7112 compute-cb@6 {
7113 compatible = "qcom,fastrpc-compute-cb";
7117 dma-coherent;
7120 compute-cb@7 {
7121 compatible = "qcom,fastrpc-compute-cb";
7125 dma-coherent;
7128 compute-cb@8 {
7129 compatible = "qcom,fastrpc-compute-cb";
7133 dma-coherent;
7136 compute-cb@9 {
7137 compatible = "qcom,fastrpc-compute-cb";
7141 dma-coherent;
7144 compute-cb@10 {
7145 compatible = "qcom,fastrpc-compute-cb";
7149 dma-coherent;
7152 compute-cb@11 {
7153 compatible = "qcom,fastrpc-compute-cb";
7157 dma-coherent;
7160 compute-cb@12 {
7161 compatible = "qcom,fastrpc-compute-cb";
7165 dma-coherent;
7168 compute-cb@13 {
7169 compatible = "qcom,fastrpc-compute-cb";
7173 dma-coherent;
7180 compatible = "qcom,sa8775p-adsp-pas";
7183 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
7188 interrupt-names = "wdog", "fatal", "ready", "handover",
7189 "stop-ack";
7192 clock-names = "xo";
7194 power-domains = <&rpmhpd SA8775P_LCX>,
7196 power-domain-names = "lcx", "lmx";
7200 memory-region = <&pil_adsp_mem>;
7204 qcom,smem-states = <&smp2p_adsp_out 0>;
7205 qcom,smem-state-names = "stop";
7209 remoteproc_adsp_glink: glink-edge {
7210 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
7217 qcom,remote-pid = <2>;
7221 qcom,glink-channels = "fastrpcglink-apps-dsp";
7223 memory-region = <&adsp_rpc_remote_heap_mem>;
7226 #address-cells = <1>;
7227 #size-cells = <0>;
7229 compute-cb@3 {
7230 compatible = "qcom,fastrpc-compute-cb";
7233 dma-coherent;
7236 compute-cb@4 {
7237 compatible = "qcom,fastrpc-compute-cb";
7240 dma-coherent;
7243 compute-cb@5 {
7244 compatible = "qcom,fastrpc-compute-cb";
7248 dma-coherent;
7254 qcom,glink-channels = "adsp_apps";
7257 #address-cells = <1>;
7258 #size-cells = <0>;
7263 #sound-dai-cells = <0>;
7264 qcom,protection-domain = "avs/audio",
7268 compatible = "qcom,q6apm-lpass-dais";
7269 #sound-dai-cells = <1>;
7273 compatible = "qcom,q6apm-dais";
7281 qcom,protection-domain = "avs/audio",
7284 q6prmcc: clock-controller {
7285 compatible = "qcom,q6prm-lpass-clocks";
7286 #clock-cells = <2>;
7294 thermal-zones {
7295 aoss-0-thermal {
7296 thermal-sensors = <&tsens0 0>;
7299 trip-point0 {
7305 trip-point1 {
7313 cpu-0-0-0-thermal {
7314 polling-delay-passive = <10>;
7316 thermal-sensors = <&tsens0 1>;
7319 trip-point0 {
7325 trip-point1 {
7333 cpu-0-1-0-thermal {
7334 polling-delay-passive = <10>;
7336 thermal-sensors = <&tsens0 2>;
7339 trip-point0 {
7345 trip-point1 {
7353 cpu-0-2-0-thermal {
7354 polling-delay-passive = <10>;
7356 thermal-sensors = <&tsens0 3>;
7359 trip-point0 {
7365 trip-point1 {
7373 cpu-0-3-0-thermal {
7374 polling-delay-passive = <10>;
7376 thermal-sensors = <&tsens0 4>;
7379 trip-point0 {
7385 trip-point1 {
7393 gpuss-0-thermal {
7394 polling-delay-passive = <10>;
7396 thermal-sensors = <&tsens0 5>;
7399 trip-point0 {
7405 trip-point1 {
7413 gpuss-1-thermal {
7414 polling-delay-passive = <10>;
7416 thermal-sensors = <&tsens0 6>;
7419 trip-point0 {
7425 trip-point1 {
7433 gpuss-2-thermal {
7434 polling-delay-passive = <10>;
7436 thermal-sensors = <&tsens0 7>;
7439 trip-point0 {
7445 trip-point1 {
7453 audio-thermal {
7454 thermal-sensors = <&tsens0 8>;
7457 trip-point0 {
7463 trip-point1 {
7471 camss-0-thermal {
7472 thermal-sensors = <&tsens0 9>;
7475 trip-point0 {
7481 trip-point1 {
7489 pcie-0-thermal {
7490 thermal-sensors = <&tsens0 10>;
7493 trip-point0 {
7499 trip-point1 {
7507 cpuss-0-0-thermal {
7508 thermal-sensors = <&tsens0 11>;
7511 trip-point0 {
7517 trip-point1 {
7525 aoss-1-thermal {
7526 thermal-sensors = <&tsens1 0>;
7529 trip-point0 {
7535 trip-point1 {
7543 cpu-0-0-1-thermal {
7544 polling-delay-passive = <10>;
7546 thermal-sensors = <&tsens1 1>;
7549 trip-point0 {
7555 trip-point1 {
7563 cpu-0-1-1-thermal {
7564 polling-delay-passive = <10>;
7566 thermal-sensors = <&tsens1 2>;
7569 trip-point0 {
7575 trip-point1 {
7583 cpu-0-2-1-thermal {
7584 polling-delay-passive = <10>;
7586 thermal-sensors = <&tsens1 3>;
7589 trip-point0 {
7595 trip-point1 {
7603 cpu-0-3-1-thermal {
7604 polling-delay-passive = <10>;
7606 thermal-sensors = <&tsens1 4>;
7609 trip-point0 {
7615 trip-point1 {
7623 gpuss-3-thermal {
7624 polling-delay-passive = <10>;
7626 thermal-sensors = <&tsens1 5>;
7629 trip-point0 {
7635 trip-point1 {
7643 gpuss-4-thermal {
7644 polling-delay-passive = <10>;
7646 thermal-sensors = <&tsens1 6>;
7649 trip-point0 {
7655 trip-point1 {
7663 gpuss-5-thermal {
7664 polling-delay-passive = <10>;
7666 thermal-sensors = <&tsens1 7>;
7669 trip-point0 {
7675 trip-point1 {
7683 video-thermal {
7684 thermal-sensors = <&tsens1 8>;
7687 trip-point0 {
7693 trip-point1 {
7701 camss-1-thermal {
7702 thermal-sensors = <&tsens1 9>;
7705 trip-point0 {
7711 trip-point1 {
7719 pcie-1-thermal {
7720 thermal-sensors = <&tsens1 10>;
7723 trip-point0 {
7729 trip-point1 {
7737 cpuss-0-1-thermal {
7738 thermal-sensors = <&tsens1 11>;
7741 trip-point0 {
7747 trip-point1 {
7755 aoss-2-thermal {
7756 thermal-sensors = <&tsens2 0>;
7759 trip-point0 {
7765 trip-point1 {
7773 cpu-1-0-0-thermal {
7774 polling-delay-passive = <10>;
7776 thermal-sensors = <&tsens2 1>;
7779 trip-point0 {
7785 trip-point1 {
7793 cpu-1-1-0-thermal {
7794 polling-delay-passive = <10>;
7796 thermal-sensors = <&tsens2 2>;
7799 trip-point0 {
7805 trip-point1 {
7813 cpu-1-2-0-thermal {
7814 polling-delay-passive = <10>;
7816 thermal-sensors = <&tsens2 3>;
7819 trip-point0 {
7825 trip-point1 {
7833 cpu-1-3-0-thermal {
7834 polling-delay-passive = <10>;
7836 thermal-sensors = <&tsens2 4>;
7839 trip-point0 {
7845 trip-point1 {
7853 nsp-0-0-0-thermal {
7854 polling-delay-passive = <10>;
7856 thermal-sensors = <&tsens2 5>;
7859 trip-point0 {
7865 trip-point1 {
7873 nsp-0-1-0-thermal {
7874 polling-delay-passive = <10>;
7876 thermal-sensors = <&tsens2 6>;
7879 trip-point0 {
7885 trip-point1 {
7893 nsp-0-2-0-thermal {
7894 polling-delay-passive = <10>;
7896 thermal-sensors = <&tsens2 7>;
7899 trip-point0 {
7905 trip-point1 {
7913 nsp-1-0-0-thermal {
7914 polling-delay-passive = <10>;
7916 thermal-sensors = <&tsens2 8>;
7919 trip-point0 {
7925 trip-point1 {
7933 nsp-1-1-0-thermal {
7934 polling-delay-passive = <10>;
7936 thermal-sensors = <&tsens2 9>;
7939 trip-point0 {
7945 trip-point1 {
7953 nsp-1-2-0-thermal {
7954 polling-delay-passive = <10>;
7956 thermal-sensors = <&tsens2 10>;
7959 trip-point0 {
7965 trip-point1 {
7973 ddrss-0-thermal {
7974 thermal-sensors = <&tsens2 11>;
7977 trip-point0 {
7983 trip-point1 {
7991 cpuss-1-0-thermal {
7992 thermal-sensors = <&tsens2 12>;
7995 trip-point0 {
8001 trip-point1 {
8009 aoss-3-thermal {
8010 thermal-sensors = <&tsens3 0>;
8013 trip-point0 {
8019 trip-point1 {
8027 cpu-1-0-1-thermal {
8028 polling-delay-passive = <10>;
8030 thermal-sensors = <&tsens3 1>;
8033 trip-point0 {
8039 trip-point1 {
8047 cpu-1-1-1-thermal {
8048 polling-delay-passive = <10>;
8050 thermal-sensors = <&tsens3 2>;
8053 trip-point0 {
8059 trip-point1 {
8067 cpu-1-2-1-thermal {
8068 polling-delay-passive = <10>;
8070 thermal-sensors = <&tsens3 3>;
8073 trip-point0 {
8079 trip-point1 {
8087 cpu-1-3-1-thermal {
8088 polling-delay-passive = <10>;
8090 thermal-sensors = <&tsens3 4>;
8093 trip-point0 {
8099 trip-point1 {
8107 nsp-0-0-1-thermal {
8108 polling-delay-passive = <10>;
8110 thermal-sensors = <&tsens3 5>;
8113 trip-point0 {
8119 trip-point1 {
8127 nsp-0-1-1-thermal {
8128 polling-delay-passive = <10>;
8130 thermal-sensors = <&tsens3 6>;
8133 trip-point0 {
8139 trip-point1 {
8147 nsp-0-2-1-thermal {
8148 polling-delay-passive = <10>;
8150 thermal-sensors = <&tsens3 7>;
8153 trip-point0 {
8159 trip-point1 {
8167 nsp-1-0-1-thermal {
8168 polling-delay-passive = <10>;
8170 thermal-sensors = <&tsens3 8>;
8173 trip-point0 {
8179 trip-point1 {
8187 nsp-1-1-1-thermal {
8188 polling-delay-passive = <10>;
8190 thermal-sensors = <&tsens3 9>;
8193 trip-point0 {
8199 trip-point1 {
8207 nsp-1-2-1-thermal {
8208 polling-delay-passive = <10>;
8210 thermal-sensors = <&tsens3 10>;
8213 trip-point0 {
8219 trip-point1 {
8227 ddrss-1-thermal {
8228 thermal-sensors = <&tsens3 11>;
8231 trip-point0 {
8237 trip-point1 {
8245 cpuss-1-1-thermal {
8246 thermal-sensors = <&tsens3 12>;
8249 trip-point0 {
8255 trip-point1 {
8265 compatible = "arm,armv8-timer";
8273 compatible = "qcom,pcie-sa8775p";
8280 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
8283 #address-cells = <3>;
8284 #size-cells = <2>;
8287 bus-range = <0x00 0xff>;
8289 dma-coherent;
8291 linux,pci-domain = <0>;
8292 num-lanes = <2>;
8303 interrupt-names = "msi0",
8312 #interrupt-cells = <1>;
8313 interrupt-map-mask = <0 0 0 0x7>;
8314 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
8319 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
8320 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
8321 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
8322 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
8323 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
8325 clock-names = "aux",
8331 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
8332 assigned-clock-rates = <19200000>;
8336 interconnect-names = "pcie-mem", "cpu-pcie";
8338 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
8341 resets = <&gcc GCC_PCIE_0_BCR>,
8342 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
8343 reset-names = "pci",
8346 power-domains = <&gcc PCIE_0_GDSC>;
8349 phy-names = "pciephy";
8351 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
8352 eq-presets-16gts = /bits/ 8 <0x55 0x55>;
8359 bus-range = <0x01 0xff>;
8361 #address-cells = <3>;
8362 #size-cells = <2>;
8367 pcie0_ep: pcie-ep@1c00000 {
8368 compatible = "qcom,sa8775p-pcie-ep";
8376 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
8379 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
8380 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
8381 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
8382 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
8383 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
8385 clock-names = "aux",
8395 interrupt-names = "global", "doorbell", "dma";
8399 interconnect-names = "pcie-mem", "cpu-pcie";
8401 dma-coherent;
8403 resets = <&gcc GCC_PCIE_0_BCR>;
8404 reset-names = "core";
8405 power-domains = <&gcc PCIE_0_GDSC>;
8407 phy-names = "pciephy";
8408 num-lanes = <2>;
8409 linux,pci-domain = <0>;
8415 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
8418 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
8419 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
8420 <&gcc GCC_PCIE_CLKREF_EN>,
8421 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
8422 <&gcc GCC_PCIE_0_PIPE_CLK>,
8423 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
8424 clock-names = "aux",
8431 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
8432 assigned-clock-rates = <100000000>;
8434 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
8435 reset-names = "phy";
8437 #clock-cells = <0>;
8438 clock-output-names = "pcie_0_pipe_clk";
8440 #phy-cells = <0>;
8446 compatible = "qcom,pcie-sa8775p";
8453 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
8456 #address-cells = <3>;
8457 #size-cells = <2>;
8460 bus-range = <0x00 0xff>;
8462 dma-coherent;
8464 linux,pci-domain = <1>;
8465 num-lanes = <4>;
8476 interrupt-names = "msi0",
8485 #interrupt-cells = <1>;
8486 interrupt-map-mask = <0 0 0 0x7>;
8487 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
8492 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
8493 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
8494 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
8495 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
8496 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
8498 clock-names = "aux",
8504 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
8505 assigned-clock-rates = <19200000>;
8509 interconnect-names = "pcie-mem", "cpu-pcie";
8511 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
8514 resets = <&gcc GCC_PCIE_1_BCR>,
8515 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
8516 reset-names = "pci",
8519 power-domains = <&gcc PCIE_1_GDSC>;
8522 phy-names = "pciephy";
8524 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
8525 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
8532 bus-range = <0x01 0xff>;
8534 #address-cells = <3>;
8535 #size-cells = <2>;
8540 pcie1_ep: pcie-ep@1c10000 {
8541 compatible = "qcom,sa8775p-pcie-ep";
8549 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
8552 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
8553 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
8554 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
8555 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
8556 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
8558 clock-names = "aux",
8568 interrupt-names = "global", "doorbell", "dma";
8572 interconnect-names = "pcie-mem", "cpu-pcie";
8574 dma-coherent;
8576 resets = <&gcc GCC_PCIE_1_BCR>;
8577 reset-names = "core";
8578 power-domains = <&gcc PCIE_1_GDSC>;
8580 phy-names = "pciephy";
8581 num-lanes = <4>;
8582 linux,pci-domain = <1>;
8588 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
8591 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
8592 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
8593 <&gcc GCC_PCIE_CLKREF_EN>,
8594 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
8595 <&gcc GCC_PCIE_1_PIPE_CLK>,
8596 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
8597 clock-names = "aux",
8604 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
8605 assigned-clock-rates = <100000000>;
8607 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
8608 reset-names = "phy";
8610 #clock-cells = <0>;
8611 clock-output-names = "pcie_1_pipe_clk";
8613 #phy-cells = <0>;