Lines Matching +full:tcsr +full:- +full:mutex
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
11 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
12 #include <dt-bindings/interconnect/qcom,ipq9574.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 ref_48mhz_clk: ref-48mhz-clk {
24 compatible = "fixed-factor-clock";
26 #clock-cells = <0>;
29 sleep_clk: sleep-clk {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
34 xo_board_clk: xo-board-clk {
35 compatible = "fixed-factor-clock";
37 #clock-cells = <0>;
40 xo_clk: xo-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a73";
54 enable-method = "psci";
55 next-level-cache = <&l2_0>;
57 clock-names = "cpu";
58 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a73";
67 enable-method = "psci";
68 next-level-cache = <&l2_0>;
70 clock-names = "cpu";
71 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>;
78 compatible = "arm,cortex-a73";
80 enable-method = "psci";
81 next-level-cache = <&l2_0>;
83 clock-names = "cpu";
84 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>;
91 compatible = "arm,cortex-a73";
93 enable-method = "psci";
94 next-level-cache = <&l2_0>;
96 clock-names = "cpu";
97 operating-points-v2 = <&cpu_opp_table>;
98 cpu-supply = <&ipq9574_s1>;
99 #cooling-cells = <2>;
102 l2_0: l2-cache {
104 cache-level = <2>;
105 cache-unified;
111 compatible = "qcom,scm-ipq9574", "qcom,scm";
112 qcom,dload-mode = <&tcsr 0x6100>;
122 cpu_opp_table: opp-table-cpu {
123 compatible = "operating-points-v2-kryo-cpu";
124 opp-shared;
125 nvmem-cells = <&cpu_speed_bin>;
127 opp-936000000 {
128 opp-hz = /bits/ 64 <936000000>;
129 opp-microvolt = <725000>;
130 opp-supported-hw = <0xf>;
131 clock-latency-ns = <200000>;
134 opp-1104000000 {
135 opp-hz = /bits/ 64 <1104000000>;
136 opp-microvolt = <787500>;
137 opp-supported-hw = <0xf>;
138 clock-latency-ns = <200000>;
141 opp-1200000000 {
142 opp-hz = /bits/ 64 <1200000000>;
143 opp-microvolt = <862500>;
144 opp-supported-hw = <0xf>;
145 clock-latency-ns = <200000>;
148 opp-1416000000 {
149 opp-hz = /bits/ 64 <1416000000>;
150 opp-microvolt = <862500>;
151 opp-supported-hw = <0x7>;
152 clock-latency-ns = <200000>;
155 opp-1488000000 {
156 opp-hz = /bits/ 64 <1488000000>;
157 opp-microvolt = <925000>;
158 opp-supported-hw = <0x7>;
159 clock-latency-ns = <200000>;
162 opp-1800000000 {
163 opp-hz = /bits/ 64 <1800000000>;
164 opp-microvolt = <987500>;
165 opp-supported-hw = <0x5>;
166 clock-latency-ns = <200000>;
169 opp-2208000000 {
170 opp-hz = /bits/ 64 <2208000000>;
171 opp-microvolt = <1062500>;
172 opp-supported-hw = <0x1>;
173 clock-latency-ns = <200000>;
178 compatible = "arm,cortex-a73-pmu";
183 compatible = "arm,psci-1.0";
188 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
190 glink-edge {
191 compatible = "qcom,glink-rpm";
193 qcom,rpm-msg-ram = <&rpm_msg_ram>;
196 rpm_requests: rpm-requests {
197 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";
198 qcom,glink-channels = "rpm_requests";
203 reserved-memory {
204 #address-cells = <2>;
205 #size-cells = <2>;
210 no-map;
215 no-map;
220 no-map;
227 no-map;
232 compatible = "simple-bus";
233 #address-cells = <1>;
234 #size-cells = <1>;
238 compatible = "qcom,rpm-msg-ram";
243 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
249 clock-names = "aux", "cfg_ahb", "pipe";
251 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
252 assigned-clock-rates = <20000000>;
256 reset-names = "phy", "common";
258 #clock-cells = <0>;
259 clock-output-names = "gcc_pcie0_pipe_clk_src";
261 #phy-cells = <0>;
266 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
272 clock-names = "aux", "cfg_ahb", "pipe";
274 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
275 assigned-clock-rates = <20000000>;
279 reset-names = "phy", "common";
281 #clock-cells = <0>;
282 clock-output-names = "gcc_pcie2_pipe_clk_src";
284 #phy-cells = <0>;
289 compatible = "qcom,ipq9574-trng", "qcom,trng";
292 clock-names = "core";
296 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
298 #address-cells = <1>;
299 #size-cells = <0>;
301 clock-names = "gcc_mdio_ahb_clk";
306 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
312 clock-names = "aux", "cfg_ahb", "pipe";
314 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
315 assigned-clock-rates = <20000000>;
319 reset-names = "phy", "common";
321 #clock-cells = <0>;
322 clock-output-names = "gcc_pcie3_pipe_clk_src";
324 #phy-cells = <0>;
329 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
335 clock-names = "aux", "cfg_ahb", "pipe";
337 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
338 assigned-clock-rates = <20000000>;
342 reset-names = "phy", "common";
344 #clock-cells = <0>;
345 clock-output-names = "gcc_pcie1_pipe_clk_src";
347 #phy-cells = <0>;
351 cmn_pll: clock-controller@9b000 {
352 compatible = "qcom,ipq9574-cmn-pll";
357 clock-names = "ref", "ahb", "sys";
358 #clock-cells = <1>;
359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
360 assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
364 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
366 #address-cells = <1>;
367 #size-cells = <1>;
369 cpu_speed_bin: cpu-speed-bin@15 {
375 cryptobam: dma-controller@704000 {
376 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
379 #dma-cells = <1>;
381 qcom,controlled-remotely;
385 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
390 clock-names = "iface", "bus", "core";
392 dma-names = "rx", "tx";
395 tsens: thermal-sensor@4a9000 {
396 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
400 interrupt-names = "combined";
402 #thermal-sensor-cells = <1>;
406 compatible = "qcom,ipq9574-tlmm";
409 gpio-controller;
410 #gpio-cells = <2>;
411 gpio-ranges = <&tlmm 0 0 65>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
415 uart2_pins: uart2-state {
418 drive-strength = <8>;
419 bias-disable;
423 gcc: clock-controller@1800000 {
424 compatible = "qcom,ipq9574-gcc";
434 #clock-cells = <1>;
435 #reset-cells = <1>;
436 #interconnect-cells = <1>;
440 compatible = "qcom,tcsr-mutex";
442 #hwlock-cells = <1>;
445 tcsr: syscon@1937000 {
446 compatible = "qcom,tcsr-ipq9574", "syscon";
451 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
455 reg-names = "hc", "cqhci", "ice";
459 interrupt-names = "hc_irq", "pwr_irq";
465 clock-names = "iface", "core", "xo", "ice";
466 non-removable;
467 supports-cqe;
471 blsp_dma: dma-controller@7884000 {
472 compatible = "qcom,bam-v1.7.0";
476 clock-names = "bam_clk";
477 #dma-cells = <1>;
482 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
487 clock-names = "core", "iface";
492 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
497 clock-names = "core", "iface";
502 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
507 clock-names = "core", "iface";
512 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
517 clock-names = "core", "iface";
522 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
527 clock-names = "core", "iface";
532 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
537 clock-names = "core", "iface";
542 compatible = "qcom,spi-qup-v2.2.1";
544 #address-cells = <1>;
545 #size-cells = <0>;
549 clock-names = "core", "iface";
551 dma-names = "tx", "rx";
556 compatible = "qcom,i2c-qup-v2.2.1";
558 #address-cells = <1>;
559 #size-cells = <0>;
563 clock-names = "core", "iface";
564 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
565 assigned-clock-rates = <50000000>;
567 dma-names = "tx", "rx";
572 compatible = "qcom,spi-qup-v2.2.1";
574 #address-cells = <1>;
575 #size-cells = <0>;
579 clock-names = "core", "iface";
581 dma-names = "tx", "rx";
586 compatible = "qcom,i2c-qup-v2.2.1";
588 #address-cells = <1>;
589 #size-cells = <0>;
593 clock-names = "core", "iface";
594 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
595 assigned-clock-rates = <50000000>;
597 dma-names = "tx", "rx";
602 compatible = "qcom,spi-qup-v2.2.1";
604 #address-cells = <1>;
605 #size-cells = <0>;
609 clock-names = "core", "iface";
611 dma-names = "tx", "rx";
616 compatible = "qcom,i2c-qup-v2.2.1";
618 #address-cells = <1>;
619 #size-cells = <0>;
623 clock-names = "core", "iface";
624 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
625 assigned-clock-rates = <50000000>;
627 dma-names = "tx", "rx";
632 compatible = "qcom,spi-qup-v2.2.1";
634 #address-cells = <1>;
635 #size-cells = <0>;
637 spi-max-frequency = <50000000>;
640 clock-names = "core", "iface";
642 dma-names = "tx", "rx";
647 compatible = "qcom,i2c-qup-v2.2.1";
649 #address-cells = <1>;
650 #size-cells = <0>;
654 clock-names = "core", "iface";
655 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
656 assigned-clock-rates = <50000000>;
658 dma-names = "tx", "rx";
663 compatible = "qcom,spi-qup-v2.2.1";
665 #address-cells = <1>;
666 #size-cells = <0>;
670 clock-names = "core", "iface";
672 dma-names = "tx", "rx";
677 compatible = "qcom,ipq9574-qusb2-phy";
679 #phy-cells = <0>;
683 clock-names = "cfg_ahb",
691 compatible = "qcom,ipq9574-qmp-usb3-phy";
693 #phy-cells = <0>;
699 clock-names = "aux",
706 reset-names = "phy",
709 #clock-cells = <0>;
710 clock-output-names = "usb0_pipe_clk";
716 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
718 #address-cells = <1>;
719 #size-cells = <1>;
728 clock-names = "cfg_noc",
734 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
736 assigned-clock-rates = <200000000>,
739 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
740 interrupt-names = "pwr_event";
749 clock-names = "ref";
752 phy-names = "usb2-phy", "usb3-phy";
753 tx-fifo-resize;
754 snps,is-utmi-l1-suspend;
755 snps,hird-threshold = /bits/ 8 <0x0>;
761 intc: interrupt-controller@b000000 {
762 compatible = "qcom,msm-qgic2";
767 #address-cells = <1>;
768 #size-cells = <1>;
769 interrupt-controller;
770 #interrupt-cells = <3>;
775 compatible = "arm,gic-v2m-frame";
777 msi-controller;
781 compatible = "arm,gic-v2m-frame";
783 msi-controller;
787 compatible = "arm,gic-v2m-frame";
789 msi-controller;
794 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
798 timeout-sec = <30>;
802 compatible = "qcom,ipq9574-apcs-apps-global",
803 "qcom,ipq6018-apcs-apps-global";
805 #clock-cells = <1>;
807 clock-names = "pll", "xo", "gpll0";
808 #mbox-cells = <1>;
812 compatible = "qcom,ipq9574-a73pll";
814 #clock-cells = <0>;
816 clock-names = "xo";
820 compatible = "arm,armv7-timer-mem";
822 #address-cells = <1>;
823 #size-cells = <1>;
829 frame-number = <0>;
836 frame-number = <1>;
843 frame-number = <2>;
850 frame-number = <3>;
857 frame-number = <4>;
864 frame-number = <5>;
871 frame-number = <6>;
878 compatible = "qcom,pcie-ipq9574";
884 reg-names = "dbi", "elbi", "atu", "parf", "config";
886 linux,pci-domain = <1>;
887 bus-range = <0x00 0xff>;
888 num-lanes = <1>;
889 #address-cells = <3>;
890 #size-cells = <2>;
903 interrupt-names = "msi0",
912 #interrupt-cells = <1>;
913 interrupt-map-mask = <0 0 0 0x7>;
914 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
925 clock-names = "axi_m",
940 reset-names = "pipe",
950 phy-names = "pciephy";
953 interconnect-names = "pcie-mem", "cpu-pcie";
958 compatible = "qcom,pcie-ipq9574";
964 reg-names = "dbi", "elbi", "atu", "parf", "config";
966 linux,pci-domain = <3>;
967 bus-range = <0x00 0xff>;
968 num-lanes = <2>;
969 #address-cells = <3>;
970 #size-cells = <2>;
983 interrupt-names = "msi0",
992 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0 0 0x7>;
994 interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
1005 clock-names = "axi_m",
1020 reset-names = "pipe",
1030 phy-names = "pciephy";
1033 interconnect-names = "pcie-mem", "cpu-pcie";
1038 compatible = "qcom,pcie-ipq9574";
1044 reg-names = "dbi", "elbi", "atu", "parf", "config";
1046 linux,pci-domain = <2>;
1047 bus-range = <0x00 0xff>;
1048 num-lanes = <2>;
1049 #address-cells = <3>;
1050 #size-cells = <2>;
1063 interrupt-names = "msi0",
1072 #interrupt-cells = <1>;
1073 interrupt-map-mask = <0 0 0 0x7>;
1074 interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
1085 clock-names = "axi_m",
1100 reset-names = "pipe",
1110 phy-names = "pciephy";
1113 interconnect-names = "pcie-mem", "cpu-pcie";
1118 compatible = "qcom,pcie-ipq9574";
1124 reg-names = "dbi", "elbi", "atu", "parf", "config";
1126 linux,pci-domain = <0>;
1127 bus-range = <0x00 0xff>;
1128 num-lanes = <1>;
1129 #address-cells = <3>;
1130 #size-cells = <2>;
1142 interrupt-names = "msi0",
1151 #interrupt-cells = <1>;
1152 interrupt-map-mask = <0 0 0 0x7>;
1153 interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
1164 clock-names = "axi_m",
1179 reset-names = "pipe",
1189 phy-names = "pciephy";
1192 interconnect-names = "pcie-mem", "cpu-pcie";
1198 thermal-zones {
1199 nss-top-thermal {
1200 thermal-sensors = <&tsens 3>;
1203 nss-top-critical {
1211 ubi-0-thermal {
1212 thermal-sensors = <&tsens 4>;
1215 ubi_0-critical {
1223 ubi-1-thermal {
1224 thermal-sensors = <&tsens 5>;
1227 ubi_1-critical {
1235 ubi-2-thermal {
1236 thermal-sensors = <&tsens 6>;
1239 ubi_2-critical {
1247 ubi-3-thermal {
1248 thermal-sensors = <&tsens 7>;
1251 ubi_3-critical {
1259 cpuss0-thermal {
1260 thermal-sensors = <&tsens 8>;
1263 cpu-critical {
1271 cpuss1-thermal {
1272 thermal-sensors = <&tsens 9>;
1275 cpu-critical {
1283 cpu0-thermal {
1284 thermal-sensors = <&tsens 10>;
1287 cpu0_crit: cpu-critical {
1293 cpu0_alert: cpu-passive {
1300 cooling-maps {
1303 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1311 cpu1-thermal {
1312 thermal-sensors = <&tsens 11>;
1315 cpu1_crit: cpu-critical {
1321 cpu1_alert: cpu-passive {
1328 cooling-maps {
1331 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1339 cpu2-thermal {
1340 thermal-sensors = <&tsens 12>;
1343 cpu2_crit: cpu-critical {
1349 cpu2_alert: cpu-passive {
1356 cooling-maps {
1359 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1367 cpu3-thermal {
1368 thermal-sensors = <&tsens 13>;
1371 cpu3_crit: cpu-critical {
1377 cpu3_alert: cpu-passive {
1384 cooling-maps {
1387 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1395 wcss-phyb-thermal {
1396 thermal-sensors = <&tsens 14>;
1399 wcss_phyb-critical {
1407 top-glue-thermal {
1408 thermal-sensors = <&tsens 15>;
1411 top_glue-critical {
1421 compatible = "arm,armv8-timer";