Lines Matching +full:i2c +full:- +full:qup +full:- +full:v1
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
12 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&intc>;
20 sleep_clk: sleep-clk {
21 compatible = "fixed-clock";
22 clock-frequency = <32000>;
23 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <24000000>;
29 #clock-cells = <0>;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 next-level-cache = <&l2_0>;
44 clock-names = "cpu";
45 operating-points-v2 = <&cpu_opp_table>;
46 #cooling-cells = <2>;
51 compatible = "arm,cortex-a53";
52 enable-method = "psci";
54 next-level-cache = <&l2_0>;
56 clock-names = "cpu";
57 operating-points-v2 = <&cpu_opp_table>;
58 #cooling-cells = <2>;
63 compatible = "arm,cortex-a53";
64 enable-method = "psci";
66 next-level-cache = <&l2_0>;
68 clock-names = "cpu";
69 operating-points-v2 = <&cpu_opp_table>;
70 #cooling-cells = <2>;
75 compatible = "arm,cortex-a53";
76 enable-method = "psci";
78 next-level-cache = <&l2_0>;
80 clock-names = "cpu";
81 operating-points-v2 = <&cpu_opp_table>;
82 #cooling-cells = <2>;
85 l2_0: l2-cache {
87 cache-level = <2>;
88 cache-unified;
94 compatible = "qcom,scm-ipq6018", "qcom,scm";
95 qcom,dload-mode = <&tcsr 0x6100>;
99 cpu_opp_table: opp-table-cpu {
100 compatible = "operating-points-v2-kryo-cpu";
101 nvmem-cells = <&cpu_speed_bin>;
102 opp-shared;
104 opp-864000000 {
105 opp-hz = /bits/ 64 <864000000>;
106 opp-microvolt = <725000>;
107 opp-supported-hw = <0xf>;
108 clock-latency-ns = <200000>;
111 opp-1056000000 {
112 opp-hz = /bits/ 64 <1056000000>;
113 opp-microvolt = <787500>;
114 opp-supported-hw = <0xf>;
115 clock-latency-ns = <200000>;
118 opp-1200000000 {
119 opp-hz = /bits/ 64 <1200000000>;
120 opp-microvolt = <850000>;
121 opp-supported-hw = <0x4>;
122 clock-latency-ns = <200000>;
125 opp-1320000000 {
126 opp-hz = /bits/ 64 <1320000000>;
127 opp-microvolt = <862500>;
128 opp-supported-hw = <0x3>;
129 clock-latency-ns = <200000>;
132 opp-1440000000 {
133 opp-hz = /bits/ 64 <1440000000>;
134 opp-microvolt = <925000>;
135 opp-supported-hw = <0x3>;
136 clock-latency-ns = <200000>;
139 opp-1512000000 {
140 opp-hz = /bits/ 64 <1512000000>;
141 opp-microvolt = <937500>;
142 opp-supported-hw = <0x2>;
143 clock-latency-ns = <200000>;
146 opp-1608000000 {
147 opp-hz = /bits/ 64 <1608000000>;
148 opp-microvolt = <987500>;
149 opp-supported-hw = <0x1>;
150 clock-latency-ns = <200000>;
153 opp-1800000000 {
154 opp-hz = /bits/ 64 <1800000000>;
155 opp-microvolt = <1062500>;
156 opp-supported-hw = <0x1>;
157 clock-latency-ns = <200000>;
162 compatible = "arm,cortex-a53-pmu";
167 compatible = "arm,psci-1.0";
172 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
174 glink-edge {
175 compatible = "qcom,glink-rpm";
177 qcom,rpm-msg-ram = <&rpm_msg_ram>;
180 rpm_requests: rpm-requests {
181 compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm";
182 qcom,glink-channels = "rpm_requests";
187 reserved-memory {
188 #address-cells = <2>;
189 #size-cells = <2>;
194 no-map;
199 no-map;
204 no-map;
209 no-map;
215 no-map;
222 no-map;
227 #address-cells = <2>;
228 #size-cells = <2>;
230 dma-ranges;
231 compatible = "simple-bus";
234 compatible = "qcom,ipq6018-qusb2-phy";
236 #phy-cells = <0>;
240 clock-names = "cfg_ahb", "ref";
247 compatible = "qcom,ipq6018-qmp-usb3-phy";
254 clock-names = "aux",
258 clock-output-names = "gcc_usb0_pipe_clk_src";
259 #clock-cells = <0>;
260 #phy-cells = <0>;
264 reset-names = "phy",
271 compatible = "qcom,ipq6018-qusb2-phy";
273 #phy-cells = <0>;
277 clock-names = "cfg_ahb", "ref";
284 compatible = "qcom,ipq6018-qmp-pcie-phy";
291 clock-names = "aux",
295 clock-output-names = "gcc_pcie0_pipe_clk_src";
296 #clock-cells = <0>;
298 #phy-cells = <0>;
302 reset-names = "phy",
307 #address-cells = <1>;
308 #size-cells = <0>;
309 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
312 clock-names = "gcc_mdio_ahb_clk";
317 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
319 #address-cells = <1>;
320 #size-cells = <1>;
322 cpu_speed_bin: cpu-speed-bin@135 {
329 compatible = "qcom,prng-ee";
332 clock-names = "core";
335 tsens: thermal-sensor@4a9000 {
336 compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
340 interrupt-names = "combined";
342 #thermal-sensor-cells = <1>;
345 cryptobam: dma-controller@704000 {
346 compatible = "qcom,bam-v1.7.0";
350 clock-names = "bam_clk";
351 #dma-cells = <1>;
353 qcom,controlled-remotely;
357 compatible = "qcom,crypto-v5.1";
362 clock-names = "iface", "bus", "core";
364 dma-names = "rx", "tx";
368 compatible = "qcom,ipq6018-pinctrl";
371 gpio-controller;
372 #gpio-cells = <2>;
373 gpio-ranges = <&tlmm 0 0 80>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
377 serial_3_pins: serial3-state {
380 drive-strength = <8>;
381 bias-pull-down;
384 qpic_pins: qpic-state {
391 drive-strength = <8>;
392 bias-disable;
396 gcc: clock-controller@1800000 {
397 compatible = "qcom,gcc-ipq6018";
400 clock-names = "xo", "sleep_clk";
401 #clock-cells = <1>;
402 #reset-cells = <1>;
406 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
408 #hwlock-cells = <1>;
412 compatible = "qcom,tcsr-ipq6018", "syscon";
417 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
419 #address-cells = <2>;
420 #size-cells = <2>;
425 clock-names = "core",
429 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
431 assigned-clock-rates = <133330000>,
436 interrupt-names = "pwr_event",
447 phy-names = "usb2-phy";
448 tx-fifo-resize;
449 snps,is-utmi-l1-suspend;
450 snps,hird-threshold = /bits/ 8 <0x0>;
458 compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
461 reg-names = "hc", "cqhci";
465 interrupt-names = "hc_irq", "pwr_irq";
470 clock-names = "iface", "core", "xo";
472 max-frequency = <192000000>;
476 blsp_dma: dma-controller@7884000 {
477 compatible = "qcom,bam-v1.7.0";
481 clock-names = "bam_clk";
482 #dma-cells = <1>;
487 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
492 clock-names = "core", "iface";
497 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
502 clock-names = "core", "iface";
507 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
512 clock-names = "core", "iface";
517 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
522 clock-names = "core", "iface";
527 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
532 clock-names = "core", "iface";
537 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
542 clock-names = "core", "iface";
547 compatible = "qcom,spi-qup-v2.2.1";
548 #address-cells = <1>;
549 #size-cells = <0>;
554 clock-names = "core", "iface";
556 dma-names = "tx", "rx";
561 compatible = "qcom,spi-qup-v2.2.1";
562 #address-cells = <1>;
563 #size-cells = <0>;
568 clock-names = "core", "iface";
570 dma-names = "tx", "rx";
575 compatible = "qcom,spi-qup-v2.2.1";
576 #address-cells = <1>;
577 #size-cells = <0>;
582 clock-names = "core", "iface";
584 dma-names = "tx", "rx";
588 blsp1_i2c2: i2c@78b6000 {
589 compatible = "qcom,i2c-qup-v2.2.1";
590 #address-cells = <1>;
591 #size-cells = <0>;
596 clock-names = "core", "iface";
597 clock-frequency = <400000>;
599 dma-names = "tx", "rx";
603 blsp1_i2c3: i2c@78b7000 {
604 compatible = "qcom,i2c-qup-v2.2.1";
605 #address-cells = <1>;
606 #size-cells = <0>;
611 clock-names = "core", "iface";
612 clock-frequency = <400000>;
614 dma-names = "tx", "rx";
618 blsp1_i2c6: i2c@78ba000 {
619 compatible = "qcom,i2c-qup-v2.2.1";
620 #address-cells = <1>;
621 #size-cells = <0>;
626 clock-names = "core", "iface";
627 clock-frequency = <400000>;
629 dma-names = "tx", "rx";
633 qpic_bam: dma-controller@7984000 {
634 compatible = "qcom,bam-v1.7.0";
638 clock-names = "bam_clk";
639 #dma-cells = <1>;
644 qpic_nand: nand-controller@79b0000 {
645 compatible = "qcom,ipq6018-nand";
647 #address-cells = <1>;
648 #size-cells = <0>;
651 clock-names = "core", "aon";
656 dma-names = "tx", "rx", "cmd";
657 pinctrl-0 = <&qpic_pins>;
658 pinctrl-names = "default";
663 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
665 #address-cells = <2>;
666 #size-cells = <2>;
673 clock-names = "cfg_noc",
678 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
681 assigned-clock-rates = <133330000>,
688 interrupt-names = "pwr_event",
700 phy-names = "usb2-phy", "usb3-phy";
702 clock-names = "ref";
703 tx-fifo-resize;
704 snps,parkmode-disable-ss-quirk;
705 snps,is-utmi-l1-suspend;
706 snps,hird-threshold = /bits/ 8 <0x0>;
713 intc: interrupt-controller@b000000 {
714 compatible = "qcom,msm-qgic2";
715 #address-cells = <2>;
716 #size-cells = <2>;
717 interrupt-controller;
718 #interrupt-cells = <3>;
727 compatible = "arm,gic-v2m-frame";
728 msi-controller;
734 compatible = "qcom,kpss-wdt";
738 timeout-sec = <10>;
742 compatible = "qcom,ipq6018-apcs-apps-global";
744 #clock-cells = <1>;
746 clock-names = "pll", "xo", "gpll0";
747 #mbox-cells = <1>;
751 compatible = "qcom,ipq6018-a53pll";
753 #clock-cells = <0>;
755 clock-names = "xo";
759 #address-cells = <1>;
760 #size-cells = <1>;
762 compatible = "arm,armv7-timer-mem";
766 frame-number = <0>;
774 frame-number = <1>;
781 frame-number = <2>;
788 frame-number = <3>;
795 frame-number = <4>;
802 frame-number = <5>;
809 frame-number = <6>;
817 compatible = "qcom,ipq6018-wcss-pil";
820 reg-names = "qdsp6",
822 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
827 interrupt-names = "wdog",
831 "stop-ack";
837 reset-names = "wcss_aon_reset",
842 clock-names = "prng";
844 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
846 qcom,smem-states = <&wcss_smp2p_out 0>,
848 qcom,smem-state-names = "shutdown",
851 memory-region = <&q6_region>;
853 glink-edge {
856 qcom,remote-pid = <1>;
860 qcom,glink-channels = "IPCRTR";
866 compatible = "qcom,pcie-ipq6018";
872 reg-names = "dbi", "elbi", "atu", "parf", "config";
875 linux,pci-domain = <0>;
876 bus-range = <0x00 0xff>;
877 num-lanes = <1>;
878 max-link-speed = <3>;
879 #address-cells = <3>;
880 #size-cells = <2>;
883 phy-names = "pciephy";
897 interrupt-names = "msi0",
907 #interrupt-cells = <1>;
908 interrupt-map-mask = <0 0 0 0x7>;
909 interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
919 clock-names = "iface",
933 reset-names = "pipe",
947 bus-range = <0x01 0xff>;
949 #address-cells = <3>;
950 #size-cells = <2>;
956 thermal-zones {
957 nss-top-thermal {
958 polling-delay-passive = <250>;
959 thermal-sensors = <&tsens 4>;
962 nss-top-critical {
970 nss-thermal {
971 polling-delay-passive = <250>;
972 thermal-sensors = <&tsens 5>;
975 nss-critical {
983 wcss-phya0-thermal {
984 polling-delay-passive = <250>;
985 thermal-sensors = <&tsens 7>;
988 wcss-phya0-critical {
996 wcss-phya1-thermal {
997 polling-delay-passive = <250>;
998 polling-delay = <1000>;
999 thermal-sensors = <&tsens 8>;
1002 wcss-phya1-critical {
1010 cpu-thermal {
1011 polling-delay-passive = <250>;
1012 thermal-sensors = <&tsens 13>;
1015 cpu-critical {
1021 cpu_alert: cpu-passive {
1028 cooling-maps {
1031 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1039 lpass-thermal {
1040 polling-delay-passive = <250>;
1041 thermal-sensors = <&tsens 14>;
1044 lpass-critical {
1052 ddrss-top-thermal {
1053 polling-delay-passive = <250>;
1054 thermal-sensors = <&tsens 15>;
1057 ddrss-top-critical {
1067 compatible = "arm,armv8-timer";
1074 wcss: wcss-smp2p {
1078 interrupt-parent = <&intc>;
1083 qcom,local-pid = <0>;
1084 qcom,remote-pid = <1>;
1086 wcss_smp2p_out: master-kernel {
1087 qcom,entry-name = "master-kernel";
1088 #qcom,smem-state-cells = <1>;
1091 wcss_smp2p_in: slave-kernel {
1092 qcom,entry-name = "slave-kernel";
1093 interrupt-controller;
1094 #interrupt-cells = <2>;