Lines Matching refs:gcc
12 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
13 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
237 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
238 <&gcc GCC_PCIE0_AHB_CLK>,
239 <&gcc GCC_PCIE0_PIPE_CLK>;
244 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
247 resets = <&gcc GCC_PCIE0_PHY_BCR>,
248 <&gcc GCC_PCIE0PHY_PHY_BCR>;
263 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
264 <&gcc GCC_PCIE1_AHB_CLK>,
265 <&gcc GCC_PCIE1_PIPE_CLK>;
270 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
273 resets = <&gcc GCC_PCIE1_PHY_BCR>,
274 <&gcc GCC_PCIE1PHY_PHY_BCR>;
289 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
290 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
358 clocks = <&gcc GCC_PCIE2_AUX_CLK>,
359 <&gcc GCC_PCIE2_AHB_CLK>,
360 <&gcc GCC_PCIE2_PIPE_CLK>;
365 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
368 resets = <&gcc GCC_PCIE2_PHY_BCR>,
369 <&gcc GCC_PCIE2PHY_PHY_BCR>;
384 clocks = <&gcc GCC_PCIE3_AUX_CLK>,
385 <&gcc GCC_PCIE3_AHB_CLK>,
386 <&gcc GCC_PCIE3_PIPE_CLK>;
391 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
394 resets = <&gcc GCC_PCIE3_PHY_BCR>,
395 <&gcc GCC_PCIE3PHY_PHY_BCR>;
439 clocks = <&gcc GCC_PRNG_AHB_CLK>;
480 gcc: clock-controller@1800000 { label
481 compatible = "qcom,ipq5424-gcc";
510 clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
511 <&gcc GCC_QUPV3_AHB_SLV_CLK>;
519 clocks = <&gcc GCC_QUPV3_UART0_CLK>;
528 clocks = <&gcc GCC_QUPV3_UART1_CLK>;
536 clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
547 clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
565 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
566 <&gcc GCC_SDCC1_APPS_CLK>,
601 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
605 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
616 clocks = <&gcc GCC_USB1_MASTER_CLK>,
617 <&gcc GCC_USB1_SLEEP_CLK>,
618 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
619 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
620 <&gcc GCC_CNOC_USB_CLK>;
628 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
629 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
642 resets = <&gcc GCC_USB1_BCR>;
649 clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
667 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
671 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
680 clocks = <&gcc GCC_USB0_AUX_CLK>,
682 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
683 <&gcc GCC_USB0_PIPE_CLK>;
689 resets = <&gcc GCC_USB0_PHY_BCR>,
690 <&gcc GCC_USB3PHY_0_PHY_BCR>;
708 clocks = <&gcc GCC_USB0_MASTER_CLK>,
709 <&gcc GCC_USB0_SLEEP_CLK>,
710 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
711 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
712 <&gcc GCC_CNOC_USB_CLK>;
720 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
721 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
734 resets = <&gcc GCC_USB_BCR>;
740 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
818 <&gcc GPLL0>;
829 <&gcc GPLL0_OUT_AUX>,
836 <&gcc GCC_NSSCC_CLK>;
905 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
906 <&gcc GCC_PCIE3_AXI_S_CLK>,
907 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
908 <&gcc GCC_PCIE3_RCHNG_CLK>,
909 <&gcc GCC_PCIE3_AHB_CLK>,
910 <&gcc GCC_PCIE3_AUX_CLK>;
918 assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>;
921 resets = <&gcc GCC_PCIE3_PIPE_ARES>,
922 <&gcc GCC_PCIE3_CORE_STICKY_RESET>,
923 <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>,
924 <&gcc GCC_PCIE3_AXI_S_ARES>,
925 <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>,
926 <&gcc GCC_PCIE3_AXI_M_ARES>,
927 <&gcc GCC_PCIE3_AUX_ARES>,
928 <&gcc GCC_PCIE3_AHB_ARES>;
940 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
941 <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
1008 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
1009 <&gcc GCC_PCIE2_AXI_S_CLK>,
1010 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
1011 <&gcc GCC_PCIE2_RCHNG_CLK>,
1012 <&gcc GCC_PCIE2_AHB_CLK>,
1013 <&gcc GCC_PCIE2_AUX_CLK>;
1021 assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>;
1024 resets = <&gcc GCC_PCIE2_PIPE_ARES>,
1025 <&gcc GCC_PCIE2_CORE_STICKY_RESET>,
1026 <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>,
1027 <&gcc GCC_PCIE2_AXI_S_ARES>,
1028 <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>,
1029 <&gcc GCC_PCIE2_AXI_M_ARES>,
1030 <&gcc GCC_PCIE2_AUX_ARES>,
1031 <&gcc GCC_PCIE2_AHB_ARES>;
1043 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
1044 <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>;
1111 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
1112 <&gcc GCC_PCIE1_AXI_S_CLK>,
1113 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
1114 <&gcc GCC_PCIE1_RCHNG_CLK>,
1115 <&gcc GCC_PCIE1_AHB_CLK>,
1116 <&gcc GCC_PCIE1_AUX_CLK>;
1124 assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>;
1127 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
1128 <&gcc GCC_PCIE1_CORE_STICKY_RESET>,
1129 <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>,
1130 <&gcc GCC_PCIE1_AXI_S_ARES>,
1131 <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>,
1132 <&gcc GCC_PCIE1_AXI_M_ARES>,
1133 <&gcc GCC_PCIE1_AUX_ARES>,
1134 <&gcc GCC_PCIE1_AHB_ARES>;
1146 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
1147 <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>;
1214 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
1215 <&gcc GCC_PCIE0_AXI_S_CLK>,
1216 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
1217 <&gcc GCC_PCIE0_RCHNG_CLK>,
1218 <&gcc GCC_PCIE0_AHB_CLK>,
1219 <&gcc GCC_PCIE0_AUX_CLK>;
1227 assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>;
1230 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
1231 <&gcc GCC_PCIE0_CORE_STICKY_RESET>,
1232 <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>,
1233 <&gcc GCC_PCIE0_AXI_S_ARES>,
1234 <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>,
1235 <&gcc GCC_PCIE0_AXI_M_ARES>,
1236 <&gcc GCC_PCIE0_AUX_ARES>,
1237 <&gcc GCC_PCIE0_AHB_ARES>;
1249 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
1250 <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>;