Lines Matching +full:dload +full:- +full:mode
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/qcom,apss-ipq.h>
11 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
12 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
13 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
14 #include <dt-bindings/interconnect/qcom,ipq5424.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/thermal/thermal.h>
19 #address-cells = <2>;
20 #size-cells = <2>;
21 interrupt-parent = <&intc>;
24 ref_48mhz_clk: ref-48mhz-clk {
25 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
35 xo_board: xo-board-clk {
36 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
41 xo_clk: xo-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
48 #address-cells = <1>;
49 #size-cells = <0>;
53 compatible = "arm,cortex-a55";
55 enable-method = "psci";
56 next-level-cache = <&l2_0>;
58 clock-names = "cpu";
59 operating-points-v2 = <&cpu_opp_table>;
61 #cooling-cells = <2>;
63 l2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&l3_0>;
69 l3_0: l3-cache {
71 cache-level = <3>;
72 cache-unified;
79 compatible = "arm,cortex-a55";
80 enable-method = "psci";
82 next-level-cache = <&l2_100>;
84 clock-names = "cpu";
85 operating-points-v2 = <&cpu_opp_table>;
87 #cooling-cells = <2>;
89 l2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&l3_0>;
99 compatible = "arm,cortex-a55";
100 enable-method = "psci";
102 next-level-cache = <&l2_200>;
104 clock-names = "cpu";
105 operating-points-v2 = <&cpu_opp_table>;
107 #cooling-cells = <2>;
109 l2_200: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&l3_0>;
119 compatible = "arm,cortex-a55";
120 enable-method = "psci";
122 next-level-cache = <&l2_300>;
124 clock-names = "cpu";
125 operating-points-v2 = <&cpu_opp_table>;
127 #cooling-cells = <2>;
129 l2_300: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 next-level-cache = <&l3_0>;
140 compatible = "qcom,scm-ipq5424", "qcom,scm";
141 qcom,dload-mode = <&tcsr 0x25100>;
145 cpu_opp_table: opp-table-cpu {
146 compatible = "operating-points-v2-kryo-cpu";
147 opp-shared;
148 nvmem-cells = <&cpu_speed_bin>;
150 opp-816000000 {
151 opp-hz = /bits/ 64 <816000000>;
152 opp-microvolt = <850000>;
153 opp-supported-hw = <0x3>;
154 clock-latency-ns = <200000>;
155 opp-peak-kBps = <816000>;
158 opp-1416000000 {
159 opp-hz = /bits/ 64 <1416000000>;
160 opp-microvolt = <850000>;
161 opp-supported-hw = <0x3>;
162 clock-latency-ns = <200000>;
163 opp-peak-kBps = <984000>;
166 opp-1800000000 {
167 opp-hz = /bits/ 64 <1800000000>;
168 opp-microvolt = <1000000>;
169 opp-supported-hw = <0x1>;
170 clock-latency-ns = <200000>;
171 opp-peak-kBps = <1272000>;
181 pmu-a55 {
182 compatible = "arm,cortex-a55-pmu";
186 pmu-dsu {
187 compatible = "arm,dsu-pmu";
193 compatible = "arm,psci-1.0";
197 reserved-memory {
198 #address-cells = <2>;
199 #size-cells = <2>;
204 no-map;
209 no-map;
215 no-map;
222 no-map;
228 compatible = "simple-bus";
229 #address-cells = <2>;
230 #size-cells = <2>;
234 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
235 "qcom,ipq9574-qmp-gen3x1-pcie-phy";
240 clock-names = "aux",
244 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
245 assigned-clock-rates = <20000000>;
249 reset-names = "phy",
252 #clock-cells = <0>;
253 clock-output-names = "gcc_pcie0_pipe_clk_src";
255 #phy-cells = <0>;
260 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
261 "qcom,ipq9574-qmp-gen3x1-pcie-phy";
266 clock-names = "aux",
270 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
271 assigned-clock-rates = <20000000>;
275 reset-names = "phy",
278 #clock-cells = <0>;
279 clock-output-names = "gcc_pcie1_pipe_clk_src";
281 #phy-cells = <0>;
285 cmn_pll: clock-controller@9b000 {
286 compatible = "qcom,ipq5424-cmn-pll";
291 clock-names = "ref", "ahb", "sys";
292 #clock-cells = <1>;
293 assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>;
294 assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
298 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
300 #address-cells = <1>;
301 #size-cells = <1>;
338 tsens_mode: mode@419 {
355 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
356 "qcom,ipq9574-qmp-gen3x2-pcie-phy";
361 clock-names = "aux",
365 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
366 assigned-clock-rates = <20000000>;
370 reset-names = "phy",
373 #clock-cells = <0>;
374 clock-output-names = "gcc_pcie2_pipe_clk_src";
376 #phy-cells = <0>;
381 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
382 "qcom,ipq9574-qmp-gen3x2-pcie-phy";
387 clock-names = "aux",
391 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
392 assigned-clock-rates = <20000000>;
396 reset-names = "phy",
399 #clock-cells = <0>;
400 clock-output-names = "gcc_pcie3_pipe_clk_src";
402 #phy-cells = <0>;
406 tsens: thermal-sensor@4a9000 {
407 compatible = "qcom,ipq5424-tsens";
411 interrupt-names = "combined";
412 nvmem-cells = <&tsens_mode>,
422 nvmem-cell-names = "mode",
433 #thermal-sensor-cells = <1>;
437 compatible = "qcom,ipq5424-trng", "qcom,trng";
440 clock-names = "core";
443 system-cache-controller@800000 {
444 compatible = "qcom,ipq5424-llcc";
446 reg-names = "llcc0_base";
451 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
453 #address-cells = <1>;
454 #size-cells = <1>;
456 cpu_speed_bin: cpu-speed-bin@234 {
463 compatible = "qcom,ipq5424-tlmm";
466 gpio-controller;
467 #gpio-cells = <2>;
468 gpio-ranges = <&tlmm 0 0 50>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
472 uart1_pins: uart1-state {
475 drive-strength = <8>;
476 bias-pull-up;
480 gcc: clock-controller@1800000 {
481 compatible = "qcom,ipq5424-gcc";
490 #clock-cells = <1>;
491 #reset-cells = <1>;
492 #interconnect-cells = <1>;
496 compatible = "qcom,tcsr-mutex";
498 #hwlock-cells = <1>;
502 compatible = "qcom,tcsr-ipq5424", "syscon";
507 compatible = "qcom,geni-se-qup";
512 clock-names = "m-ahb", "s-ahb";
513 #address-cells = <2>;
514 #size-cells = <2>;
517 compatible = "qcom,geni-uart";
520 clock-names = "se";
526 compatible = "qcom,geni-debug-uart";
529 clock-names = "se";
534 compatible = "qcom,geni-spi";
537 clock-names = "se";
539 #address-cells = <1>;
540 #size-cells = <0>;
545 compatible = "qcom,geni-spi";
548 clock-names = "se";
550 #address-cells = <1>;
551 #size-cells = <0>;
557 compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
559 reg-names = "hc", "cqhci";
563 interrupt-names = "hc_irq", "pwr_irq";
568 clock-names = "iface", "core", "xo";
570 supports-cqe;
575 intc: interrupt-controller@f200000 {
576 compatible = "arm,gic-v3";
579 #address-cells = <0>;
580 #interrupt-cells = <0x3>;
581 interrupt-controller;
582 #redistributor-regions = <1>;
583 redistributor-stride = <0x0 0x20000>;
585 mbi-ranges = <672 128>;
586 msi-controller;
590 compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
597 compatible = "qcom,ipq5424-qusb2-phy";
599 #phy-cells = <0>;
603 clock-names = "cfg_ahb", "ref";
610 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
612 #address-cells = <2>;
613 #size-cells = <2>;
622 clock-names = "core",
628 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
630 assigned-clock-rates = <200000000>,
633 interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
637 interrupt-names = "pwr_event",
643 qcom,select-utmi-as-pipe-clk;
650 clock-names = "ref";
653 phy-names = "usb2-phy";
654 tx-fifo-resize;
655 snps,is-utmi-l1-suspend;
656 snps,hird-threshold = /bits/ 8 <0x0>;
663 compatible = "qcom,ipq5424-qusb2-phy";
665 #phy-cells = <0>;
669 clock-names = "cfg_ahb", "ref";
676 compatible = "qcom,ipq5424-qmp-usb3-phy";
678 #phy-cells = <0>;
684 clock-names = "aux",
691 reset-names = "phy",
694 #clock-cells = <0>;
695 clock-output-names = "usb0_pipe_clk";
701 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
704 #address-cells = <2>;
705 #size-cells = <2>;
714 clock-names = "core",
720 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
722 assigned-clock-rates = <200000000>,
725 interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
729 interrupt-names = "pwr_event",
741 clock-names = "ref";
744 phy-names = "usb2-phy", "usb3-phy";
745 tx-fifo-resize;
746 snps,is-utmi-l1-suspend;
747 snps,hird-threshold = /bits/ 8 <0x0>;
750 snps,dis-u1-entry-quirk;
751 snps,dis-u2-entry-quirk;
756 compatible = "arm,armv7-timer-mem";
759 #address-cells = <1>;
760 #size-cells = <1>;
767 frame-number = <0>;
773 frame-number = <1>;
781 frame-number = <2>;
788 frame-number = <3>;
795 frame-number = <4>;
802 frame-number = <5>;
809 frame-number = <6>;
814 apss_clk: clock-controller@fa80000 {
815 compatible = "qcom,ipq5424-apss-clk";
819 #clock-cells = <1>;
820 #interconnect-cells = <1>;
823 clock-controller@39b00000 {
824 compatible = "qcom,ipq5424-nsscc";
837 clock-names = "xo",
848 #clock-cells = <1>;
849 #reset-cells = <1>;
850 #interconnect-cells = <1>;
854 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
861 reg-names = "dbi",
868 linux,pci-domain = <3>;
869 num-lanes = <2>;
870 #address-cells = <3>;
871 #size-cells = <2>;
876 msi-map = <0x0 &intc 0x0 0x1000>;
888 interrupt-names = "msi0",
898 #interrupt-cells = <1>;
899 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
900 interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
911 clock-names = "axi_m",
918 assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>;
919 assigned-clock-rates = <100000000>;
929 reset-names = "pipe",
939 phy-names = "pciephy";
942 interconnect-names = "pcie-mem", "cpu-pcie";
949 bus-range = <0x01 0xff>;
951 #address-cells = <3>;
952 #size-cells = <2>;
958 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
965 reg-names = "dbi",
972 linux,pci-domain = <2>;
973 num-lanes = <2>;
974 #address-cells = <3>;
975 #size-cells = <2>;
980 msi-map = <0x0 &intc 0x0 0x1000>;
991 interrupt-names = "msi0",
1001 #interrupt-cells = <1>;
1002 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1003 interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
1014 clock-names = "axi_m",
1021 assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>;
1022 assigned-clock-rates = <100000000>;
1032 reset-names = "pipe",
1042 phy-names = "pciephy";
1045 interconnect-names = "pcie-mem", "cpu-pcie";
1052 bus-range = <0x01 0xff>;
1054 #address-cells = <3>;
1055 #size-cells = <2>;
1061 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
1068 reg-names = "dbi",
1075 linux,pci-domain = <1>;
1076 num-lanes = <1>;
1077 #address-cells = <3>;
1078 #size-cells = <2>;
1083 msi-map = <0x0 &intc 0x0 0x1000>;
1094 interrupt-names = "msi0",
1104 #interrupt-cells = <1>;
1105 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1106 interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
1117 clock-names = "axi_m",
1124 assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>;
1125 assigned-clock-rates = <100000000>;
1135 reset-names = "pipe",
1145 phy-names = "pciephy";
1148 interconnect-names = "pcie-mem", "cpu-pcie";
1155 bus-range = <0x01 0xff>;
1157 #address-cells = <3>;
1158 #size-cells = <2>;
1164 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
1171 reg-names = "dbi",
1178 linux,pci-domain = <0>;
1179 num-lanes = <1>;
1180 #address-cells = <3>;
1181 #size-cells = <2>;
1186 msi-map = <0x0 &intc 0x0 0x1000>;
1197 interrupt-names = "msi0",
1207 #interrupt-cells = <1>;
1208 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1209 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1220 clock-names = "axi_m",
1227 assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>;
1228 assigned-clock-rates = <100000000>;
1238 reset-names = "pipe",
1248 phy-names = "pciephy";
1251 interconnect-names = "pcie-mem", "cpu-pcie";
1258 bus-range = <0x01 0xff>;
1260 #address-cells = <3>;
1261 #size-cells = <2>;
1267 thermal_zones: thermal-zones {
1268 cpu0-thermal {
1269 polling-delay-passive = <100>;
1270 thermal-sensors = <&tsens 14>;
1273 cpu0_crit: cpu-critical {
1279 cpu0_alert: cpu-passive {
1286 cooling-maps {
1289 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1297 cpu1-thermal {
1298 polling-delay-passive = <100>;
1299 thermal-sensors = <&tsens 12>;
1302 cpu1_crit: cpu-critical {
1308 cpu1_alert: cpu-passive {
1315 cooling-maps {
1318 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1326 cpu2-thermal {
1327 polling-delay-passive = <100>;
1328 thermal-sensors = <&tsens 11>;
1331 cpu2_crit: cpu-critical {
1337 cpu2_alert: cpu-passive {
1344 cooling-maps {
1347 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1355 cpu3-thermal {
1356 polling-delay-passive = <100>;
1357 thermal-sensors = <&tsens 13>;
1360 cpu3_crit: cpu-critical {
1366 cpu3_alert: cpu-passive {
1373 cooling-maps {
1376 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1384 wcss-tile2-thermal {
1385 thermal-sensors = <&tsens 9>;
1388 wcss-tile2-critical {
1396 wcss-tile3-thermal {
1397 thermal-sensors = <&tsens 10>;
1400 wcss-tile3-critical {
1408 top-glue-thermal {
1409 thermal-sensors = <&tsens 15>;
1412 top-glue-critical {
1422 compatible = "arm,armv8-timer";