Lines Matching +full:ns +full:- +full:thermal
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interconnect/qcom,ipq5332.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
24 xo_board: xo-board-clk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 next-level-cache = <&l2_0>;
41 operating-points-v2 = <&cpu_opp_table>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 next-level-cache = <&l2_0>;
51 operating-points-v2 = <&cpu_opp_table>;
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 next-level-cache = <&l2_0>;
61 operating-points-v2 = <&cpu_opp_table>;
66 compatible = "arm,cortex-a53";
68 enable-method = "psci";
69 next-level-cache = <&l2_0>;
71 operating-points-v2 = <&cpu_opp_table>;
74 l2_0: l2-cache {
76 cache-level = <2>;
77 cache-unified;
83 compatible = "qcom,scm-ipq5332", "qcom,scm";
84 qcom,dload-mode = <&tcsr 0x6100>;
94 cpu_opp_table: opp-table-cpu {
95 compatible = "operating-points-v2-kryo-cpu";
96 opp-shared;
97 nvmem-cells = <&cpu_speed_bin>;
99 opp-1100000000 {
100 opp-hz = /bits/ 64 <1100000000>;
101 opp-supported-hw = <0x7>;
102 clock-latency-ns = <200000>;
105 opp-1500000000 {
106 opp-hz = /bits/ 64 <1500000000>;
107 opp-supported-hw = <0x3>;
108 clock-latency-ns = <200000>;
113 compatible = "arm,cortex-a53-pmu";
118 compatible = "arm,psci-1.0";
122 reserved-memory {
123 #address-cells = <2>;
124 #size-cells = <2>;
129 no-map;
134 no-map;
139 no-map;
145 no-map;
152 compatible = "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
158 compatible = "qcom,ipq5332-usb-hsphy";
165 #phy-cells = <0>;
171 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
173 #address-cells = <1>;
174 #size-cells = <1>;
176 cpu_speed_bin: cpu-speed-bin@1d {
223 compatible = "qcom,ipq5332-trng", "qcom,trng";
226 clock-names = "core";
229 tsens: thermal-sensor@4a9000 {
230 compatible = "qcom,ipq5332-tsens";
234 interrupt-names = "combined";
235 nvmem-cells = <&tsens_mode>,
243 nvmem-cell-names = "mode",
252 #thermal-sensor-cells = <1>;
256 compatible = "qcom,ipq5332-uniphy-pcie-phy";
266 #clock-cells = <0>;
268 #phy-cells = <0>;
270 num-lanes = <1>;
276 compatible = "qcom,ipq5332-uniphy-pcie-phy";
286 #clock-cells = <0>;
288 #phy-cells = <0>;
290 num-lanes = <2>;
296 compatible = "qcom,ipq5332-tlmm";
299 gpio-controller;
300 #gpio-cells = <2>;
301 gpio-ranges = <&tlmm 0 0 53>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
305 serial_0_pins: serial0-state {
308 drive-strength = <8>;
309 bias-pull-up;
313 gcc: clock-controller@1800000 {
314 compatible = "qcom,ipq5332-gcc";
316 #clock-cells = <1>;
317 #reset-cells = <1>;
318 #interconnect-cells = <1>;
327 compatible = "qcom,tcsr-mutex";
329 #hwlock-cells = <1>;
333 compatible = "qcom,tcsr-ipq5332", "syscon";
338 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
343 interrupt-names = "hc_irq", "pwr_irq";
348 clock-names = "iface", "core", "xo";
352 blsp_dma: dma-controller@7884000 {
353 compatible = "qcom,bam-v1.7.0";
357 clock-names = "bam_clk";
358 #dma-cells = <1>;
363 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
368 clock-names = "core", "iface";
373 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
378 clock-names = "core", "iface";
380 dma-names = "tx", "rx";
385 compatible = "qcom,spi-qup-v2.2.1";
387 #address-cells = <1>;
388 #size-cells = <0>;
392 clock-names = "core", "iface";
394 dma-names = "tx", "rx";
399 compatible = "qcom,i2c-qup-v2.2.1";
401 #address-cells = <1>;
402 #size-cells = <0>;
406 clock-names = "core", "iface";
408 dma-names = "tx", "rx";
413 compatible = "qcom,spi-qup-v2.2.1";
415 #address-cells = <1>;
416 #size-cells = <0>;
420 clock-names = "core", "iface";
422 dma-names = "tx", "rx";
427 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
433 interrupt-names = "pwr_event",
440 clock-names = "core",
446 qcom,select-utmi-as-pipe-clk;
448 #address-cells = <1>;
449 #size-cells = <1>;
453 interconnect-names = "usb-ddr", "apps-usb";
461 clock-names = "ref";
463 phy-names = "usb2-phy";
465 tx-fifo-resize;
466 snps,is-utmi-l1-suspend;
467 snps,hird-threshold = /bits/ 8 <0x0>;
473 intc: interrupt-controller@b000000 {
474 compatible = "qcom,msm-qgic2";
480 interrupt-controller;
481 #interrupt-cells = <3>;
482 #address-cells = <1>;
483 #size-cells = <1>;
487 compatible = "arm,gic-v2m-frame";
489 msi-controller;
493 compatible = "arm,gic-v2m-frame";
495 msi-controller;
499 compatible = "arm,gic-v2m-frame";
501 msi-controller;
506 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
510 timeout-sec = <30>;
514 compatible = "qcom,ipq5332-apcs-apps-global",
515 "qcom,ipq6018-apcs-apps-global";
517 #clock-cells = <1>;
519 clock-names = "pll", "xo", "gpll0";
520 #mbox-cells = <1>;
524 compatible = "qcom,ipq5332-a53pll";
526 #clock-cells = <0>;
528 clock-names = "xo";
532 compatible = "arm,armv7-timer-mem";
534 #address-cells = <1>;
535 #size-cells = <1>;
543 frame-number = <0>;
549 frame-number = <1>;
556 frame-number = <2>;
563 frame-number = <3>;
570 frame-number = <4>;
577 frame-number = <5>;
584 frame-number = <6>;
590 compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
597 reg-names = "dbi",
604 linux,pci-domain = <1>;
605 num-lanes = <2>;
606 #address-cells = <3>;
607 #size-cells = <2>;
612 msi-map = <0x0 &v2m0 0x0 0xffd>;
623 interrupt-names = "msi0",
633 #interrupt-cells = <1>;
634 interrupt-map-mask = <0 0 0 0x7>;
635 interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
646 clock-names = "axi_m",
653 assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>;
655 assigned-clock-rates = <2000000>;
665 reset-names = "pipe",
675 phy-names = "pciephy";
679 interconnect-names = "pcie-mem", "cpu-pcie";
687 #address-cells = <3>;
688 #size-cells = <2>;
694 compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
701 reg-names = "dbi",
708 linux,pci-domain = <0>;
709 num-lanes = <1>;
710 #address-cells = <3>;
711 #size-cells = <2>;
716 msi-map = <0x0 &v2m0 0x0 0xffd>;
727 interrupt-names = "msi0",
737 #interrupt-cells = <1>;
738 interrupt-map-mask = <0 0 0 0x7>;
739 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
750 clock-names = "axi_m",
757 assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>;
759 assigned-clock-rates = <2000000>;
769 reset-names = "pipe",
779 phy-names = "pciephy";
783 interconnect-names = "pcie-mem", "cpu-pcie";
791 #address-cells = <3>;
792 #size-cells = <2>;
798 thermal-zones {
799 rfa-0-thermal {
800 thermal-sensors = <&tsens 11>;
803 rfa-0-critical {
811 rfa-1-thermal {
812 thermal-sensors = <&tsens 12>;
815 rfa-1-critical {
823 misc-thermal {
824 thermal-sensors = <&tsens 13>;
827 misc-critical {
835 cpu-top-thermal {
836 polling-delay-passive = <100>;
837 thermal-sensors = <&tsens 14>;
840 cpu-top-critical {
846 cpu-passive {
854 top-glue-thermal {
855 thermal-sensors = <&tsens 15>;
858 top-glue-critical {
868 compatible = "arm,armv8-timer";