Lines Matching +full:0 +full:x004a8000
21 #clock-cells = <0>;
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
47 reg = <0x1>;
57 reg = <0x2>;
67 reg = <0x3>;
84 qcom,dload-mode = <&tcsr 0x6100>;
91 reg = <0x0 0x40000000 0x0 0x0>;
101 opp-supported-hw = <0x7>;
107 opp-supported-hw = <0x3>;
128 reg = <0x0 0x4a100000 0x0 0x400000>;
133 reg = <0x0 0x4a500000 0x0 0x100000>;
138 reg = <0x0 0x4a600000 0x0 0x200000>;
144 reg = <0x0 0x4a800000 0x0 0x100000>;
151 soc@0 {
155 ranges = <0 0 0 0xffffffff>;
159 reg = <0x0007b000 0x12c>;
165 #phy-cells = <0>;
172 reg = <0x000a4000 0x721>;
177 reg = <0x1d 0x2>;
182 reg = <0x3a5 0x1>;
187 reg = <0x3a6 0x1>;
188 bits = <0 4>;
192 reg = <0x3a6 0x1>;
197 reg = <0x3ad 0x2>;
202 reg = <0x3ae 0x1>;
207 reg = <0x3e1 0x1>;
208 bits = <0 3>;
212 reg = <0x3e1 0x2>;
217 reg = <0x3e2 0x2>;
224 reg = <0x000e3000 0x1000>;
231 reg = <0x004a9000 0x1000>,
232 <0x004a8000 0x1000>;
257 reg = <0x004b0000 0x800>;
266 #clock-cells = <0>;
268 #phy-cells = <0>;
277 reg = <0x004b1000 0x1000>;
286 #clock-cells = <0>;
288 #phy-cells = <0>;
297 reg = <0x01000000 0x300000>;
301 gpio-ranges = <&tlmm 0 0 53>;
315 reg = <0x01800000 0x80000>;
323 <0>;
328 reg = <0x01905000 0x20000>;
334 reg = <0x01937000 0x21000>;
339 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
354 reg = <0x07884000 0x1d000>;
359 qcom,ee = <0>;
364 reg = <0x078af000 0x200>;
374 reg = <0x078b0000 0x200>;
386 reg = <0x078b5000 0x600>;
388 #size-cells = <0>;
400 reg = <0x078b6000 0x600>;
402 #size-cells = <0>;
414 reg = <0x078b7000 0x600>;
416 #size-cells = <0>;
428 reg = <0x08af8800 0x400>;
459 reg = <0x08a00000 0xe000>;
467 snps,hird-threshold = /bits/ 8 <0x0>;
475 reg = <0x0b000000 0x1000>, /* GICD */
476 <0x0b002000 0x1000>, /* GICC */
477 <0x0b001000 0x1000>, /* GICH */
478 <0x0b004000 0x1000>; /* GICV */
484 ranges = <0 0x0b00c000 0x3000>;
486 v2m0: v2m@0 {
488 reg = <0x00000000 0xffd>;
494 reg = <0x00001000 0xffd>;
500 reg = <0x00002000 0xffd>;
507 reg = <0x0b017000 0x1000>;
516 reg = <0x0b111000 0x1000>;
525 reg = <0x0b116000 0x40>;
526 #clock-cells = <0>;
533 reg = <0x0b120000 0x1000>;
539 reg = <0x0b121000 0x1000>,
540 <0x0b122000 0x1000>;
543 frame-number = <0>;
547 reg = <0x0b123000 0x1000>;
554 reg = <0x0b124000 0x1000>;
561 reg = <0x0b125000 0x1000>;
568 reg = <0x0b126000 0x1000>;
575 reg = <0x0b127000 0x1000>;
582 reg = <0x0b128000 0x1000>;
591 reg = <0x18000000 0xf1c>,
592 <0x18000f20 0xa8>,
593 <0x18001000 0x1000>,
594 <0x00088000 0x3000>,
595 <0x18100000 0x1000>,
596 <0x0008b000 0x1000>;
609 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>,
610 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
612 msi-map = <0x0 &v2m0 0x0 0xffd>;
634 interrupt-map-mask = <0 0 0 0x7>;
635 interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
636 <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
637 <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
638 <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
683 pcie@0 {
685 reg = <0x0 0x0 0x0 0x0 0x0>;
695 reg = <0x20000000 0xf1c>,
696 <0x20000f20 0xa8>,
697 <0x20001000 0x1000>,
698 <0x00080000 0x3000>,
699 <0x20100000 0x1000>,
700 <0x00083000 0x1000>;
708 linux,pci-domain = <0>;
713 ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>,
714 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>;
716 msi-map = <0x0 &v2m0 0x0 0xffd>;
738 interrupt-map-mask = <0 0 0 0x7>;
739 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
740 <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
741 <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
742 <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
787 pcie@0 {
789 reg = <0x0 0x0 0x0 0x0 0x0>;
799 rfa-0-thermal {
803 rfa-0-critical {