Lines Matching +full:gpio10 +full:- +full:pins
1 // SPDX-License-Identifier: BSD-3-Clause
3 * IPQ5332 AP-MI01.2 board device tree source
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
18 clock-frequency = <400000>;
19 pinctrl-0 = <&i2c_1_pins>;
20 pinctrl-names = "default";
25 bus-width = <4>;
26 max-frequency = <192000000>;
27 mmc-ddr-1_8v;
28 mmc-hs200-1_8v;
29 non-removable;
30 pinctrl-0 = <&sdc_default_state>;
31 pinctrl-names = "default";
36 pinctrl-0 = <&pcie0_default>;
37 pinctrl-names = "default";
39 perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
40 wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
50 pinctrl-0 = <&pcie1_default>;
51 pinctrl-names = "default";
53 perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
54 wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
64 i2c_1_pins: i2c-1-state {
65 pins = "gpio29", "gpio30";
67 drive-strength = <8>;
68 bias-pull-up;
71 pcie0_default: pcie0-default-state {
72 clkreq-n-pins {
73 pins = "gpio37";
75 drive-strength = <8>;
76 bias-pull-up;
79 perst-n-pins {
80 pins = "gpio38";
82 drive-strength = <8>;
83 bias-pull-up;
84 output-low;
87 wake-n-pins {
88 pins = "gpio39";
90 drive-strength = <8>;
91 bias-pull-up;
95 pcie1_default: pcie1-default-state {
96 clkreq-n-pins {
97 pins = "gpio46";
99 drive-strength = <8>;
100 bias-pull-up;
103 perst-n-pins {
104 pins = "gpio47";
106 drive-strength = <8>;
107 bias-pull-up;
108 output-low;
111 wake-n-pins {
112 pins = "gpio48";
114 drive-strength = <8>;
115 bias-pull-up;
119 sdc_default_state: sdc-default-state {
120 clk-pins {
121 pins = "gpio13";
123 drive-strength = <8>;
124 bias-disable;
127 cmd-pins {
128 pins = "gpio12";
130 drive-strength = <8>;
131 bias-pull-up;
134 data-pins {
135 pins = "gpio8", "gpio9", "gpio10", "gpio11";
137 drive-strength = <8>;
138 bias-pull-up;