Lines Matching refs:gcc
10 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
797 gcc: clock-controller@100000 { label
798 compatible = "qcom,x1e80100-gcc";
886 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
887 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
905 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
941 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
977 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1013 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1049 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1085 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1121 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1157 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1193 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1229 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1265 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1301 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1337 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1362 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1398 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1434 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1470 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1531 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1532 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1550 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1586 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1622 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1658 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1694 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1730 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1766 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1802 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1838 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1874 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1910 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1946 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1982 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2018 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2054 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2079 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2115 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2176 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
2177 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
2194 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2230 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2266 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2302 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2338 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2374 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2399 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2435 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2507 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2543 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2579 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2615 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2651 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2687 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2723 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2759 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2859 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2868 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2870 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2871 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2877 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2879 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2880 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
2930 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2939 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2941 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2942 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2948 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2950 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2951 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
3001 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
3010 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
3012 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
3013 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
3019 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
3021 resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
3022 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
3224 clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
3225 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
3226 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
3227 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
3228 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
3229 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3230 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3239 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
3249 resets = <&gcc GCC_PCIE_3_BCR>,
3250 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
3254 power-domains = <&gcc GCC_PCIE_3_GDSC>;
3415 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
3416 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
3418 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
3419 <&gcc GCC_PCIE_3_PIPE_CLK>,
3420 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
3428 resets = <&gcc GCC_PCIE_3_PHY_BCR>,
3429 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
3433 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
3436 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
3500 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
3501 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3502 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
3503 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
3504 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
3505 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
3506 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
3515 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
3525 resets = <&gcc GCC_PCIE_6A_BCR>,
3526 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
3530 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
3547 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
3548 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3550 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
3551 <&gcc GCC_PCIE_6A_PIPE_CLK>,
3552 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
3560 resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
3561 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
3565 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3568 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3632 clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3633 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3634 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
3635 <&gcc GCC_PCIE_5_SLV_AXI_CLK>,
3636 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
3637 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3638 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3647 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3657 resets = <&gcc GCC_PCIE_5_BCR>,
3658 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
3662 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3677 clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3678 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3680 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
3681 <&gcc GCC_PCIE_5_PIPE_CLK>,
3682 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>;
3690 resets = <&gcc GCC_PCIE_5_PHY_BCR>,
3691 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
3695 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3698 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3762 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3763 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3764 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
3765 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
3766 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
3767 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3768 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3777 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3787 resets = <&gcc GCC_PCIE_4_BCR>,
3788 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
3792 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3817 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3818 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3820 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
3821 <&gcc GCC_PCIE_4_PIPE_CLK>,
3822 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
3830 resets = <&gcc GCC_PCIE_4_PHY_BCR>,
3831 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
3835 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3838 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
4035 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4036 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4077 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
4078 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
4117 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4118 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
4665 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4666 <&gcc GCC_SDCC2_APPS_CLK>,
4718 clocks = <&gcc GCC_SDCC4_AHB_CLK>,
4719 <&gcc GCC_SDCC4_APPS_CLK>,
4772 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
4786 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
4800 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
4809 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
4811 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
4812 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
4818 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
4819 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
4823 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
4837 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
4839 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
4840 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
4846 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
4847 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
4851 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
4865 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
4866 <&gcc GCC_USB30_TERT_MASTER_CLK>,
4867 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
4868 <&gcc GCC_USB30_TERT_SLEEP_CLK>,
4869 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4870 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4871 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4872 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4873 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4884 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4885 <&gcc GCC_USB30_TERT_MASTER_CLK>;
4898 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4901 resets = <&gcc GCC_USB30_TERT_BCR>;
4968 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
4969 <&gcc GCC_USB20_MASTER_CLK>,
4970 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
4971 <&gcc GCC_USB20_SLEEP_CLK>,
4972 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4973 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4974 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4975 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4976 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4987 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4988 <&gcc GCC_USB20_MASTER_CLK>;
4998 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
5001 resets = <&gcc GCC_USB20_PRIM_BCR>;
5039 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
5040 <&gcc GCC_USB30_MP_MASTER_CLK>,
5041 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
5042 <&gcc GCC_USB30_MP_SLEEP_CLK>,
5043 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
5044 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
5045 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
5046 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
5047 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
5058 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
5059 <&gcc GCC_USB30_MP_MASTER_CLK>;
5079 power-domains = <&gcc GCC_USB30_MP_GDSC>;
5082 resets = <&gcc GCC_USB30_MP_BCR>;
5127 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
5128 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
5129 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
5130 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
5131 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5132 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
5133 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
5134 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
5135 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
5146 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5147 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
5160 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
5163 resets = <&gcc GCC_USB30_PRIM_BCR>;
5220 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
5221 <&gcc GCC_USB30_SEC_MASTER_CLK>,
5222 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
5223 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
5224 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
5225 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
5226 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
5227 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
5228 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
5239 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
5240 <&gcc GCC_USB30_SEC_MASTER_CLK>;
5253 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
5256 resets = <&gcc GCC_USB30_SEC_BCR>;
5332 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
5348 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
5407 <&gcc GCC_VIDEO_AHB_CLK>;
5425 <&gcc GCC_DISP_HF_AXI_CLK>,
5462 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5936 <&gcc GCC_DISP_AHB_CLK>,