Lines Matching +full:pdc +full:- +full:intc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
12 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/soc/qcom,gpr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 #include <dt-bindings/thermal/thermal.h>
27 interrupt-parent = <&intc>;
29 #address-cells = <2>;
30 #size-cells = <2>;
35 xo_board: xo-board {
36 compatible = "fixed-clock";
37 clock-frequency = <76800000>;
38 #clock-cells = <0>;
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 clock-frequency = <32764>;
44 #clock-cells = <0>;
47 bi_tcxo_div2: bi-tcxo-div2-clk {
48 compatible = "fixed-factor-clock";
49 #clock-cells = <0>;
52 clock-mult = <1>;
53 clock-div = <2>;
56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
57 compatible = "fixed-factor-clock";
58 #clock-cells = <0>;
61 clock-mult = <1>;
62 clock-div = <2>;
67 #address-cells = <2>;
68 #size-cells = <0>;
74 enable-method = "psci";
75 next-level-cache = <&l2_0>;
76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
77 power-domain-names = "psci", "perf";
79 l2_0: l2-cache {
81 cache-level = <2>;
82 cache-unified;
90 enable-method = "psci";
91 next-level-cache = <&l2_0>;
92 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
93 power-domain-names = "psci", "perf";
100 enable-method = "psci";
101 next-level-cache = <&l2_0>;
102 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
103 power-domain-names = "psci", "perf";
110 enable-method = "psci";
111 next-level-cache = <&l2_0>;
112 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
113 power-domain-names = "psci", "perf";
120 enable-method = "psci";
121 next-level-cache = <&l2_1>;
122 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
123 power-domain-names = "psci", "perf";
125 l2_1: l2-cache {
127 cache-level = <2>;
128 cache-unified;
136 enable-method = "psci";
137 next-level-cache = <&l2_1>;
138 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
139 power-domain-names = "psci", "perf";
146 enable-method = "psci";
147 next-level-cache = <&l2_1>;
148 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
149 power-domain-names = "psci", "perf";
156 enable-method = "psci";
157 next-level-cache = <&l2_1>;
158 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
159 power-domain-names = "psci", "perf";
166 enable-method = "psci";
167 next-level-cache = <&l2_2>;
168 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
169 power-domain-names = "psci", "perf";
171 l2_2: l2-cache {
173 cache-level = <2>;
174 cache-unified;
182 enable-method = "psci";
183 next-level-cache = <&l2_2>;
184 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
185 power-domain-names = "psci", "perf";
192 enable-method = "psci";
193 next-level-cache = <&l2_2>;
194 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
195 power-domain-names = "psci", "perf";
202 enable-method = "psci";
203 next-level-cache = <&l2_2>;
204 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
205 power-domain-names = "psci", "perf";
208 cpu-map {
264 idle-states {
265 entry-method = "psci";
267 cluster_c4: cpu-sleep-0 {
268 compatible = "arm,idle-state";
269 idle-state-name = "ret";
270 arm,psci-suspend-param = <0x00000004>;
271 entry-latency-us = <180>;
272 exit-latency-us = <500>;
273 min-residency-us = <600>;
277 domain-idle-states {
278 cluster_cl4: cluster-sleep-0 {
279 compatible = "domain-idle-state";
280 arm,psci-suspend-param = <0x01000044>;
281 entry-latency-us = <350>;
282 exit-latency-us = <500>;
283 min-residency-us = <2500>;
286 cluster_cl5: cluster-sleep-1 {
287 compatible = "domain-idle-state";
288 arm,psci-suspend-param = <0x01000054>;
289 entry-latency-us = <2200>;
290 exit-latency-us = <4000>;
291 min-residency-us = <7000>;
296 dummy-sink {
297 compatible = "arm,coresight-dummy-sink";
299 in-ports {
302 remote-endpoint = <&swao_rep_out1>;
310 compatible = "qcom,scm-x1e80100", "qcom,scm";
313 qcom,dload-mode = <&tcsr 0x19000>;
319 mbox-names = "tx", "rx";
322 #address-cells = <1>;
323 #size-cells = <0>;
327 #power-domain-cells = <1>;
332 clk_virt: interconnect-0 {
333 compatible = "qcom,x1e80100-clk-virt";
334 #interconnect-cells = <2>;
335 qcom,bcm-voters = <&apps_bcm_voter>;
338 mc_virt: interconnect-1 {
339 compatible = "qcom,x1e80100-mc-virt";
340 #interconnect-cells = <2>;
341 qcom,bcm-voters = <&apps_bcm_voter>;
351 compatible = "arm,armv8-pmuv3";
356 compatible = "arm,psci-1.0";
359 cpu_pd0: power-domain-cpu0 {
360 #power-domain-cells = <0>;
361 power-domains = <&cluster_pd0>;
362 domain-idle-states = <&cluster_c4>;
365 cpu_pd1: power-domain-cpu1 {
366 #power-domain-cells = <0>;
367 power-domains = <&cluster_pd0>;
368 domain-idle-states = <&cluster_c4>;
371 cpu_pd2: power-domain-cpu2 {
372 #power-domain-cells = <0>;
373 power-domains = <&cluster_pd0>;
374 domain-idle-states = <&cluster_c4>;
377 cpu_pd3: power-domain-cpu3 {
378 #power-domain-cells = <0>;
379 power-domains = <&cluster_pd0>;
380 domain-idle-states = <&cluster_c4>;
383 cpu_pd4: power-domain-cpu4 {
384 #power-domain-cells = <0>;
385 power-domains = <&cluster_pd1>;
386 domain-idle-states = <&cluster_c4>;
389 cpu_pd5: power-domain-cpu5 {
390 #power-domain-cells = <0>;
391 power-domains = <&cluster_pd1>;
392 domain-idle-states = <&cluster_c4>;
395 cpu_pd6: power-domain-cpu6 {
396 #power-domain-cells = <0>;
397 power-domains = <&cluster_pd1>;
398 domain-idle-states = <&cluster_c4>;
401 cpu_pd7: power-domain-cpu7 {
402 #power-domain-cells = <0>;
403 power-domains = <&cluster_pd1>;
404 domain-idle-states = <&cluster_c4>;
407 cpu_pd8: power-domain-cpu8 {
408 #power-domain-cells = <0>;
409 power-domains = <&cluster_pd2>;
410 domain-idle-states = <&cluster_c4>;
413 cpu_pd9: power-domain-cpu9 {
414 #power-domain-cells = <0>;
415 power-domains = <&cluster_pd2>;
416 domain-idle-states = <&cluster_c4>;
419 cpu_pd10: power-domain-cpu10 {
420 #power-domain-cells = <0>;
421 power-domains = <&cluster_pd2>;
422 domain-idle-states = <&cluster_c4>;
425 cpu_pd11: power-domain-cpu11 {
426 #power-domain-cells = <0>;
427 power-domains = <&cluster_pd2>;
428 domain-idle-states = <&cluster_c4>;
431 cluster_pd0: power-domain-cpu-cluster0 {
432 #power-domain-cells = <0>;
433 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
434 power-domains = <&system_pd>;
437 cluster_pd1: power-domain-cpu-cluster1 {
438 #power-domain-cells = <0>;
439 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
440 power-domains = <&system_pd>;
443 cluster_pd2: power-domain-cpu-cluster2 {
444 #power-domain-cells = <0>;
445 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
446 power-domains = <&system_pd>;
449 system_pd: power-domain-system {
450 #power-domain-cells = <0>;
451 /* TODO: system-wide idle states */
455 reserved-memory {
456 #address-cells = <2>;
457 #size-cells = <2>;
460 gunyah_hyp_mem: gunyah-hyp@80000000 {
462 no-map;
465 hyp_elf_package_mem: hyp-elf-package@80800000 {
467 no-map;
472 no-map;
475 cpucp_log_mem: cpucp-log@80e00000 {
477 no-map;
482 no-map;
485 reserved-region@81380000 {
487 no-map;
490 tags_mem: tags-region@81400000 {
492 no-map;
495 xbl_dtlog_mem: xbl-dtlog@81a00000 {
497 no-map;
500 xbl_ramdump_mem: xbl-ramdump@81a40000 {
502 no-map;
505 aop_image_mem: aop-image@81c00000 {
507 no-map;
510 aop_cmd_db_mem: aop-cmd-db@81c60000 {
511 compatible = "qcom,cmd-db";
513 no-map;
516 aop_config_mem: aop-config@81c80000 {
518 no-map;
521 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
523 no-map;
526 tme_log_mem: tme-log@81ce0000 {
528 no-map;
531 uefi_log_mem: uefi-log@81ce4000 {
533 no-map;
536 secdata_apss_mem: secdata-apss@81cff000 {
538 no-map;
541 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
543 no-map;
546 gpu_prr_mem: gpu-prr@81f00000 {
548 no-map;
551 tpm_control_mem: tpm-control@81f10000 {
553 no-map;
556 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
558 no-map;
561 pld_pep_mem: pld-pep@81f30000 {
563 no-map;
566 pld_gmu_mem: pld-gmu@81f36000 {
568 no-map;
571 pld_pdp_mem: pld-pdp@81f37000 {
573 no-map;
576 tz_stat_mem: tz-stat@82700000 {
578 no-map;
581 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
583 no-map;
586 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
588 no-map;
591 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
593 no-map;
596 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
598 no-map;
601 spss_region_mem: spss-region@86700000 {
603 no-map;
606 adsp_boot_mem: adsp-boot@86b00000 {
608 no-map;
613 no-map;
618 no-map;
621 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
623 no-map;
628 no-map;
631 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
633 no-map;
636 gpu_microcode_mem: gpu-microcode@8d9fe000 {
638 no-map;
643 no-map;
648 no-map;
651 av1_encoder_mem: av1-encoder@8e900000 {
653 no-map;
656 reserved-region@8f000000 {
658 no-map;
663 no-map;
666 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
668 no-map;
671 xbl_sc_mem: xbl-sc@d8000000 {
673 no-map;
676 reserved-region@d8040000 {
678 no-map;
683 no-map;
688 no-map;
693 no-map;
696 llcc_lpi_mem: llcc-lpi@ff800000 {
698 no-map;
705 no-map;
709 qup_opp_table_100mhz: opp-table-qup100mhz {
710 compatible = "operating-points-v2";
712 opp-75000000 {
713 opp-hz = /bits/ 64 <75000000>;
714 required-opps = <&rpmhpd_opp_low_svs>;
717 opp-100000000 {
718 opp-hz = /bits/ 64 <100000000>;
719 required-opps = <&rpmhpd_opp_svs>;
723 qup_opp_table_120mhz: opp-table-qup120mhz {
724 compatible = "operating-points-v2";
726 opp-75000000 {
727 opp-hz = /bits/ 64 <75000000>;
728 required-opps = <&rpmhpd_opp_low_svs>;
731 opp-120000000 {
732 opp-hz = /bits/ 64 <120000000>;
733 required-opps = <&rpmhpd_opp_svs>;
737 smp2p-adsp {
740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
748 qcom,local-pid = <0>;
749 qcom,remote-pid = <2>;
751 smp2p_adsp_out: master-kernel {
752 qcom,entry-name = "master-kernel";
753 #qcom,smem-state-cells = <1>;
756 smp2p_adsp_in: slave-kernel {
757 qcom,entry-name = "slave-kernel";
758 interrupt-controller;
759 #interrupt-cells = <2>;
763 smp2p-cdsp {
766 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
774 qcom,local-pid = <0>;
775 qcom,remote-pid = <5>;
777 smp2p_cdsp_out: master-kernel {
778 qcom,entry-name = "master-kernel";
779 #qcom,smem-state-cells = <1>;
782 smp2p_cdsp_in: slave-kernel {
783 qcom,entry-name = "slave-kernel";
784 interrupt-controller;
785 #interrupt-cells = <2>;
790 compatible = "simple-bus";
792 #address-cells = <2>;
793 #size-cells = <2>;
794 dma-ranges = <0 0 0 0 0x10 0>;
797 gcc: clock-controller@100000 {
798 compatible = "qcom,x1e80100-gcc";
839 power-domains = <&rpmhpd RPMHPD_CX>;
840 #clock-cells = <1>;
841 #reset-cells = <1>;
842 #power-domain-cells = <1>;
846 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
850 interrupt-controller;
851 #interrupt-cells = <3>;
853 #mbox-cells = <2>;
856 gpi_dma2: dma-controller@800000 {
857 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
873 dma-channels = <12>;
874 dma-channel-mask = <0x3e>;
875 #dma-cells = <3>;
883 compatible = "qcom,geni-se-qup";
888 clock-names = "m-ahb",
889 "s-ahb";
893 #address-cells = <2>;
894 #size-cells = <2>;
900 compatible = "qcom,geni-i2c";
906 clock-names = "se";
914 interconnect-names = "qup-core",
915 "qup-config",
916 "qup-memory";
918 power-domains = <&rpmhpd RPMHPD_CX>;
919 required-opps = <&rpmhpd_opp_low_svs>;
923 dma-names = "tx",
926 pinctrl-0 = <&qup_i2c16_data_clk>;
927 pinctrl-names = "default";
929 #address-cells = <1>;
930 #size-cells = <0>;
936 compatible = "qcom,geni-spi";
942 clock-names = "se";
950 interconnect-names = "qup-core",
951 "qup-config",
952 "qup-memory";
954 power-domains = <&rpmhpd RPMHPD_CX>;
955 operating-points-v2 = <&qup_opp_table_120mhz>;
959 dma-names = "tx",
962 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
963 pinctrl-names = "default";
965 #address-cells = <1>;
966 #size-cells = <0>;
972 compatible = "qcom,geni-i2c";
978 clock-names = "se";
986 interconnect-names = "qup-core",
987 "qup-config",
988 "qup-memory";
990 power-domains = <&rpmhpd RPMHPD_CX>;
991 required-opps = <&rpmhpd_opp_low_svs>;
995 dma-names = "tx",
998 pinctrl-0 = <&qup_i2c17_data_clk>;
999 pinctrl-names = "default";
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1008 compatible = "qcom,geni-spi";
1014 clock-names = "se";
1022 interconnect-names = "qup-core",
1023 "qup-config",
1024 "qup-memory";
1026 power-domains = <&rpmhpd RPMHPD_CX>;
1027 operating-points-v2 = <&qup_opp_table_120mhz>;
1031 dma-names = "tx",
1034 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1035 pinctrl-names = "default";
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1044 compatible = "qcom,geni-i2c";
1050 clock-names = "se";
1058 interconnect-names = "qup-core",
1059 "qup-config",
1060 "qup-memory";
1062 power-domains = <&rpmhpd RPMHPD_CX>;
1063 required-opps = <&rpmhpd_opp_low_svs>;
1067 dma-names = "tx",
1070 pinctrl-0 = <&qup_i2c18_data_clk>;
1071 pinctrl-names = "default";
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1080 compatible = "qcom,geni-spi";
1086 clock-names = "se";
1094 interconnect-names = "qup-core",
1095 "qup-config",
1096 "qup-memory";
1098 power-domains = <&rpmhpd RPMHPD_CX>;
1099 operating-points-v2 = <&qup_opp_table_100mhz>;
1103 dma-names = "tx",
1106 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1107 pinctrl-names = "default";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1116 compatible = "qcom,geni-i2c";
1122 clock-names = "se";
1130 interconnect-names = "qup-core",
1131 "qup-config",
1132 "qup-memory";
1134 power-domains = <&rpmhpd RPMHPD_CX>;
1135 required-opps = <&rpmhpd_opp_low_svs>;
1139 dma-names = "tx",
1142 pinctrl-0 = <&qup_i2c19_data_clk>;
1143 pinctrl-names = "default";
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1152 compatible = "qcom,geni-spi";
1158 clock-names = "se";
1166 interconnect-names = "qup-core",
1167 "qup-config",
1168 "qup-memory";
1170 power-domains = <&rpmhpd RPMHPD_CX>;
1171 operating-points-v2 = <&qup_opp_table_100mhz>;
1175 dma-names = "tx",
1178 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1179 pinctrl-names = "default";
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1188 compatible = "qcom,geni-i2c";
1194 clock-names = "se";
1202 interconnect-names = "qup-core",
1203 "qup-config",
1204 "qup-memory";
1206 power-domains = <&rpmhpd RPMHPD_CX>;
1207 required-opps = <&rpmhpd_opp_low_svs>;
1211 dma-names = "tx",
1214 pinctrl-0 = <&qup_i2c20_data_clk>;
1215 pinctrl-names = "default";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1224 compatible = "qcom,geni-spi";
1230 clock-names = "se";
1238 interconnect-names = "qup-core",
1239 "qup-config",
1240 "qup-memory";
1242 power-domains = <&rpmhpd RPMHPD_CX>;
1243 operating-points-v2 = <&qup_opp_table_100mhz>;
1247 dma-names = "tx",
1250 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1251 pinctrl-names = "default";
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1260 compatible = "qcom,geni-i2c";
1266 clock-names = "se";
1274 interconnect-names = "qup-core",
1275 "qup-config",
1276 "qup-memory";
1278 power-domains = <&rpmhpd RPMHPD_CX>;
1279 required-opps = <&rpmhpd_opp_low_svs>;
1283 dma-names = "tx",
1286 pinctrl-0 = <&qup_i2c21_data_clk>;
1287 pinctrl-names = "default";
1289 #address-cells = <1>;
1290 #size-cells = <0>;
1296 compatible = "qcom,geni-spi";
1302 clock-names = "se";
1310 interconnect-names = "qup-core",
1311 "qup-config",
1312 "qup-memory";
1314 power-domains = <&rpmhpd RPMHPD_CX>;
1315 operating-points-v2 = <&qup_opp_table_100mhz>;
1319 dma-names = "tx",
1322 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1323 pinctrl-names = "default";
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1332 compatible = "qcom,geni-uart";
1338 clock-names = "se";
1344 interconnect-names = "qup-core",
1345 "qup-config";
1347 power-domains = <&rpmhpd RPMHPD_CX>;
1348 operating-points-v2 = <&qup_opp_table_100mhz>;
1350 pinctrl-0 = <&qup_uart21_default>;
1351 pinctrl-names = "default";
1357 compatible = "qcom,geni-i2c";
1363 clock-names = "se";
1371 interconnect-names = "qup-core",
1372 "qup-config",
1373 "qup-memory";
1375 power-domains = <&rpmhpd RPMHPD_CX>;
1376 required-opps = <&rpmhpd_opp_low_svs>;
1380 dma-names = "tx",
1383 pinctrl-0 = <&qup_i2c22_data_clk>;
1384 pinctrl-names = "default";
1386 #address-cells = <1>;
1387 #size-cells = <0>;
1393 compatible = "qcom,geni-spi";
1399 clock-names = "se";
1407 interconnect-names = "qup-core",
1408 "qup-config",
1409 "qup-memory";
1411 power-domains = <&rpmhpd RPMHPD_CX>;
1412 operating-points-v2 = <&qup_opp_table_100mhz>;
1416 dma-names = "tx",
1419 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1420 pinctrl-names = "default";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1429 compatible = "qcom,geni-i2c";
1435 clock-names = "se";
1443 interconnect-names = "qup-core",
1444 "qup-config",
1445 "qup-memory";
1447 power-domains = <&rpmhpd RPMHPD_CX>;
1448 required-opps = <&rpmhpd_opp_low_svs>;
1452 dma-names = "tx",
1455 pinctrl-0 = <&qup_i2c23_data_clk>;
1456 pinctrl-names = "default";
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1465 compatible = "qcom,geni-spi";
1471 clock-names = "se";
1479 interconnect-names = "qup-core",
1480 "qup-config",
1481 "qup-memory";
1483 power-domains = <&rpmhpd RPMHPD_CX>;
1484 operating-points-v2 = <&qup_opp_table_100mhz>;
1488 dma-names = "tx",
1491 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1492 pinctrl-names = "default";
1494 #address-cells = <1>;
1495 #size-cells = <0>;
1501 gpi_dma1: dma-controller@a00000 {
1502 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1518 dma-channels = <12>;
1519 dma-channel-mask = <0x3e>;
1520 #dma-cells = <3>;
1528 compatible = "qcom,geni-se-qup";
1533 clock-names = "m-ahb",
1534 "s-ahb";
1538 #address-cells = <2>;
1539 #size-cells = <2>;
1545 compatible = "qcom,geni-i2c";
1551 clock-names = "se";
1559 interconnect-names = "qup-core",
1560 "qup-config",
1561 "qup-memory";
1563 power-domains = <&rpmhpd RPMHPD_CX>;
1564 required-opps = <&rpmhpd_opp_low_svs>;
1568 dma-names = "tx",
1571 pinctrl-0 = <&qup_i2c8_data_clk>;
1572 pinctrl-names = "default";
1574 #address-cells = <1>;
1575 #size-cells = <0>;
1581 compatible = "qcom,geni-spi";
1587 clock-names = "se";
1595 interconnect-names = "qup-core",
1596 "qup-config",
1597 "qup-memory";
1599 power-domains = <&rpmhpd RPMHPD_CX>;
1600 operating-points-v2 = <&qup_opp_table_120mhz>;
1604 dma-names = "tx",
1607 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1608 pinctrl-names = "default";
1610 #address-cells = <1>;
1611 #size-cells = <0>;
1617 compatible = "qcom,geni-i2c";
1623 clock-names = "se";
1631 interconnect-names = "qup-core",
1632 "qup-config",
1633 "qup-memory";
1635 power-domains = <&rpmhpd RPMHPD_CX>;
1636 required-opps = <&rpmhpd_opp_low_svs>;
1640 dma-names = "tx",
1643 pinctrl-0 = <&qup_i2c9_data_clk>;
1644 pinctrl-names = "default";
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1653 compatible = "qcom,geni-spi";
1659 clock-names = "se";
1667 interconnect-names = "qup-core",
1668 "qup-config",
1669 "qup-memory";
1671 power-domains = <&rpmhpd RPMHPD_CX>;
1672 operating-points-v2 = <&qup_opp_table_120mhz>;
1676 dma-names = "tx",
1679 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1680 pinctrl-names = "default";
1682 #address-cells = <1>;
1683 #size-cells = <0>;
1689 compatible = "qcom,geni-i2c";
1695 clock-names = "se";
1703 interconnect-names = "qup-core",
1704 "qup-config",
1705 "qup-memory";
1707 power-domains = <&rpmhpd RPMHPD_CX>;
1708 required-opps = <&rpmhpd_opp_low_svs>;
1712 dma-names = "tx",
1715 pinctrl-0 = <&qup_i2c10_data_clk>;
1716 pinctrl-names = "default";
1718 #address-cells = <1>;
1719 #size-cells = <0>;
1725 compatible = "qcom,geni-spi";
1731 clock-names = "se";
1739 interconnect-names = "qup-core",
1740 "qup-config",
1741 "qup-memory";
1743 power-domains = <&rpmhpd RPMHPD_CX>;
1744 operating-points-v2 = <&qup_opp_table_100mhz>;
1748 dma-names = "tx",
1751 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1752 pinctrl-names = "default";
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1761 compatible = "qcom,geni-i2c";
1767 clock-names = "se";
1775 interconnect-names = "qup-core",
1776 "qup-config",
1777 "qup-memory";
1779 power-domains = <&rpmhpd RPMHPD_CX>;
1780 required-opps = <&rpmhpd_opp_low_svs>;
1784 dma-names = "tx",
1787 pinctrl-0 = <&qup_i2c11_data_clk>;
1788 pinctrl-names = "default";
1790 #address-cells = <1>;
1791 #size-cells = <0>;
1797 compatible = "qcom,geni-spi";
1803 clock-names = "se";
1811 interconnect-names = "qup-core",
1812 "qup-config",
1813 "qup-memory";
1815 power-domains = <&rpmhpd RPMHPD_CX>;
1816 operating-points-v2 = <&qup_opp_table_100mhz>;
1820 dma-names = "tx",
1823 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1824 pinctrl-names = "default";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1833 compatible = "qcom,geni-i2c";
1839 clock-names = "se";
1847 interconnect-names = "qup-core",
1848 "qup-config",
1849 "qup-memory";
1851 power-domains = <&rpmhpd RPMHPD_CX>;
1852 required-opps = <&rpmhpd_opp_low_svs>;
1856 dma-names = "tx",
1859 pinctrl-0 = <&qup_i2c12_data_clk>;
1860 pinctrl-names = "default";
1862 #address-cells = <1>;
1863 #size-cells = <0>;
1869 compatible = "qcom,geni-spi";
1875 clock-names = "se";
1883 interconnect-names = "qup-core",
1884 "qup-config",
1885 "qup-memory";
1887 power-domains = <&rpmhpd RPMHPD_CX>;
1888 operating-points-v2 = <&qup_opp_table_100mhz>;
1892 dma-names = "tx",
1895 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1896 pinctrl-names = "default";
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1905 compatible = "qcom,geni-i2c";
1911 clock-names = "se";
1919 interconnect-names = "qup-core",
1920 "qup-config",
1921 "qup-memory";
1923 power-domains = <&rpmhpd RPMHPD_CX>;
1924 required-opps = <&rpmhpd_opp_low_svs>;
1928 dma-names = "tx",
1931 pinctrl-0 = <&qup_i2c13_data_clk>;
1932 pinctrl-names = "default";
1934 #address-cells = <1>;
1935 #size-cells = <0>;
1941 compatible = "qcom,geni-spi";
1947 clock-names = "se";
1955 interconnect-names = "qup-core",
1956 "qup-config",
1957 "qup-memory";
1959 power-domains = <&rpmhpd RPMHPD_CX>;
1960 operating-points-v2 = <&qup_opp_table_100mhz>;
1964 dma-names = "tx",
1967 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1968 pinctrl-names = "default";
1970 #address-cells = <1>;
1971 #size-cells = <0>;
1977 compatible = "qcom,geni-i2c";
1983 clock-names = "se";
1991 interconnect-names = "qup-core",
1992 "qup-config",
1993 "qup-memory";
1995 power-domains = <&rpmhpd RPMHPD_CX>;
1996 required-opps = <&rpmhpd_opp_low_svs>;
2000 dma-names = "tx",
2003 pinctrl-0 = <&qup_i2c14_data_clk>;
2004 pinctrl-names = "default";
2006 #address-cells = <1>;
2007 #size-cells = <0>;
2013 compatible = "qcom,geni-spi";
2019 clock-names = "se";
2027 interconnect-names = "qup-core",
2028 "qup-config",
2029 "qup-memory";
2031 power-domains = <&rpmhpd RPMHPD_CX>;
2032 operating-points-v2 = <&qup_opp_table_100mhz>;
2036 dma-names = "tx",
2039 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2040 pinctrl-names = "default";
2042 #address-cells = <1>;
2043 #size-cells = <0>;
2049 compatible = "qcom,geni-uart";
2055 clock-names = "se";
2061 interconnect-names = "qup-core",
2062 "qup-config";
2064 power-domains = <&rpmhpd RPMHPD_CX>;
2065 operating-points-v2 = <&qup_opp_table_100mhz>;
2067 pinctrl-0 = <&qup_uart14_default>;
2068 pinctrl-names = "default";
2074 compatible = "qcom,geni-i2c";
2080 clock-names = "se";
2088 interconnect-names = "qup-core",
2089 "qup-config",
2090 "qup-memory";
2092 power-domains = <&rpmhpd RPMHPD_CX>;
2093 required-opps = <&rpmhpd_opp_low_svs>;
2097 dma-names = "tx",
2100 pinctrl-0 = <&qup_i2c15_data_clk>;
2101 pinctrl-names = "default";
2103 #address-cells = <1>;
2104 #size-cells = <0>;
2110 compatible = "qcom,geni-spi";
2116 clock-names = "se";
2124 interconnect-names = "qup-core",
2125 "qup-config",
2126 "qup-memory";
2128 power-domains = <&rpmhpd RPMHPD_CX>;
2129 operating-points-v2 = <&qup_opp_table_100mhz>;
2133 dma-names = "tx",
2136 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2137 pinctrl-names = "default";
2139 #address-cells = <1>;
2140 #size-cells = <0>;
2146 gpi_dma0: dma-controller@b00000 {
2147 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
2163 dma-channels = <12>;
2164 dma-channel-mask = <0x3e>;
2165 #dma-cells = <3>;
2173 compatible = "qcom,geni-se-qup";
2178 clock-names = "m-ahb",
2179 "s-ahb";
2182 #address-cells = <2>;
2183 #size-cells = <2>;
2189 compatible = "qcom,geni-i2c";
2195 clock-names = "se";
2203 interconnect-names = "qup-core",
2204 "qup-config",
2205 "qup-memory";
2207 power-domains = <&rpmhpd RPMHPD_CX>;
2208 required-opps = <&rpmhpd_opp_low_svs>;
2212 dma-names = "tx",
2215 pinctrl-0 = <&qup_i2c0_data_clk>;
2216 pinctrl-names = "default";
2218 #address-cells = <1>;
2219 #size-cells = <0>;
2225 compatible = "qcom,geni-spi";
2231 clock-names = "se";
2239 interconnect-names = "qup-core",
2240 "qup-config",
2241 "qup-memory";
2243 power-domains = <&rpmhpd RPMHPD_CX>;
2244 operating-points-v2 = <&qup_opp_table_120mhz>;
2248 dma-names = "tx",
2251 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2252 pinctrl-names = "default";
2254 #address-cells = <1>;
2255 #size-cells = <0>;
2261 compatible = "qcom,geni-i2c";
2267 clock-names = "se";
2275 interconnect-names = "qup-core",
2276 "qup-config",
2277 "qup-memory";
2279 power-domains = <&rpmhpd RPMHPD_CX>;
2280 required-opps = <&rpmhpd_opp_low_svs>;
2284 dma-names = "tx",
2287 pinctrl-0 = <&qup_i2c1_data_clk>;
2288 pinctrl-names = "default";
2290 #address-cells = <1>;
2291 #size-cells = <0>;
2297 compatible = "qcom,geni-spi";
2303 clock-names = "se";
2311 interconnect-names = "qup-core",
2312 "qup-config",
2313 "qup-memory";
2315 power-domains = <&rpmhpd RPMHPD_CX>;
2316 operating-points-v2 = <&qup_opp_table_120mhz>;
2320 dma-names = "tx",
2323 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2324 pinctrl-names = "default";
2326 #address-cells = <1>;
2327 #size-cells = <0>;
2333 compatible = "qcom,geni-i2c";
2339 clock-names = "se";
2347 interconnect-names = "qup-core",
2348 "qup-config",
2349 "qup-memory";
2351 power-domains = <&rpmhpd RPMHPD_CX>;
2352 required-opps = <&rpmhpd_opp_low_svs>;
2356 dma-names = "tx",
2359 pinctrl-0 = <&qup_i2c2_data_clk>;
2360 pinctrl-names = "default";
2362 #address-cells = <1>;
2363 #size-cells = <0>;
2369 compatible = "qcom,geni-uart";
2375 clock-names = "se";
2381 interconnect-names = "qup-core",
2382 "qup-config";
2384 power-domains = <&rpmhpd RPMHPD_CX>;
2385 operating-points-v2 = <&qup_opp_table_100mhz>;
2387 pinctrl-0 = <&qup_uart2_default>;
2388 pinctrl-names = "default";
2394 compatible = "qcom,geni-spi";
2400 clock-names = "se";
2408 interconnect-names = "qup-core",
2409 "qup-config",
2410 "qup-memory";
2412 power-domains = <&rpmhpd RPMHPD_CX>;
2413 operating-points-v2 = <&qup_opp_table_100mhz>;
2417 dma-names = "tx",
2420 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2421 pinctrl-names = "default";
2423 #address-cells = <1>;
2424 #size-cells = <0>;
2430 compatible = "qcom,geni-i2c";
2436 clock-names = "se";
2444 interconnect-names = "qup-core",
2445 "qup-config",
2446 "qup-memory";
2448 power-domains = <&rpmhpd RPMHPD_CX>;
2449 required-opps = <&rpmhpd_opp_low_svs>;
2453 dma-names = "tx",
2456 pinctrl-0 = <&qup_i2c3_data_clk>;
2457 pinctrl-names = "default";
2459 #address-cells = <1>;
2460 #size-cells = <0>;
2466 compatible = "qcom,geni-spi";
2472 clock-names = "se";
2480 interconnect-names = "qup-core",
2481 "qup-config",
2482 "qup-memory";
2484 power-domains = <&rpmhpd RPMHPD_CX>;
2485 operating-points-v2 = <&qup_opp_table_100mhz>;
2489 dma-names = "tx",
2492 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2493 pinctrl-names = "default";
2495 #address-cells = <1>;
2496 #size-cells = <0>;
2502 compatible = "qcom,geni-i2c";
2508 clock-names = "se";
2516 interconnect-names = "qup-core",
2517 "qup-config",
2518 "qup-memory";
2520 power-domains = <&rpmhpd RPMHPD_CX>;
2521 required-opps = <&rpmhpd_opp_low_svs>;
2525 dma-names = "tx",
2528 pinctrl-0 = <&qup_i2c4_data_clk>;
2529 pinctrl-names = "default";
2531 #address-cells = <1>;
2532 #size-cells = <0>;
2538 compatible = "qcom,geni-spi";
2544 clock-names = "se";
2552 interconnect-names = "qup-core",
2553 "qup-config",
2554 "qup-memory";
2556 power-domains = <&rpmhpd RPMHPD_CX>;
2557 operating-points-v2 = <&qup_opp_table_100mhz>;
2561 dma-names = "tx",
2564 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2565 pinctrl-names = "default";
2567 #address-cells = <1>;
2568 #size-cells = <0>;
2574 compatible = "qcom,geni-i2c";
2580 clock-names = "se";
2588 interconnect-names = "qup-core",
2589 "qup-config",
2590 "qup-memory";
2592 power-domains = <&rpmhpd RPMHPD_CX>;
2593 required-opps = <&rpmhpd_opp_low_svs>;
2597 dma-names = "tx",
2600 pinctrl-0 = <&qup_i2c5_data_clk>;
2601 pinctrl-names = "default";
2603 #address-cells = <1>;
2604 #size-cells = <0>;
2610 compatible = "qcom,geni-spi";
2616 clock-names = "se";
2624 interconnect-names = "qup-core",
2625 "qup-config",
2626 "qup-memory";
2628 power-domains = <&rpmhpd RPMHPD_CX>;
2629 operating-points-v2 = <&qup_opp_table_100mhz>;
2633 dma-names = "tx",
2636 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2637 pinctrl-names = "default";
2639 #address-cells = <1>;
2640 #size-cells = <0>;
2646 compatible = "qcom,geni-i2c";
2652 clock-names = "se";
2660 interconnect-names = "qup-core",
2661 "qup-config",
2662 "qup-memory";
2664 power-domains = <&rpmhpd RPMHPD_CX>;
2665 required-opps = <&rpmhpd_opp_low_svs>;
2669 dma-names = "tx",
2672 pinctrl-0 = <&qup_i2c6_data_clk>;
2673 pinctrl-names = "default";
2675 #address-cells = <1>;
2676 #size-cells = <0>;
2682 compatible = "qcom,geni-spi";
2688 clock-names = "se";
2696 interconnect-names = "qup-core",
2697 "qup-config",
2698 "qup-memory";
2700 power-domains = <&rpmhpd RPMHPD_CX>;
2701 operating-points-v2 = <&qup_opp_table_100mhz>;
2705 dma-names = "tx",
2708 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2709 pinctrl-names = "default";
2711 #address-cells = <1>;
2712 #size-cells = <0>;
2718 compatible = "qcom,geni-i2c";
2724 clock-names = "se";
2732 interconnect-names = "qup-core",
2733 "qup-config",
2734 "qup-memory";
2736 power-domains = <&rpmhpd RPMHPD_CX>;
2737 required-opps = <&rpmhpd_opp_low_svs>;
2741 dma-names = "tx",
2744 pinctrl-0 = <&qup_i2c7_data_clk>;
2745 pinctrl-names = "default";
2747 #address-cells = <1>;
2748 #size-cells = <0>;
2754 compatible = "qcom,geni-spi";
2760 clock-names = "se";
2768 interconnect-names = "qup-core",
2769 "qup-config",
2770 "qup-memory";
2772 power-domains = <&rpmhpd RPMHPD_CX>;
2773 operating-points-v2 = <&qup_opp_table_100mhz>;
2777 dma-names = "tx",
2780 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2781 pinctrl-names = "default";
2783 #address-cells = <1>;
2784 #size-cells = <0>;
2790 tsens0: thermal-sensor@c271000 {
2791 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2795 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2796 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
2797 interrupt-names = "uplow",
2802 #thermal-sensor-cells = <1>;
2805 tsens1: thermal-sensor@c272000 {
2806 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2810 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2811 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
2812 interrupt-names = "uplow",
2817 #thermal-sensor-cells = <1>;
2820 tsens2: thermal-sensor@c273000 {
2821 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2825 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2826 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
2827 interrupt-names = "uplow",
2832 #thermal-sensor-cells = <1>;
2835 tsens3: thermal-sensor@c274000 {
2836 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2840 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2841 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
2842 interrupt-names = "uplow",
2847 #thermal-sensor-cells = <1>;
2851 compatible = "qcom,x1e80100-snps-eusb2-phy",
2852 "qcom,sm8550-snps-eusb2-phy";
2854 #phy-cells = <0>;
2857 clock-names = "ref";
2865 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2872 clock-names = "aux",
2877 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2881 reset-names = "phy",
2884 #clock-cells = <1>;
2885 #phy-cells = <1>;
2887 mode-switch;
2888 orientation-switch;
2893 #address-cells = <1>;
2894 #size-cells = <0>;
2907 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2915 remote-endpoint = <&mdss_dp0_out>;
2922 compatible = "qcom,x1e80100-snps-eusb2-phy",
2923 "qcom,sm8550-snps-eusb2-phy";
2925 #phy-cells = <0>;
2928 clock-names = "ref";
2936 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2943 clock-names = "aux",
2948 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2952 reset-names = "phy",
2955 #clock-cells = <1>;
2956 #phy-cells = <1>;
2958 mode-switch;
2959 orientation-switch;
2964 #address-cells = <1>;
2965 #size-cells = <0>;
2978 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2986 remote-endpoint = <&mdss_dp1_out>;
2993 compatible = "qcom,x1e80100-snps-eusb2-phy",
2994 "qcom,sm8550-snps-eusb2-phy";
2996 #phy-cells = <0>;
2999 clock-names = "ref";
3007 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
3014 clock-names = "aux",
3019 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
3023 reset-names = "phy",
3026 #clock-cells = <1>;
3027 #phy-cells = <1>;
3029 mode-switch;
3030 orientation-switch;
3035 #address-cells = <1>;
3036 #size-cells = <0>;
3049 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
3057 remote-endpoint = <&mdss_dp2_out>;
3064 compatible = "qcom,x1e80100-cnoc-main";
3067 qcom,bcm-voters = <&apps_bcm_voter>;
3069 #interconnect-cells = <2>;
3073 compatible = "qcom,x1e80100-cnoc-cfg";
3076 qcom,bcm-voters = <&apps_bcm_voter>;
3078 #interconnect-cells = <2>;
3082 compatible = "qcom,x1e80100-system-noc";
3085 qcom,bcm-voters = <&apps_bcm_voter>;
3087 #interconnect-cells = <2>;
3091 compatible = "qcom,x1e80100-pcie-south-anoc";
3094 qcom,bcm-voters = <&apps_bcm_voter>;
3096 #interconnect-cells = <2>;
3100 compatible = "qcom,x1e80100-pcie-center-anoc";
3103 qcom,bcm-voters = <&apps_bcm_voter>;
3105 #interconnect-cells = <2>;
3109 compatible = "qcom,x1e80100-aggre1-noc";
3112 qcom,bcm-voters = <&apps_bcm_voter>;
3114 #interconnect-cells = <2>;
3118 compatible = "qcom,x1e80100-aggre2-noc";
3121 qcom,bcm-voters = <&apps_bcm_voter>;
3123 #interconnect-cells = <2>;
3127 compatible = "qcom,x1e80100-pcie-north-anoc";
3130 qcom,bcm-voters = <&apps_bcm_voter>;
3132 #interconnect-cells = <2>;
3136 compatible = "qcom,x1e80100-usb-center-anoc";
3139 qcom,bcm-voters = <&apps_bcm_voter>;
3141 #interconnect-cells = <2>;
3145 compatible = "qcom,x1e80100-usb-north-anoc";
3148 qcom,bcm-voters = <&apps_bcm_voter>;
3150 #interconnect-cells = <2>;
3154 compatible = "qcom,x1e80100-usb-south-anoc";
3157 qcom,bcm-voters = <&apps_bcm_voter>;
3159 #interconnect-cells = <2>;
3163 compatible = "qcom,x1e80100-mmss-noc";
3166 qcom,bcm-voters = <&apps_bcm_voter>;
3168 #interconnect-cells = <2>;
3173 compatible = "qcom,pcie-x1e80100";
3180 reg-names = "parf",
3186 #address-cells = <3>;
3187 #size-cells = <2>;
3191 bus-range = <0x00 0xff>;
3193 dma-coherent;
3195 linux,pci-domain = <3>;
3196 num-lanes = <8>;
3207 interrupt-names = "msi0",
3217 #interrupt-cells = <1>;
3218 interrupt-map-mask = <0 0 0 0x7>;
3219 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
3220 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
3221 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3222 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3231 clock-names = "aux",
3239 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
3240 assigned-clock-rates = <19200000>;
3246 interconnect-names = "pcie-mem",
3247 "cpu-pcie";
3251 reset-names = "pci",
3254 power-domains = <&gcc GCC_PCIE_3_GDSC>;
3257 phy-names = "pciephy";
3259 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
3261 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
3263 operating-points-v2 = <&pcie3_opp_table>;
3267 pcie3_opp_table: opp-table {
3268 compatible = "operating-points-v2";
3271 opp-2500000-1 {
3272 opp-hz = /bits/ 64 <2500000>;
3273 required-opps = <&rpmhpd_opp_low_svs>;
3274 opp-peak-kBps = <250000 1>;
3275 opp-level = <1>;
3279 opp-5000000-1 {
3280 opp-hz = /bits/ 64 <5000000>;
3281 required-opps = <&rpmhpd_opp_low_svs>;
3282 opp-peak-kBps = <500000 1>;
3283 opp-level = <1>;
3287 opp-10000000-1 {
3288 opp-hz = /bits/ 64 <10000000>;
3289 required-opps = <&rpmhpd_opp_low_svs>;
3290 opp-peak-kBps = <1000000 1>;
3291 opp-level = <1>;
3295 opp-20000000-1 {
3296 opp-hz = /bits/ 64 <20000000>;
3297 required-opps = <&rpmhpd_opp_low_svs>;
3298 opp-peak-kBps = <2000000 1>;
3299 opp-level = <1>;
3303 opp-5000000-2 {
3304 opp-hz = /bits/ 64 <5000000>;
3305 required-opps = <&rpmhpd_opp_low_svs>;
3306 opp-peak-kBps = <500000 1>;
3307 opp-level = <2>;
3311 opp-10000000-2 {
3312 opp-hz = /bits/ 64 <10000000>;
3313 required-opps = <&rpmhpd_opp_low_svs>;
3314 opp-peak-kBps = <1000000 1>;
3315 opp-level = <2>;
3319 opp-20000000-2 {
3320 opp-hz = /bits/ 64 <20000000>;
3321 required-opps = <&rpmhpd_opp_low_svs>;
3322 opp-peak-kBps = <2000000 1>;
3323 opp-level = <2>;
3327 opp-40000000-2 {
3328 opp-hz = /bits/ 64 <40000000>;
3329 required-opps = <&rpmhpd_opp_low_svs>;
3330 opp-peak-kBps = <4000000 1>;
3331 opp-level = <2>;
3335 opp-8000000-3 {
3336 opp-hz = /bits/ 64 <8000000>;
3337 required-opps = <&rpmhpd_opp_svs>;
3338 opp-peak-kBps = <984500 1>;
3339 opp-level = <3>;
3343 opp-16000000-3 {
3344 opp-hz = /bits/ 64 <16000000>;
3345 required-opps = <&rpmhpd_opp_svs>;
3346 opp-peak-kBps = <1969000 1>;
3347 opp-level = <3>;
3351 opp-32000000-3 {
3352 opp-hz = /bits/ 64 <32000000>;
3353 required-opps = <&rpmhpd_opp_svs>;
3354 opp-peak-kBps = <3938000 1>;
3355 opp-level = <3>;
3359 opp-64000000-3 {
3360 opp-hz = /bits/ 64 <64000000>;
3361 required-opps = <&rpmhpd_opp_svs>;
3362 opp-peak-kBps = <7876000 1>;
3363 opp-level = <3>;
3367 opp-16000000-4 {
3368 opp-hz = /bits/ 64 <16000000>;
3369 required-opps = <&rpmhpd_opp_svs>;
3370 opp-peak-kBps = <1969000 1>;
3371 opp-level = <4>;
3375 opp-32000000-4 {
3376 opp-hz = /bits/ 64 <32000000>;
3377 required-opps = <&rpmhpd_opp_svs>;
3378 opp-peak-kBps = <3938000 1>;
3379 opp-level = <4>;
3383 opp-64000000-4 {
3384 opp-hz = /bits/ 64 <64000000>;
3385 required-opps = <&rpmhpd_opp_svs>;
3386 opp-peak-kBps = <7876000 1>;
3387 opp-level = <4>;
3391 opp-128000000-4 {
3392 opp-hz = /bits/ 64 <128000000>;
3393 required-opps = <&rpmhpd_opp_svs>;
3394 opp-peak-kBps = <15753000 1>;
3395 opp-level = <4>;
3403 bus-range = <0x01 0xff>;
3405 #address-cells = <3>;
3406 #size-cells = <2>;
3412 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
3421 clock-names = "aux",
3430 reset-names = "phy",
3433 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
3434 assigned-clock-rates = <100000000>;
3436 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
3438 #clock-cells = <0>;
3439 clock-output-names = "pcie3_pipe_clk";
3441 #phy-cells = <0>;
3448 compatible = "qcom,pcie-x1e80100";
3455 reg-names = "parf",
3461 #address-cells = <3>;
3462 #size-cells = <2>;
3465 bus-range = <0x00 0xff>;
3467 dma-coherent;
3469 linux,pci-domain = <6>;
3470 num-lanes = <4>;
3472 msi-map = <0x0 &gic_its 0xe0000 0x10000>;
3483 interrupt-names = "msi0",
3493 #interrupt-cells = <1>;
3494 interrupt-map-mask = <0 0 0 0x7>;
3495 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
3496 <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
3497 <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
3498 <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>;
3507 clock-names = "aux",
3515 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
3516 assigned-clock-rates = <19200000>;
3522 interconnect-names = "pcie-mem",
3523 "cpu-pcie";
3527 reset-names = "pci",
3530 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
3531 required-opps = <&rpmhpd_opp_nom>;
3534 phy-names = "pciephy";
3536 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
3537 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
3543 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3553 clock-names = "aux",
3562 reset-names = "phy",
3565 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3566 assigned-clock-rates = <100000000>;
3568 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3570 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3572 #clock-cells = <0>;
3573 clock-output-names = "pcie6a_pipe_clk";
3575 #phy-cells = <0>;
3582 compatible = "qcom,pcie-x1e80100";
3589 reg-names = "parf",
3595 #address-cells = <3>;
3596 #size-cells = <2>;
3599 bus-range = <0x00 0xff>;
3601 dma-coherent;
3603 linux,pci-domain = <5>;
3604 num-lanes = <2>;
3615 interrupt-names = "msi0",
3625 #interrupt-cells = <1>;
3626 interrupt-map-mask = <0 0 0 0x7>;
3627 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
3628 <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3629 <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
3630 <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
3639 clock-names = "aux",
3647 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3648 assigned-clock-rates = <19200000>;
3654 interconnect-names = "pcie-mem",
3655 "cpu-pcie";
3659 reset-names = "pci",
3662 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3663 required-opps = <&rpmhpd_opp_nom>;
3666 phy-names = "pciephy";
3668 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3674 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3683 clock-names = "aux",
3692 reset-names = "phy",
3695 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3696 assigned-clock-rates = <100000000>;
3698 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3700 #clock-cells = <0>;
3701 clock-output-names = "pcie5_pipe_clk";
3703 #phy-cells = <0>;
3710 compatible = "qcom,pcie-x1e80100";
3717 reg-names = "parf",
3723 #address-cells = <3>;
3724 #size-cells = <2>;
3727 bus-range = <0x00 0xff>;
3729 dma-coherent;
3731 linux,pci-domain = <4>;
3732 num-lanes = <2>;
3734 msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3745 interrupt-names = "msi0",
3755 #interrupt-cells = <1>;
3756 interrupt-map-mask = <0 0 0 0x7>;
3757 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
3758 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
3759 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
3760 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
3769 clock-names = "aux",
3777 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3778 assigned-clock-rates = <19200000>;
3784 interconnect-names = "pcie-mem",
3785 "cpu-pcie";
3789 reset-names = "pci",
3792 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3793 required-opps = <&rpmhpd_opp_nom>;
3796 phy-names = "pciephy";
3798 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3805 bus-range = <0x01 0xff>;
3807 #address-cells = <3>;
3808 #size-cells = <2>;
3814 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3823 clock-names = "aux",
3832 reset-names = "phy",
3835 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3836 assigned-clock-rates = <100000000>;
3838 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3840 #clock-cells = <0>;
3841 clock-output-names = "pcie4_pipe_clk";
3843 #phy-cells = <0>;
3849 compatible = "qcom,tcsr-mutex";
3851 #hwlock-cells = <1>;
3854 tcsr: clock-controller@1fc0000 {
3855 compatible = "qcom,x1e80100-tcsr", "syscon";
3858 #clock-cells = <1>;
3859 #reset-cells = <1>;
3863 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3868 reg-names = "kgsl_3d0_reg_memory",
3877 operating-points-v2 = <&gpu_opp_table>;
3880 #cooling-cells = <2>;
3882 nvmem-cells = <&gpu_speed_bin>;
3883 nvmem-cell-names = "speed_bin";
3886 interconnect-names = "gfx-mem";
3890 gpu_zap_shader: zap-shader {
3891 memory-region = <&gpu_microcode_mem>;
3894 gpu_opp_table: opp-table {
3895 compatible = "operating-points-v2-adreno", "operating-points-v2";
3897 opp-1500000000 {
3898 opp-hz = /bits/ 64 <1500000000>;
3899 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
3900 opp-peak-kBps = <16500000>;
3901 qcom,opp-acd-level = <0xa82a5ffd>;
3902 opp-supported-hw = <0x03>;
3905 opp-1375000000 {
3906 opp-hz = /bits/ 64 <1375000000>;
3907 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
3908 opp-peak-kBps = <16500000>;
3909 qcom,opp-acd-level = <0xa82a5ffd>;
3910 opp-supported-hw = <0x03>;
3913 opp-1250000000 {
3914 opp-hz = /bits/ 64 <1250000000>;
3915 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
3916 opp-peak-kBps = <16500000>;
3917 qcom,opp-acd-level = <0xa82a5ffd>;
3918 opp-supported-hw = <0x07>;
3921 opp-1175000000 {
3922 opp-hz = /bits/ 64 <1175000000>;
3923 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
3924 opp-peak-kBps = <14398438>;
3925 qcom,opp-acd-level = <0xa82a5ffd>;
3926 opp-supported-hw = <0x07>;
3929 opp-1100000000-0 {
3930 opp-hz = /bits/ 64 <1100000000>;
3931 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3932 opp-peak-kBps = <14398438>;
3933 qcom,opp-acd-level = <0xa82a5ffd>;
3934 opp-supported-hw = <0x07>;
3938 opp-1100000000-1 {
3939 opp-hz = /bits/ 64 <1100000000>;
3940 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3941 opp-peak-kBps = <16500000>;
3942 qcom,opp-acd-level = <0xa82a5ffd>;
3943 opp-supported-hw = <0x08>;
3946 opp-1000000000 {
3947 opp-hz = /bits/ 64 <1000000000>;
3948 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3949 opp-peak-kBps = <14398438>;
3950 qcom,opp-acd-level = <0xa82b5ffd>;
3951 opp-supported-hw = <0x0f>;
3954 opp-925000000 {
3955 opp-hz = /bits/ 64 <925000000>;
3956 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3957 opp-peak-kBps = <14398438>;
3958 qcom,opp-acd-level = <0xa82b5ffd>;
3959 opp-supported-hw = <0x0f>;
3962 opp-800000000 {
3963 opp-hz = /bits/ 64 <800000000>;
3964 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3965 opp-peak-kBps = <12449219>;
3966 qcom,opp-acd-level = <0xa82c5ffd>;
3967 opp-supported-hw = <0x0f>;
3970 opp-744000000 {
3971 opp-hz = /bits/ 64 <744000000>;
3972 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3973 opp-peak-kBps = <10687500>;
3974 qcom,opp-acd-level = <0x882e5ffd>;
3975 opp-supported-hw = <0x0f>;
3978 opp-687000000-0 {
3979 opp-hz = /bits/ 64 <687000000>;
3980 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3981 opp-peak-kBps = <8171875>;
3982 qcom,opp-acd-level = <0x882e5ffd>;
3983 opp-supported-hw = <0x0f>;
3987 opp-687000000-1 {
3988 opp-hz = /bits/ 64 <687000000>;
3989 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3990 opp-peak-kBps = <16500000>;
3991 qcom,opp-acd-level = <0x882e5ffd>;
3992 opp-supported-hw = <0x10>;
3995 opp-550000000 {
3996 opp-hz = /bits/ 64 <550000000>;
3997 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3998 opp-peak-kBps = <6074219>;
3999 qcom,opp-acd-level = <0xc0285ffd>;
4000 opp-supported-hw = <0x1f>;
4003 opp-390000000 {
4004 opp-hz = /bits/ 64 <390000000>;
4005 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4006 opp-peak-kBps = <3000000>;
4007 qcom,opp-acd-level = <0xc0285ffd>;
4008 opp-supported-hw = <0x1f>;
4011 opp-300000000 {
4012 opp-hz = /bits/ 64 <300000000>;
4013 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4014 opp-peak-kBps = <2136719>;
4015 qcom,opp-acd-level = <0xc02b5ffd>;
4016 opp-supported-hw = <0x1f>;
4022 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
4026 reg-names = "gmu", "rscc", "gmu_pdc";
4030 interrupt-names = "hfi", "gmu";
4039 clock-names = "ahb",
4047 power-domains = <&gpucc GPU_CX_GDSC>,
4049 power-domain-names = "cx",
4056 operating-points-v2 = <&gmu_opp_table>;
4058 gmu_opp_table: opp-table {
4059 compatible = "operating-points-v2";
4061 opp-550000000 {
4062 opp-hz = /bits/ 64 <550000000>;
4063 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4066 opp-220000000 {
4067 opp-hz = /bits/ 64 <220000000>;
4068 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4073 gpucc: clock-controller@3d90000 {
4074 compatible = "qcom,x1e80100-gpucc";
4079 #clock-cells = <1>;
4080 #reset-cells = <1>;
4081 #power-domain-cells = <1>;
4085 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
4086 "qcom,smmu-500", "arm,mmu-500";
4088 #iommu-cells = <2>;
4089 #global-interrupts = <1>;
4120 clock-names = "hlos",
4124 power-domains = <&gpucc GPU_CX_GDSC>;
4125 dma-coherent;
4129 compatible = "qcom,x1e80100-gem-noc";
4132 qcom,bcm-voters = <&apps_bcm_voter>;
4134 #interconnect-cells = <2>;
4138 compatible = "qcom,x1e80100-nsp-noc";
4141 qcom,bcm-voters = <&apps_bcm_voter>;
4143 #interconnect-cells = <2>;
4147 compatible = "qcom,x1e80100-adsp-pas";
4150 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4155 interrupt-names = "wdog",
4159 "stop-ack";
4162 clock-names = "xo";
4164 power-domains = <&rpmhpd RPMHPD_LCX>,
4166 power-domain-names = "lcx",
4172 memory-region = <&adspslpi_mem>,
4177 qcom,smem-states = <&smp2p_adsp_out 0>;
4178 qcom,smem-state-names = "stop";
4182 glink-edge {
4183 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4190 qcom,remote-pid = <2>;
4194 qcom,glink-channels = "fastrpcglink-apps-dsp";
4196 qcom,non-secure-domain;
4197 #address-cells = <1>;
4198 #size-cells = <0>;
4200 compute-cb@3 {
4201 compatible = "qcom,fastrpc-compute-cb";
4205 dma-coherent;
4208 compute-cb@4 {
4209 compatible = "qcom,fastrpc-compute-cb";
4213 dma-coherent;
4216 compute-cb@5 {
4217 compatible = "qcom,fastrpc-compute-cb";
4221 dma-coherent;
4224 compute-cb@6 {
4225 compatible = "qcom,fastrpc-compute-cb";
4229 dma-coherent;
4232 compute-cb@7 {
4233 compatible = "qcom,fastrpc-compute-cb";
4237 dma-coherent;
4243 qcom,glink-channels = "adsp_apps";
4246 #address-cells = <1>;
4247 #size-cells = <0>;
4252 #sound-dai-cells = <0>;
4253 qcom,protection-domain = "avs/audio",
4257 compatible = "qcom,q6apm-lpass-dais";
4258 #sound-dai-cells = <1>;
4262 compatible = "qcom,q6apm-dais";
4271 qcom,protection-domain = "avs/audio",
4274 q6prmcc: clock-controller {
4275 compatible = "qcom,q6prm-lpass-clocks";
4276 #clock-cells = <2>;
4284 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4290 clock-names = "mclk",
4295 #clock-cells = <0>;
4296 clock-output-names = "wsa2-mclk";
4297 #sound-dai-cells = <1>;
4298 sound-name-prefix = "WSA2";
4302 compatible = "qcom,soundwire-v2.0.0";
4305 clock-names = "iface";
4309 pinctrl-0 = <&wsa2_swr_active>;
4310 pinctrl-names = "default";
4312 reset-names = "swr_audio_cgcr";
4314 qcom,din-ports = <4>;
4315 qcom,dout-ports = <9>;
4317 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4318 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4319 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4320 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4321 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4322 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4323 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4324 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4325 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4327 #address-cells = <2>;
4328 #size-cells = <0>;
4329 #sound-dai-cells = <1>;
4334 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
4340 clock-names = "mclk",
4345 #clock-cells = <0>;
4346 clock-output-names = "mclk";
4347 #sound-dai-cells = <1>;
4351 compatible = "qcom,soundwire-v2.0.0";
4354 clock-names = "iface";
4358 pinctrl-0 = <&rx_swr_active>;
4359 pinctrl-names = "default";
4362 reset-names = "swr_audio_cgcr";
4363 qcom,din-ports = <1>;
4364 qcom,dout-ports = <11>;
4366 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4367 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4368 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4369 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4370 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4371 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4372 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
4373 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4374 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4376 #address-cells = <2>;
4377 #size-cells = <0>;
4378 #sound-dai-cells = <1>;
4383 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
4389 clock-names = "mclk",
4394 #clock-cells = <0>;
4395 clock-output-names = "mclk";
4396 #sound-dai-cells = <1>;
4400 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4406 clock-names = "mclk",
4411 #clock-cells = <0>;
4412 clock-output-names = "mclk";
4413 #sound-dai-cells = <1>;
4414 sound-name-prefix = "WSA";
4418 compatible = "qcom,soundwire-v2.0.0";
4421 clock-names = "iface";
4425 pinctrl-0 = <&wsa_swr_active>;
4426 pinctrl-names = "default";
4428 reset-names = "swr_audio_cgcr";
4430 qcom,din-ports = <4>;
4431 qcom,dout-ports = <9>;
4433 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4434 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4435 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4436 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4437 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4438 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4439 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4440 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4441 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4443 #address-cells = <2>;
4444 #size-cells = <0>;
4445 #sound-dai-cells = <1>;
4449 lpass_audiocc: clock-controller@6b6c000 {
4450 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
4452 #clock-cells = <1>;
4453 #reset-cells = <1>;
4457 compatible = "qcom,soundwire-v2.0.0";
4460 clock-names = "iface";
4463 interrupt-names = "core", "wakeup";
4466 reset-names = "swr_audio_cgcr";
4468 pinctrl-0 = <&tx_swr_active>;
4469 pinctrl-names = "default";
4471 qcom,din-ports = <4>;
4472 qcom,dout-ports = <1>;
4474 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
4475 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
4476 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
4477 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4478 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4479 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4480 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4481 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4482 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
4484 #address-cells = <2>;
4485 #size-cells = <0>;
4486 #sound-dai-cells = <1>;
4491 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
4496 clock-names = "mclk",
4500 #clock-cells = <0>;
4501 clock-output-names = "fsgen";
4502 #sound-dai-cells = <1>;
4506 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
4512 clock-names = "core", "audio";
4514 gpio-controller;
4515 #gpio-cells = <2>;
4516 gpio-ranges = <&lpass_tlmm 0 0 23>;
4518 tx_swr_active: tx-swr-active-state {
4519 clk-pins {
4522 drive-strength = <2>;
4523 slew-rate = <1>;
4524 bias-disable;
4527 data-pins {
4530 drive-strength = <2>;
4531 slew-rate = <1>;
4532 bias-bus-hold;
4536 rx_swr_active: rx-swr-active-state {
4537 clk-pins {
4540 drive-strength = <2>;
4541 slew-rate = <1>;
4542 bias-disable;
4545 data-pins {
4548 drive-strength = <2>;
4549 slew-rate = <1>;
4550 bias-bus-hold;
4554 dmic01_default: dmic01-default-state {
4555 clk-pins {
4558 drive-strength = <8>;
4559 output-high;
4562 data-pins {
4565 drive-strength = <8>;
4566 input-enable;
4570 dmic23_default: dmic23-default-state {
4571 clk-pins {
4574 drive-strength = <8>;
4575 output-high;
4578 data-pins {
4581 drive-strength = <8>;
4582 input-enable;
4586 wsa_swr_active: wsa-swr-active-state {
4587 clk-pins {
4590 drive-strength = <2>;
4591 slew-rate = <1>;
4592 bias-disable;
4595 data-pins {
4598 drive-strength = <2>;
4599 slew-rate = <1>;
4600 bias-bus-hold;
4604 wsa2_swr_active: wsa2-swr-active-state {
4605 clk-pins {
4608 drive-strength = <2>;
4609 slew-rate = <1>;
4610 bias-disable;
4613 data-pins {
4616 drive-strength = <2>;
4617 slew-rate = <1>;
4618 bias-bus-hold;
4623 lpasscc: clock-controller@6ea0000 {
4624 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
4626 #clock-cells = <1>;
4627 #reset-cells = <1>;
4631 compatible = "qcom,x1e80100-lpass-ag-noc";
4634 qcom,bcm-voters = <&apps_bcm_voter>;
4636 #interconnect-cells = <2>;
4640 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
4643 qcom,bcm-voters = <&apps_bcm_voter>;
4645 #interconnect-cells = <2>;
4649 compatible = "qcom,x1e80100-lpass-lpicx-noc";
4652 qcom,bcm-voters = <&apps_bcm_voter>;
4654 #interconnect-cells = <2>;
4658 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4663 interrupt-names = "hc_irq", "pwr_irq";
4668 clock-names = "iface", "core", "xo";
4670 qcom,dll-config = <0x0007642c>;
4671 qcom,ddr-config = <0x80040868>;
4672 power-domains = <&rpmhpd RPMHPD_CX>;
4673 operating-points-v2 = <&sdhc2_opp_table>;
4679 interconnect-names = "sdhc-ddr", "cpu-sdhc";
4680 bus-width = <4>;
4681 dma-coherent;
4685 sdhc2_opp_table: opp-table {
4686 compatible = "operating-points-v2";
4688 opp-19200000 {
4689 opp-hz = /bits/ 64 <19200000>;
4690 required-opps = <&rpmhpd_opp_min_svs>;
4693 opp-50000000 {
4694 opp-hz = /bits/ 64 <50000000>;
4695 required-opps = <&rpmhpd_opp_low_svs>;
4698 opp-100000000 {
4699 opp-hz = /bits/ 64 <100000000>;
4700 required-opps = <&rpmhpd_opp_svs>;
4703 opp-202000000 {
4704 opp-hz = /bits/ 64 <202000000>;
4705 required-opps = <&rpmhpd_opp_svs_l1>;
4711 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4716 interrupt-names = "hc_irq", "pwr_irq";
4721 clock-names = "iface", "core", "xo";
4723 qcom,dll-config = <0x0007642c>;
4724 qcom,ddr-config = <0x80040868>;
4725 power-domains = <&rpmhpd RPMHPD_CX>;
4726 operating-points-v2 = <&sdhc4_opp_table>;
4732 interconnect-names = "sdhc-ddr", "cpu-sdhc";
4733 bus-width = <4>;
4734 dma-coherent;
4738 sdhc4_opp_table: opp-table {
4739 compatible = "operating-points-v2";
4741 opp-19200000 {
4742 opp-hz = /bits/ 64 <19200000>;
4743 required-opps = <&rpmhpd_opp_min_svs>;
4746 opp-50000000 {
4747 opp-hz = /bits/ 64 <50000000>;
4748 required-opps = <&rpmhpd_opp_low_svs>;
4751 opp-100000000 {
4752 opp-hz = /bits/ 64 <100000000>;
4753 required-opps = <&rpmhpd_opp_svs>;
4756 opp-202000000 {
4757 opp-hz = /bits/ 64 <202000000>;
4758 required-opps = <&rpmhpd_opp_svs_l1>;
4764 compatible = "qcom,x1e80100-snps-eusb2-phy",
4765 "qcom,sm8550-snps-eusb2-phy";
4767 #phy-cells = <0>;
4770 clock-names = "ref";
4778 compatible = "qcom,x1e80100-snps-eusb2-phy",
4779 "qcom,sm8550-snps-eusb2-phy";
4781 #phy-cells = <0>;
4784 clock-names = "ref";
4792 compatible = "qcom,x1e80100-snps-eusb2-phy",
4793 "qcom,sm8550-snps-eusb2-phy";
4795 #phy-cells = <0>;
4798 clock-names = "ref";
4806 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4813 clock-names = "aux",
4820 reset-names = "phy",
4823 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
4825 #clock-cells = <0>;
4826 clock-output-names = "usb_mp_phy0_pipe_clk";
4828 #phy-cells = <0>;
4834 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4841 clock-names = "aux",
4848 reset-names = "phy",
4851 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
4853 #clock-cells = <0>;
4854 clock-output-names = "usb_mp_phy1_pipe_clk";
4856 #phy-cells = <0>;
4862 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4874 clock-names = "cfg_noc",
4884 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4886 assigned-clock-rates = <19200000>,
4889 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4890 <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
4891 <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
4892 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
4893 interrupt-names = "pwr_event",
4898 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4899 required-opps = <&rpmhpd_opp_nom>;
4907 interconnect-names = "usb-ddr",
4908 "apps-usb";
4910 wakeup-source;
4912 #address-cells = <2>;
4913 #size-cells = <2>;
4928 phy-names = "usb2-phy",
4929 "usb3-phy";
4934 snps,dis-u1-entry-quirk;
4935 snps,dis-u2-entry-quirk;
4937 dma-coherent;
4940 #address-cells = <1>;
4941 #size-cells = <0>;
4954 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4962 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4964 #address-cells = <2>;
4965 #size-cells = <2>;
4977 clock-names = "cfg_noc",
4987 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4989 assigned-clock-rates = <19200000>, <200000000>;
4991 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
4992 <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
4993 <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
4994 interrupt-names = "pwr_event",
4998 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4999 required-opps = <&rpmhpd_opp_nom>;
5007 interconnect-names = "usb-ddr",
5008 "apps-usb";
5010 qcom,select-utmi-as-pipe-clk;
5011 wakeup-source;
5021 phy-names = "usb2-phy";
5022 maximum-speed = "high-speed";
5023 snps,dis-u1-entry-quirk;
5024 snps,dis-u2-entry-quirk;
5026 dma-coherent;
5036 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
5048 clock-names = "cfg_noc",
5058 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
5060 assigned-clock-rates = <19200000>,
5063 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
5064 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
5065 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
5066 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
5067 <&pdc 52 IRQ_TYPE_EDGE_BOTH>,
5068 <&pdc 51 IRQ_TYPE_EDGE_BOTH>,
5069 <&pdc 54 IRQ_TYPE_EDGE_BOTH>,
5070 <&pdc 53 IRQ_TYPE_EDGE_BOTH>,
5071 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
5072 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
5073 interrupt-names = "pwr_event_1", "pwr_event_2",
5079 power-domains = <&gcc GCC_USB30_MP_GDSC>;
5080 required-opps = <&rpmhpd_opp_nom>;
5088 interconnect-names = "usb-ddr",
5089 "apps-usb";
5091 wakeup-source;
5093 #address-cells = <2>;
5094 #size-cells = <2>;
5109 phy-names = "usb2-0", "usb3-0",
5110 "usb2-1", "usb3-1";
5116 snps,dis-u1-entry-quirk;
5117 snps,dis-u2-entry-quirk;
5119 dma-coherent;
5124 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
5136 clock-names = "cfg_noc",
5146 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5148 assigned-clock-rates = <19200000>,
5151 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
5152 <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
5153 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
5154 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
5155 interrupt-names = "pwr_event",
5160 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
5161 required-opps = <&rpmhpd_opp_nom>;
5165 wakeup-source;
5167 #address-cells = <2>;
5168 #size-cells = <2>;
5183 phy-names = "usb2-phy",
5184 "usb3-phy";
5189 snps,dis-u1-entry-quirk;
5190 snps,dis-u2-entry-quirk;
5192 dma-coherent;
5195 #address-cells = <1>;
5196 #size-cells = <0>;
5209 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
5217 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
5229 clock-names = "cfg_noc",
5239 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
5241 assigned-clock-rates = <19200000>,
5244 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
5245 <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
5246 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
5247 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
5248 interrupt-names = "pwr_event",
5253 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
5254 required-opps = <&rpmhpd_opp_nom>;
5262 interconnect-names = "usb-ddr",
5263 "apps-usb";
5265 wakeup-source;
5267 #address-cells = <2>;
5268 #size-cells = <2>;
5283 phy-names = "usb2-phy",
5284 "usb3-phy";
5289 snps,dis-u1-entry-quirk;
5290 snps,dis-u2-entry-quirk;
5292 dma-coherent;
5295 #address-cells = <1>;
5296 #size-cells = <0>;
5309 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
5316 iris: video-codec@aa00000 {
5317 compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris";
5322 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
5326 power-domain-names = "venus",
5330 operating-points-v2 = <&iris_opp_table>;
5335 clock-names = "iface",
5343 interconnect-names = "cpu-cfg",
5344 "video-mem";
5346 memory-region = <&video_mem>;
5349 reset-names = "bus";
5353 dma-coherent;
5362 iris_opp_table: opp-table {
5363 compatible = "operating-points-v2";
5365 opp-192000000 {
5366 opp-hz = /bits/ 64 <192000000>;
5367 required-opps = <&rpmhpd_opp_low_svs_d1>,
5371 opp-240000000 {
5372 opp-hz = /bits/ 64 <240000000>;
5373 required-opps = <&rpmhpd_opp_svs>,
5377 opp-338000000 {
5378 opp-hz = /bits/ 64 <338000000>;
5379 required-opps = <&rpmhpd_opp_svs>,
5383 opp-366000000 {
5384 opp-hz = /bits/ 64 <366000000>;
5385 required-opps = <&rpmhpd_opp_svs_l1>,
5389 opp-444000000 {
5390 opp-hz = /bits/ 64 <444000000>;
5391 required-opps = <&rpmhpd_opp_nom>,
5395 opp-481000000 {
5396 opp-hz = /bits/ 64 <481000000>;
5397 required-opps = <&rpmhpd_opp_turbo>,
5403 videocc: clock-controller@aaf0000 {
5404 compatible = "qcom,x1e80100-videocc";
5408 power-domains = <&rpmhpd RPMHPD_MMCX>,
5410 required-opps = <&rpmhpd_opp_low_svs>,
5412 #clock-cells = <1>;
5413 #reset-cells = <1>;
5414 #power-domain-cells = <1>;
5417 mdss: display-subsystem@ae00000 {
5418 compatible = "qcom,x1e80100-mdss";
5420 reg-names = "mdss";
5436 interconnect-names = "mdp0-mem",
5437 "mdp1-mem",
5438 "cpu-cfg";
5440 power-domains = <&dispcc MDSS_GDSC>;
5444 interrupt-controller;
5445 #interrupt-cells = <1>;
5447 #address-cells = <2>;
5448 #size-cells = <2>;
5453 mdss_mdp: display-controller@ae01000 {
5454 compatible = "qcom,x1e80100-dpu";
5457 reg-names = "mdp",
5460 interrupts-extended = <&mdss 0>;
5467 clock-names = "nrt_bus",
5473 operating-points-v2 = <&mdp_opp_table>;
5475 power-domains = <&rpmhpd RPMHPD_MMCX>;
5478 #address-cells = <1>;
5479 #size-cells = <0>;
5485 remote-endpoint = <&mdss_dp0_in>;
5493 remote-endpoint = <&mdss_dp1_in>;
5501 remote-endpoint = <&mdss_dp3_in>;
5509 remote-endpoint = <&mdss_dp2_in>;
5514 mdp_opp_table: opp-table {
5515 compatible = "operating-points-v2";
5517 opp-200000000 {
5518 opp-hz = /bits/ 64 <200000000>;
5519 required-opps = <&rpmhpd_opp_low_svs>;
5522 opp-325000000 {
5523 opp-hz = /bits/ 64 <325000000>;
5524 required-opps = <&rpmhpd_opp_svs>;
5527 opp-375000000 {
5528 opp-hz = /bits/ 64 <375000000>;
5529 required-opps = <&rpmhpd_opp_svs_l1>;
5532 opp-514000000 {
5533 opp-hz = /bits/ 64 <514000000>;
5534 required-opps = <&rpmhpd_opp_nom>;
5537 opp-575000000 {
5538 opp-hz = /bits/ 64 <575000000>;
5539 required-opps = <&rpmhpd_opp_nom_l1>;
5544 mdss_dp0: displayport-controller@ae90000 {
5545 compatible = "qcom,x1e80100-dp";
5552 interrupts-extended = <&mdss 12>;
5560 clock-names = "core_iface",
5567 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5570 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5574 operating-points-v2 = <&mdss_dp0_opp_table>;
5576 power-domains = <&rpmhpd RPMHPD_MMCX>;
5579 phy-names = "dp";
5581 #sound-dai-cells = <0>;
5586 #address-cells = <1>;
5587 #size-cells = <0>;
5593 remote-endpoint = <&mdss_intf0_out>;
5601 data-lanes = <0 1 2 3>;
5602 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
5607 mdss_dp0_opp_table: opp-table {
5608 compatible = "operating-points-v2";
5610 opp-160000000 {
5611 opp-hz = /bits/ 64 <160000000>;
5612 required-opps = <&rpmhpd_opp_low_svs>;
5615 opp-270000000 {
5616 opp-hz = /bits/ 64 <270000000>;
5617 required-opps = <&rpmhpd_opp_svs>;
5620 opp-540000000 {
5621 opp-hz = /bits/ 64 <540000000>;
5622 required-opps = <&rpmhpd_opp_svs_l1>;
5625 opp-810000000 {
5626 opp-hz = /bits/ 64 <810000000>;
5627 required-opps = <&rpmhpd_opp_nom>;
5632 mdss_dp1: displayport-controller@ae98000 {
5633 compatible = "qcom,x1e80100-dp";
5640 interrupts-extended = <&mdss 13>;
5648 clock-names = "core_iface",
5655 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5658 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5662 operating-points-v2 = <&mdss_dp1_opp_table>;
5664 power-domains = <&rpmhpd RPMHPD_MMCX>;
5667 phy-names = "dp";
5669 #sound-dai-cells = <0>;
5674 #address-cells = <1>;
5675 #size-cells = <0>;
5681 remote-endpoint = <&mdss_intf4_out>;
5689 data-lanes = <0 1 2 3>;
5690 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
5695 mdss_dp1_opp_table: opp-table {
5696 compatible = "operating-points-v2";
5698 opp-160000000 {
5699 opp-hz = /bits/ 64 <160000000>;
5700 required-opps = <&rpmhpd_opp_low_svs>;
5703 opp-270000000 {
5704 opp-hz = /bits/ 64 <270000000>;
5705 required-opps = <&rpmhpd_opp_svs>;
5708 opp-540000000 {
5709 opp-hz = /bits/ 64 <540000000>;
5710 required-opps = <&rpmhpd_opp_svs_l1>;
5713 opp-810000000 {
5714 opp-hz = /bits/ 64 <810000000>;
5715 required-opps = <&rpmhpd_opp_nom>;
5720 mdss_dp2: displayport-controller@ae9a000 {
5721 compatible = "qcom,x1e80100-dp";
5728 interrupts-extended = <&mdss 14>;
5736 clock-names = "core_iface",
5743 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5746 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5750 operating-points-v2 = <&mdss_dp2_opp_table>;
5752 power-domains = <&rpmhpd RPMHPD_MMCX>;
5755 phy-names = "dp";
5757 #sound-dai-cells = <0>;
5762 #address-cells = <1>;
5763 #size-cells = <0>;
5768 remote-endpoint = <&mdss_intf6_out>;
5776 data-lanes = <0 1 2 3>;
5777 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
5782 mdss_dp2_opp_table: opp-table {
5783 compatible = "operating-points-v2";
5785 opp-160000000 {
5786 opp-hz = /bits/ 64 <160000000>;
5787 required-opps = <&rpmhpd_opp_low_svs>;
5790 opp-270000000 {
5791 opp-hz = /bits/ 64 <270000000>;
5792 required-opps = <&rpmhpd_opp_svs>;
5795 opp-540000000 {
5796 opp-hz = /bits/ 64 <540000000>;
5797 required-opps = <&rpmhpd_opp_svs_l1>;
5800 opp-810000000 {
5801 opp-hz = /bits/ 64 <810000000>;
5802 required-opps = <&rpmhpd_opp_nom>;
5807 mdss_dp3: displayport-controller@aea0000 {
5808 compatible = "qcom,x1e80100-dp";
5815 interrupts-extended = <&mdss 15>;
5822 clock-names = "core_iface",
5828 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5830 assigned-clock-parents = <&mdss_dp3_phy 0>,
5833 operating-points-v2 = <&mdss_dp3_opp_table>;
5835 power-domains = <&rpmhpd RPMHPD_MMCX>;
5838 phy-names = "dp";
5840 #sound-dai-cells = <0>;
5845 #address-cells = <1>;
5846 #size-cells = <0>;
5852 remote-endpoint = <&mdss_intf5_out>;
5864 mdss_dp3_opp_table: opp-table {
5865 compatible = "operating-points-v2";
5867 opp-160000000 {
5868 opp-hz = /bits/ 64 <160000000>;
5869 required-opps = <&rpmhpd_opp_low_svs>;
5872 opp-270000000 {
5873 opp-hz = /bits/ 64 <270000000>;
5874 required-opps = <&rpmhpd_opp_svs>;
5877 opp-540000000 {
5878 opp-hz = /bits/ 64 <540000000>;
5879 required-opps = <&rpmhpd_opp_svs_l1>;
5882 opp-810000000 {
5883 opp-hz = /bits/ 64 <810000000>;
5884 required-opps = <&rpmhpd_opp_nom>;
5892 compatible = "qcom,x1e80100-dp-phy";
5900 clock-names = "aux",
5903 power-domains = <&rpmhpd RPMHPD_MX>;
5905 #clock-cells = <1>;
5906 #phy-cells = <0>;
5912 compatible = "qcom,x1e80100-dp-phy";
5920 clock-names = "aux",
5923 power-domains = <&rpmhpd RPMHPD_MX>;
5925 #clock-cells = <1>;
5926 #phy-cells = <0>;
5931 dispcc: clock-controller@af00000 {
5932 compatible = "qcom,x1e80100-dispcc";
5950 power-domains = <&rpmhpd RPMHPD_MMCX>;
5951 required-opps = <&rpmhpd_opp_low_svs>;
5952 #clock-cells = <1>;
5953 #reset-cells = <1>;
5954 #power-domain-cells = <1>;
5957 pdc: interrupt-controller@b220000 { label
5958 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
5961 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
5964 #interrupt-cells = <2>;
5965 interrupt-parent = <&intc>;
5966 interrupt-controller;
5969 aoss_qmp: power-management@c300000 {
5970 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
5972 interrupt-parent = <&ipcc>;
5973 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
5977 #clock-cells = <0>;
5981 compatible = "qcom,rpmh-stats";
5986 compatible = "qcom,x1e80100-spmi-pmic-arb";
5990 reg-names = "core", "chnls", "obsrvr";
5995 #address-cells = <2>;
5996 #size-cells = <2>;
6002 reg-names = "cnfg", "intr";
6004 interrupt-names = "periph_irq";
6005 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
6006 interrupt-controller;
6007 #interrupt-cells = <4>;
6009 #address-cells = <2>;
6010 #size-cells = <0>;
6016 reg-names = "cnfg", "intr";
6018 interrupt-names = "periph_irq";
6019 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
6020 interrupt-controller;
6021 #interrupt-cells = <4>;
6023 #address-cells = <2>;
6024 #size-cells = <0>;
6029 compatible = "qcom,x1e80100-tlmm";
6034 gpio-controller;
6035 #gpio-cells = <2>;
6037 interrupt-controller;
6038 #interrupt-cells = <2>;
6040 gpio-ranges = <&tlmm 0 0 239>;
6041 wakeup-parent = <&pdc>;
6043 edp0_hpd_default: edp0-hpd-default-state {
6046 bias-disable;
6049 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
6053 drive-strength = <2>;
6054 bias-pull-up = <2200>;
6057 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
6061 drive-strength = <2>;
6062 bias-pull-up = <2200>;
6065 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
6069 drive-strength = <2>;
6070 bias-pull-up = <2200>;
6073 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
6077 drive-strength = <2>;
6078 bias-pull-up = <2200>;
6081 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
6085 drive-strength = <2>;
6086 bias-pull-up = <2200>;
6089 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
6093 drive-strength = <2>;
6094 bias-pull-up = <2200>;
6097 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
6101 drive-strength = <2>;
6102 bias-pull-up = <2200>;
6105 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
6109 drive-strength = <2>;
6110 bias-pull-up = <2200>;
6113 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
6117 drive-strength = <2>;
6118 bias-pull-up = <2200>;
6121 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
6125 drive-strength = <2>;
6126 bias-pull-up = <2200>;
6129 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
6133 drive-strength = <2>;
6134 bias-pull-up = <2200>;
6137 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
6141 drive-strength = <2>;
6142 bias-pull-up = <2200>;
6145 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
6149 drive-strength = <2>;
6150 bias-pull-up = <2200>;
6153 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
6157 drive-strength = <2>;
6158 bias-pull-up = <2200>;
6161 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
6165 drive-strength = <2>;
6166 bias-pull-up = <2200>;
6169 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
6173 drive-strength = <2>;
6174 bias-pull-up = <2200>;
6177 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
6181 drive-strength = <2>;
6182 bias-pull-up = <2200>;
6185 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
6189 drive-strength = <2>;
6190 bias-pull-up = <2200>;
6193 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
6197 drive-strength = <2>;
6198 bias-pull-up = <2200>;
6201 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
6205 drive-strength = <2>;
6206 bias-pull-up = <2200>;
6209 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
6213 drive-strength = <2>;
6214 bias-pull-up = <2200>;
6217 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
6221 drive-strength = <2>;
6222 bias-pull-up = <2200>;
6225 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
6229 drive-strength = <2>;
6230 bias-pull-up = <2200>;
6233 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
6237 drive-strength = <2>;
6238 bias-pull-up = <2200>;
6241 qup_spi0_cs: qup-spi0-cs-state {
6244 drive-strength = <6>;
6245 bias-disable;
6248 qup_spi0_data_clk: qup-spi0-data-clk-state {
6252 drive-strength = <6>;
6253 bias-disable;
6256 qup_spi1_cs: qup-spi1-cs-state {
6259 drive-strength = <6>;
6260 bias-disable;
6263 qup_spi1_data_clk: qup-spi1-data-clk-state {
6267 drive-strength = <6>;
6268 bias-disable;
6271 qup_spi2_cs: qup-spi2-cs-state {
6274 drive-strength = <6>;
6275 bias-disable;
6278 qup_spi2_data_clk: qup-spi2-data-clk-state {
6282 drive-strength = <6>;
6283 bias-disable;
6286 qup_spi3_cs: qup-spi3-cs-state {
6289 drive-strength = <6>;
6290 bias-disable;
6293 qup_spi3_data_clk: qup-spi3-data-clk-state {
6297 drive-strength = <6>;
6298 bias-disable;
6301 qup_spi4_cs: qup-spi4-cs-state {
6304 drive-strength = <6>;
6305 bias-disable;
6308 qup_spi4_data_clk: qup-spi4-data-clk-state {
6312 drive-strength = <6>;
6313 bias-disable;
6316 qup_spi5_cs: qup-spi5-cs-state {
6319 drive-strength = <6>;
6320 bias-disable;
6323 qup_spi5_data_clk: qup-spi5-data-clk-state {
6327 drive-strength = <6>;
6328 bias-disable;
6331 qup_spi6_cs: qup-spi6-cs-state {
6334 drive-strength = <6>;
6335 bias-disable;
6338 qup_spi6_data_clk: qup-spi6-data-clk-state {
6342 drive-strength = <6>;
6343 bias-disable;
6346 qup_spi7_cs: qup-spi7-cs-state {
6349 drive-strength = <6>;
6350 bias-disable;
6353 qup_spi7_data_clk: qup-spi7-data-clk-state {
6357 drive-strength = <6>;
6358 bias-disable;
6361 qup_spi8_cs: qup-spi8-cs-state {
6364 drive-strength = <6>;
6365 bias-disable;
6368 qup_spi8_data_clk: qup-spi8-data-clk-state {
6372 drive-strength = <6>;
6373 bias-disable;
6376 qup_spi9_cs: qup-spi9-cs-state {
6379 drive-strength = <6>;
6380 bias-disable;
6383 qup_spi9_data_clk: qup-spi9-data-clk-state {
6387 drive-strength = <6>;
6388 bias-disable;
6391 qup_spi10_cs: qup-spi10-cs-state {
6394 drive-strength = <6>;
6395 bias-disable;
6398 qup_spi10_data_clk: qup-spi10-data-clk-state {
6402 drive-strength = <6>;
6403 bias-disable;
6406 qup_spi11_cs: qup-spi11-cs-state {
6409 drive-strength = <6>;
6410 bias-disable;
6413 qup_spi11_data_clk: qup-spi11-data-clk-state {
6417 drive-strength = <6>;
6418 bias-disable;
6421 qup_spi12_cs: qup-spi12-cs-state {
6424 drive-strength = <6>;
6425 bias-disable;
6428 qup_spi12_data_clk: qup-spi12-data-clk-state {
6432 drive-strength = <6>;
6433 bias-disable;
6436 qup_spi13_cs: qup-spi13-cs-state {
6439 drive-strength = <6>;
6440 bias-disable;
6443 qup_spi13_data_clk: qup-spi13-data-clk-state {
6447 drive-strength = <6>;
6448 bias-disable;
6451 qup_spi14_cs: qup-spi14-cs-state {
6454 drive-strength = <6>;
6455 bias-disable;
6458 qup_spi14_data_clk: qup-spi14-data-clk-state {
6462 drive-strength = <6>;
6463 bias-disable;
6466 qup_spi15_cs: qup-spi15-cs-state {
6469 drive-strength = <6>;
6470 bias-disable;
6473 qup_spi15_data_clk: qup-spi15-data-clk-state {
6477 drive-strength = <6>;
6478 bias-disable;
6481 qup_spi16_cs: qup-spi16-cs-state {
6484 drive-strength = <6>;
6485 bias-disable;
6488 qup_spi16_data_clk: qup-spi16-data-clk-state {
6492 drive-strength = <6>;
6493 bias-disable;
6496 qup_spi17_cs: qup-spi17-cs-state {
6499 drive-strength = <6>;
6500 bias-disable;
6503 qup_spi17_data_clk: qup-spi17-data-clk-state {
6507 drive-strength = <6>;
6508 bias-disable;
6511 qup_spi18_cs: qup-spi18-cs-state {
6514 drive-strength = <6>;
6515 bias-disable;
6518 qup_spi18_data_clk: qup-spi18-data-clk-state {
6522 drive-strength = <6>;
6523 bias-disable;
6526 qup_spi19_cs: qup-spi19-cs-state {
6529 drive-strength = <6>;
6530 bias-disable;
6533 qup_spi19_data_clk: qup-spi19-data-clk-state {
6537 drive-strength = <6>;
6538 bias-disable;
6541 qup_spi20_cs: qup-spi20-cs-state {
6544 drive-strength = <6>;
6545 bias-disable;
6548 qup_spi20_data_clk: qup-spi20-data-clk-state {
6552 drive-strength = <6>;
6553 bias-disable;
6556 qup_spi21_cs: qup-spi21-cs-state {
6559 drive-strength = <6>;
6560 bias-disable;
6563 qup_spi21_data_clk: qup-spi21-data-clk-state {
6567 drive-strength = <6>;
6568 bias-disable;
6571 qup_spi22_cs: qup-spi22-cs-state {
6574 drive-strength = <6>;
6575 bias-disable;
6578 qup_spi22_data_clk: qup-spi22-data-clk-state {
6582 drive-strength = <6>;
6583 bias-disable;
6586 qup_spi23_cs: qup-spi23-cs-state {
6589 drive-strength = <6>;
6590 bias-disable;
6593 qup_spi23_data_clk: qup-spi23-data-clk-state {
6597 drive-strength = <6>;
6598 bias-disable;
6601 qup_uart2_default: qup-uart2-default-state {
6602 cts-pins {
6605 drive-strength = <2>;
6606 bias-disable;
6609 rts-pins {
6612 drive-strength = <2>;
6613 bias-disable;
6616 tx-pins {
6619 drive-strength = <2>;
6620 bias-disable;
6623 rx-pins {
6626 drive-strength = <2>;
6627 bias-disable;
6631 qup_uart14_default: qup-uart14-default-state {
6632 cts-pins {
6635 bias-bus-hold;
6638 rts-pins {
6641 drive-strength = <2>;
6642 bias-disable;
6645 tx-pins {
6648 drive-strength = <2>;
6649 bias-disable;
6652 rx-pins {
6655 bias-pull-up;
6659 qup_uart21_default: qup-uart21-default-state {
6660 tx-pins {
6663 drive-strength = <2>;
6664 bias-disable;
6667 rx-pins {
6670 drive-strength = <2>;
6671 bias-disable;
6675 sdc2_default: sdc2-default-state {
6676 clk-pins {
6678 drive-strength = <16>;
6679 bias-disable;
6682 cmd-pins {
6684 drive-strength = <10>;
6685 bias-pull-up;
6688 data-pins {
6690 drive-strength = <10>;
6691 bias-pull-up;
6695 sdc2_sleep: sdc2-sleep-state {
6696 clk-pins {
6698 drive-strength = <2>;
6699 bias-disable;
6702 cmd-pins {
6704 drive-strength = <2>;
6705 bias-pull-up;
6708 data-pins {
6710 drive-strength = <2>;
6711 bias-pull-up;
6717 compatible = "arm,coresight-stm", "arm,primecell";
6720 reg-names = "stm-base",
6721 "stm-stimulus-base";
6724 clock-names = "apb_pclk";
6726 out-ports {
6729 remote-endpoint = <&funnel0_in7>;
6736 compatible = "qcom,coresight-tpdm", "arm,primecell";
6740 clock-names = "apb_pclk";
6742 qcom,cmb-element-bits = <32>;
6743 qcom,cmb-msrs-num = <32>;
6746 out-ports {
6749 remote-endpoint = <&qdss_tpda_in0>;
6756 compatible = "qcom,coresight-tpda", "arm,primecell";
6760 clock-names = "apb_pclk";
6762 in-ports {
6763 #address-cells = <1>;
6764 #size-cells = <0>;
6770 remote-endpoint = <&dcc_tpdm_out>;
6778 remote-endpoint = <&qdss_tpdm_out>;
6783 out-ports {
6786 remote-endpoint = <&funnel0_in6>;
6793 compatible = "qcom,coresight-tpdm", "arm,primecell";
6797 clock-names = "apb_pclk";
6799 qcom,cmb-element-bits = <32>;
6800 qcom,cmb-msrs-num = <32>;
6802 out-ports {
6805 remote-endpoint = <&qdss_tpda_in1>;
6812 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6816 clock-names = "apb_pclk";
6818 in-ports {
6819 #address-cells = <1>;
6820 #size-cells = <0>;
6826 remote-endpoint = <&qdss_tpda_out>;
6834 remote-endpoint = <&stm_out>;
6839 out-ports {
6842 remote-endpoint = <&qdss_funnel_in0>;
6849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6853 clock-names = "apb_pclk";
6855 in-ports {
6856 #address-cells = <1>;
6857 #size-cells = <0>;
6863 remote-endpoint = <&tmess_funnel_out>;
6871 remote-endpoint = <&dlst_funnel_out>;
6879 remote-endpoint = <&dlct1_funnel_out>;
6884 out-ports {
6887 remote-endpoint = <&qdss_funnel_in1>;
6894 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6898 clock-names = "apb_pclk";
6900 in-ports {
6901 #address-cells = <1>;
6902 #size-cells = <0>;
6908 remote-endpoint = <&funnel0_out>;
6916 remote-endpoint = <&funnel1_out>;
6921 out-ports {
6924 remote-endpoint = <&aoss_funnel_in7>;
6931 compatible = "qcom,coresight-tpdm", "arm,primecell";
6935 clock-names = "apb_pclk";
6937 qcom,cmb-element-bits = <64>;
6938 qcom,cmb-msrs-num = <32>;
6940 out-ports {
6943 remote-endpoint = <&dlct2_tpda_in15>;
6950 compatible = "qcom,coresight-tpdm", "arm,primecell";
6954 clock-names = "apb_pclk";
6956 qcom,dsb-element-bits = <32>;
6957 qcom,dsb-msrs-num = <32>;
6959 out-ports {
6962 remote-endpoint = <&dlct1_tpda_in21>;
6969 compatible = "qcom,coresight-tpdm", "arm,primecell";
6973 clock-names = "apb_pclk";
6975 qcom,cmb-element-bits = <32>;
6976 qcom,cmb-msrs-num = <32>;
6978 out-ports {
6981 remote-endpoint = <&dlct1_tpda_in19>;
6988 compatible = "qcom,coresight-tpdm", "arm,primecell";
6992 clock-names = "apb_pclk";
6994 qcom,dsb-element-bits = <32>;
6995 qcom,dsb-msrs-num = <32>;
6997 out-ports {
7000 remote-endpoint = <&lpass_cx_funnel_in0>;
7007 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7011 clock-names = "apb_pclk";
7013 in-ports {
7016 remote-endpoint = <&lpass_cx_tpdm_out>;
7021 out-ports {
7024 remote-endpoint = <&dlct1_tpda_in4>;
7031 compatible = "arm,coresight-cti", "arm,primecell";
7035 clock-names = "apb_pclk";
7039 compatible = "qcom,coresight-tpdm", "arm,primecell";
7043 clock-names = "apb_pclk";
7045 qcom,dsb-element-bits = <32>;
7046 qcom,dsb-msrs-num = <32>;
7049 out-ports {
7052 remote-endpoint = <&dlct1_tpda_in20>;
7059 compatible = "qcom,coresight-tpdm", "arm,primecell";
7063 clock-names = "apb_pclk";
7065 qcom,dsb-element-bits = <32>;
7066 qcom,dsb-msrs-num = <32>;
7069 out-ports {
7072 remote-endpoint = <&dlst_tpda_in8>;
7079 compatible = "qcom,coresight-tpdm", "arm,primecell";
7083 clock-names = "apb_pclk";
7085 qcom,cmb-element-bits = <64>;
7086 qcom,cmb-msrs-num = <32>;
7088 out-ports {
7091 remote-endpoint = <&dlst_tpda_in9>;
7098 compatible = "qcom,coresight-tpda", "arm,primecell";
7102 clock-names = "apb_pclk";
7104 in-ports {
7105 #address-cells = <1>;
7106 #size-cells = <0>;
7112 remote-endpoint = <&dlst_tpdm0_out>;
7120 remote-endpoint = <&dlst_tpdm1_out>;
7125 out-ports {
7128 remote-endpoint = <&dlst_funnel_in0>;
7135 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7139 clock-names = "apb_pclk";
7141 in-ports {
7144 remote-endpoint = <&dlst_tpda_out>;
7149 out-ports {
7152 remote-endpoint = <&funnel1_in5>;
7159 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7163 clock-names = "apb_pclk";
7165 in-ports {
7166 #address-cells = <1>;
7167 #size-cells = <0>;
7173 remote-endpoint = <&ddr_lpi_funnel_out>;
7181 remote-endpoint = <&aoss_tpda_out>;
7189 remote-endpoint = <&qdss_funnel_out>;
7194 out-ports {
7197 remote-endpoint = <&etf0_in>;
7204 compatible = "arm,coresight-tmc", "arm,primecell";
7208 clock-names = "apb_pclk";
7210 in-ports {
7213 remote-endpoint = <&aoss_funnel_out>;
7218 out-ports {
7221 remote-endpoint = <&swao_rep_in>;
7228 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
7232 clock-names = "apb_pclk";
7234 in-ports {
7237 remote-endpoint = <&etf0_out>;
7242 out-ports {
7245 remote-endpoint = <&eud_in>;
7252 compatible = "qcom,coresight-tpda", "arm,primecell";
7256 clock-names = "apb_pclk";
7258 in-ports {
7259 #address-cells = <1>;
7260 #size-cells = <0>;
7266 remote-endpoint = <&aoss_tpdm0_out>;
7274 remote-endpoint = <&aoss_tpdm1_out>;
7282 remote-endpoint = <&aoss_tpdm2_out>;
7290 remote-endpoint = <&aoss_tpdm3_out>;
7298 remote-endpoint = <&aoss_tpdm4_out>;
7303 out-ports {
7306 remote-endpoint = <&aoss_funnel_in6>;
7313 compatible = "qcom,coresight-tpdm", "arm,primecell";
7317 clock-names = "apb_pclk";
7319 qcom,cmb-element-bits = <64>;
7320 qcom,cmb-msrs-num = <32>;
7322 out-ports {
7325 remote-endpoint = <&aoss_tpda_in0>;
7332 compatible = "qcom,coresight-tpdm", "arm,primecell";
7336 clock-names = "apb_pclk";
7338 qcom,cmb-element-bits = <64>;
7339 qcom,cmb-msrs-num = <32>;
7341 out-ports {
7344 remote-endpoint = <&aoss_tpda_in1>;
7351 compatible = "qcom,coresight-tpdm", "arm,primecell";
7355 clock-names = "apb_pclk";
7357 qcom,cmb-element-bits = <64>;
7358 qcom,cmb-msrs-num = <32>;
7360 out-ports {
7363 remote-endpoint = <&aoss_tpda_in2>;
7370 compatible = "qcom,coresight-tpdm", "arm,primecell";
7374 clock-names = "apb_pclk";
7376 qcom,cmb-element-bits = <64>;
7377 qcom,cmb-msrs-num = <32>;
7379 out-ports {
7382 remote-endpoint = <&aoss_tpda_in3>;
7389 compatible = "qcom,coresight-tpdm", "arm,primecell";
7393 clock-names = "apb_pclk";
7395 qcom,dsb-element-bits = <32>;
7396 qcom,dsb-msrs-num = <32>;
7398 out-ports {
7401 remote-endpoint = <&aoss_tpda_in4>;
7408 compatible = "qcom,coresight-tpdm", "arm,primecell";
7412 clock-names = "apb_pclk";
7414 qcom,dsb-element-bits = <32>;
7415 qcom,dsb-msrs-num = <32>;
7418 out-ports {
7421 remote-endpoint = <&ddr_lpi_tpda_in>;
7428 compatible = "qcom,coresight-tpda", "arm,primecell";
7432 clock-names = "apb_pclk";
7435 in-ports {
7438 remote-endpoint = <&lpicc_tpdm_out>;
7443 out-ports {
7446 remote-endpoint = <&ddr_lpi_funnel_in0>;
7453 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7457 clock-names = "apb_pclk";
7460 in-ports {
7463 remote-endpoint = <&ddr_lpi_tpda_out>;
7468 out-ports {
7471 remote-endpoint = <&aoss_funnel_in3>;
7478 compatible = "qcom,coresight-tpdm", "arm,primecell";
7482 clock-names = "apb_pclk";
7484 qcom,dsb-element-bits = <32>;
7485 qcom,dsb-msrs-num = <32>;
7487 out-ports {
7490 remote-endpoint = <&mm_funnel_in4>;
7497 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7501 clock-names = "apb_pclk";
7503 in-ports {
7504 #address-cells = <1>;
7505 #size-cells = <0>;
7511 remote-endpoint = <&mm_tpdm_out>;
7516 out-ports {
7519 remote-endpoint = <&dlct2_tpda_in4>;
7526 compatible = "qcom,coresight-tpdm", "arm,primecell";
7530 clock-names = "apb_pclk";
7532 qcom,dsb-element-bits = <32>;
7533 qcom,dsb-msrs-num = <32>;
7535 out-ports {
7538 remote-endpoint = <&dlct1_tpda_in26>;
7545 compatible = "qcom,coresight-tpdm", "arm,primecell";
7549 clock-names = "apb_pclk";
7551 qcom,cmb-element-bits = <64>;
7552 qcom,cmb-msrs-num = <32>;
7554 out-ports {
7557 remote-endpoint = <&dlct1_tpda_in27>;
7564 compatible = "qcom,coresight-tpda", "arm,primecell";
7568 clock-names = "apb_pclk";
7570 in-ports {
7571 #address-cells = <1>;
7572 #size-cells = <0>;
7578 remote-endpoint = <&lpass_cx_funnel_out>;
7586 remote-endpoint = <&prng_tpdm_out>;
7594 remote-endpoint = <&qm_tpdm_out>;
7602 remote-endpoint = <&gcc_tpdm_out>;
7610 remote-endpoint = <&dlct1_tpdm_out>;
7618 remote-endpoint = <&ipcc_tpdm_out>;
7623 out-ports {
7626 remote-endpoint = <&dlct1_funnel_in0>;
7633 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7637 clock-names = "apb_pclk";
7639 in-ports {
7640 #address-cells = <1>;
7641 #size-cells = <0>;
7647 remote-endpoint = <&dlct1_tpda_out>;
7655 remote-endpoint = <&dlct2_funnel_out>;
7663 remote-endpoint = <&ddr_funnel0_out>;
7668 out-ports {
7671 remote-endpoint = <&funnel1_in6>;
7678 compatible = "qcom,coresight-tpdm", "arm,primecell";
7682 clock-names = "apb_pclk";
7684 qcom,cmb-element-bits = <64>;
7685 qcom,cmb-msrs-num = <32>;
7687 out-ports {
7690 remote-endpoint = <&dlct2_tpda_in16>;
7697 compatible = "qcom,coresight-tpdm", "arm,primecell";
7701 clock-names = "apb_pclk";
7703 qcom,cmb-element-bits = <64>;
7704 qcom,cmb-msrs-num = <32>;
7706 out-ports {
7709 remote-endpoint = <&dlct2_tpda_in17>;
7716 compatible = "qcom,coresight-tpda", "arm,primecell";
7720 clock-names = "apb_pclk";
7722 in-ports {
7723 #address-cells = <1>;
7724 #size-cells = <0>;
7730 remote-endpoint = <&mm_funnel_out>;
7738 remote-endpoint = <&mxa_tpdm_out>;
7746 remote-endpoint = <&dlct2_tpdm0_out>;
7754 remote-endpoint = <&dlct2_tpdm1_out>;
7759 out-ports {
7762 remote-endpoint = <&dlct2_funnel_in0>;
7769 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7773 clock-names = "apb_pclk";
7775 in-ports {
7778 remote-endpoint = <&dlct2_tpda_out>;
7783 out-ports {
7786 remote-endpoint = <&dlct1_funnel_in4>;
7793 compatible = "qcom,coresight-tpdm", "arm,primecell";
7797 clock-names = "apb_pclk";
7799 qcom,cmb-element-bits = <64>;
7800 qcom,cmb-msrs-num = <32>;
7801 qcom,dsb-element-bits = <32>;
7802 qcom,dsb-msrs-num = <32>;
7805 out-ports {
7808 remote-endpoint = <&tmess_tpda_in2>;
7815 compatible = "qcom,coresight-tpda", "arm,primecell";
7819 clock-names = "apb_pclk";
7821 in-ports {
7822 #address-cells = <1>;
7823 #size-cells = <0>;
7829 remote-endpoint = <&tmess_tpdm1_out>;
7834 out-ports {
7837 remote-endpoint = <&tmess_funnel_in0>;
7844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7848 clock-names = "apb_pclk";
7850 in-ports {
7853 remote-endpoint = <&tmess_tpda_out>;
7858 out-ports {
7861 remote-endpoint = <&funnel1_in2>;
7868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7872 clock-names = "apb_pclk";
7874 in-ports {
7875 #address-cells = <1>;
7876 #size-cells = <0>;
7882 remote-endpoint = <&ddr_funnel1_out>;
7887 out-ports {
7890 remote-endpoint = <&dlct1_funnel_in5>;
7897 compatible = "qcom,coresight-tpdm", "arm,primecell";
7901 clock-names = "apb_pclk";
7903 qcom,cmb-element-bits = <32>;
7904 qcom,cmb-msrs-num = <32>;
7906 out-ports {
7909 remote-endpoint = <&llcc_tpda_in0>;
7916 compatible = "qcom,coresight-tpdm", "arm,primecell";
7920 clock-names = "apb_pclk";
7922 qcom,cmb-element-bits = <32>;
7923 qcom,cmb-msrs-num = <32>;
7925 out-ports {
7928 remote-endpoint = <&llcc_tpda_in1>;
7935 compatible = "qcom,coresight-tpdm", "arm,primecell";
7939 clock-names = "apb_pclk";
7941 qcom,cmb-element-bits = <32>;
7942 qcom,cmb-msrs-num = <32>;
7944 out-ports {
7947 remote-endpoint = <&llcc_tpda_in2>;
7954 compatible = "qcom,coresight-tpdm", "arm,primecell";
7958 clock-names = "apb_pclk";
7960 qcom,cmb-element-bits = <32>;
7961 qcom,cmb-msrs-num = <32>;
7963 out-ports {
7966 remote-endpoint = <&llcc_tpda_in3>;
7973 compatible = "qcom,coresight-tpdm", "arm,primecell";
7977 clock-names = "apb_pclk";
7979 qcom,cmb-element-bits = <32>;
7980 qcom,cmb-msrs-num = <32>;
7982 out-ports {
7985 remote-endpoint = <&llcc_tpda_in4>;
7992 compatible = "qcom,coresight-tpdm", "arm,primecell";
7996 clock-names = "apb_pclk";
7998 qcom,cmb-element-bits = <32>;
7999 qcom,cmb-msrs-num = <32>;
8001 out-ports {
8004 remote-endpoint = <&llcc_tpda_in5>;
8011 compatible = "qcom,coresight-tpdm", "arm,primecell";
8015 clock-names = "apb_pclk";
8017 qcom,cmb-element-bits = <32>;
8018 qcom,cmb-msrs-num = <32>;
8020 out-ports {
8023 remote-endpoint = <&llcc_tpda_in6>;
8030 compatible = "qcom,coresight-tpdm", "arm,primecell";
8034 clock-names = "apb_pclk";
8036 qcom,cmb-element-bits = <32>;
8037 qcom,cmb-msrs-num = <32>;
8039 out-ports {
8042 remote-endpoint = <&llcc_tpda_in7>;
8049 compatible = "qcom,coresight-tpda", "arm,primecell";
8053 clock-names = "apb_pclk";
8055 in-ports {
8056 #address-cells = <1>;
8057 #size-cells = <0>;
8063 remote-endpoint = <&llcc0_tpdm_out>;
8071 remote-endpoint = <&llcc1_tpdm_out>;
8079 remote-endpoint = <&llcc2_tpdm_out>;
8087 remote-endpoint = <&llcc3_tpdm_out>;
8095 remote-endpoint = <&llcc4_tpdm_out>;
8103 remote-endpoint = <&llcc5_tpdm_out>;
8111 remote-endpoint = <&llcc6_tpdm_out>;
8119 remote-endpoint = <&llcc7_tpdm_out>;
8124 out-ports {
8127 remote-endpoint = <&ddr_funnel1_in0>;
8134 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8138 clock-names = "apb_pclk";
8140 in-ports {
8143 remote-endpoint = <&llcc_tpda_out>;
8148 out-ports {
8151 remote-endpoint = <&ddr_funnel0_in6>;
8158 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
8259 #iommu-cells = <2>;
8260 #global-interrupts = <1>;
8262 dma-coherent;
8266 compatible = "arm,smmu-v3";
8268 #iommu-cells = <1>;
8272 interrupt-names = "eventq",
8274 "cmdq-sync";
8275 dma-coherent;
8279 intc: interrupt-controller@17000000 { label
8280 compatible = "arm,gic-v3";
8286 #interrupt-cells = <3>;
8287 interrupt-controller;
8289 #redistributor-regions = <1>;
8290 redistributor-stride = <0x0 0x40000>;
8292 #address-cells = <2>;
8293 #size-cells = <2>;
8296 gic_its: msi-controller@17040000 {
8297 compatible = "arm,gic-v3-its";
8300 msi-controller;
8301 #msi-cells = <1>;
8306 compatible = "qcom,x1e80100-cpucp-mbox";
8309 #mbox-cells = <1>;
8313 compatible = "qcom,rpmh-rsc";
8317 reg-names = "drv-0", "drv-1", "drv-2";
8322 qcom,tcs-offset = <0xd00>;
8323 qcom,drv-id = <2>;
8324 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
8328 power-domains = <&system_pd>;
8330 apps_bcm_voter: bcm-voter {
8331 compatible = "qcom,bcm-voter";
8334 rpmhcc: clock-controller {
8335 compatible = "qcom,x1e80100-rpmh-clk";
8338 clock-names = "xo";
8340 #clock-cells = <1>;
8343 rpmhpd: power-controller {
8344 compatible = "qcom,x1e80100-rpmhpd";
8346 operating-points-v2 = <&rpmhpd_opp_table>;
8348 #power-domain-cells = <1>;
8350 rpmhpd_opp_table: opp-table {
8351 compatible = "operating-points-v2";
8353 rpmhpd_opp_ret: opp-16 {
8354 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
8357 rpmhpd_opp_min_svs: opp-48 {
8358 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
8361 rpmhpd_opp_low_svs_d2: opp-52 {
8362 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
8365 rpmhpd_opp_low_svs_d1: opp-56 {
8366 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
8369 rpmhpd_opp_low_svs_d0: opp-60 {
8370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
8373 rpmhpd_opp_low_svs: opp-64 {
8374 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
8377 rpmhpd_opp_low_svs_l1: opp-80 {
8378 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
8381 rpmhpd_opp_svs: opp-128 {
8382 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
8385 rpmhpd_opp_svs_l0: opp-144 {
8386 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
8389 rpmhpd_opp_svs_l1: opp-192 {
8390 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
8393 rpmhpd_opp_nom: opp-256 {
8394 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
8397 rpmhpd_opp_nom_l1: opp-320 {
8398 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
8401 rpmhpd_opp_nom_l2: opp-336 {
8402 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
8405 rpmhpd_opp_turbo: opp-384 {
8406 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
8409 rpmhpd_opp_turbo_l1: opp-416 {
8410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
8417 compatible = "arm,armv7-timer-mem";
8420 #address-cells = <2>;
8421 #size-cells = <1>;
8431 frame-number = <0>;
8439 frame-number = <1>;
8449 frame-number = <2>;
8459 frame-number = <3>;
8469 frame-number = <4>;
8479 frame-number = <5>;
8489 frame-number = <6>;
8496 compatible = "mmio-sram";
8499 #address-cells = <1>;
8500 #size-cells = <1>;
8503 cpu_scp_lpri0: scp-sram-section@0 {
8504 compatible = "arm,scmi-shmem";
8508 cpu_scp_lpri1: scp-sram-section@200 {
8509 compatible = "arm,scmi-shmem";
8515 compatible = "arm,sbsa-gwdt";
8522 compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
8524 #address-cells = <1>;
8525 #size-cells = <1>;
8527 gpu_speed_bin: gpu-speed-bin@119 {
8534 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
8542 operating-points-v2 = <&llcc_bwmon_opp_table>;
8544 llcc_bwmon_opp_table: opp-table {
8545 compatible = "operating-points-v2";
8547 opp-0 {
8548 opp-peak-kBps = <800000>;
8551 opp-1 {
8552 opp-peak-kBps = <2188000>;
8555 opp-2 {
8556 opp-peak-kBps = <3072000>;
8559 opp-3 {
8560 opp-peak-kBps = <6220800>;
8563 opp-4 {
8564 opp-peak-kBps = <6835200>;
8567 opp-5 {
8568 opp-peak-kBps = <8371200>;
8571 opp-6 {
8572 opp-peak-kBps = <10944000>;
8575 opp-7 {
8576 opp-peak-kBps = <12748800>;
8579 opp-8 {
8580 opp-peak-kBps = <14745600>;
8583 opp-9 {
8584 opp-peak-kBps = <16896000>;
8591 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8599 operating-points-v2 = <&cpu_bwmon_opp_table>;
8604 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8612 operating-points-v2 = <&cpu_bwmon_opp_table>;
8614 cpu_bwmon_opp_table: opp-table {
8615 compatible = "operating-points-v2";
8617 opp-0 {
8618 opp-peak-kBps = <4800000>;
8621 opp-1 {
8622 opp-peak-kBps = <7464000>;
8625 opp-2 {
8626 opp-peak-kBps = <9600000>;
8629 opp-3 {
8630 opp-peak-kBps = <12896000>;
8633 opp-4 {
8634 opp-peak-kBps = <14928000>;
8637 opp-5 {
8638 opp-peak-kBps = <17064000>;
8645 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8653 operating-points-v2 = <&cpu_bwmon_opp_table>;
8656 system-cache-controller@25000000 {
8657 compatible = "qcom,x1e80100-llcc";
8668 reg-names = "llcc0_base",
8682 compatible = "qcom,x1e80100-cdsp-pas";
8685 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
8690 interrupt-names = "wdog",
8694 "stop-ack";
8697 clock-names = "xo";
8699 power-domains = <&rpmhpd RPMHPD_CX>,
8702 power-domain-names = "cx",
8709 memory-region = <&cdsp_mem>,
8714 qcom,smem-states = <&smp2p_cdsp_out 0>;
8715 qcom,smem-state-names = "stop";
8719 glink-edge {
8720 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
8727 qcom,remote-pid = <5>;
8731 qcom,glink-channels = "fastrpcglink-apps-dsp";
8733 qcom,non-secure-domain;
8734 #address-cells = <1>;
8735 #size-cells = <0>;
8737 compute-cb@1 {
8738 compatible = "qcom,fastrpc-compute-cb";
8741 dma-coherent;
8744 compute-cb@2 {
8745 compatible = "qcom,fastrpc-compute-cb";
8748 dma-coherent;
8751 compute-cb@3 {
8752 compatible = "qcom,fastrpc-compute-cb";
8755 dma-coherent;
8758 compute-cb@4 {
8759 compatible = "qcom,fastrpc-compute-cb";
8762 dma-coherent;
8765 compute-cb@5 {
8766 compatible = "qcom,fastrpc-compute-cb";
8769 dma-coherent;
8772 compute-cb@6 {
8773 compatible = "qcom,fastrpc-compute-cb";
8776 dma-coherent;
8779 compute-cb@7 {
8780 compatible = "qcom,fastrpc-compute-cb";
8783 dma-coherent;
8786 compute-cb@8 {
8787 compatible = "qcom,fastrpc-compute-cb";
8790 dma-coherent;
8793 /* note: compute-cb@9 is secure */
8795 compute-cb@10 {
8796 compatible = "qcom,fastrpc-compute-cb";
8799 dma-coherent;
8802 compute-cb@11 {
8803 compatible = "qcom,fastrpc-compute-cb";
8806 dma-coherent;
8809 compute-cb@12 {
8810 compatible = "qcom,fastrpc-compute-cb";
8813 dma-coherent;
8816 compute-cb@13 {
8817 compatible = "qcom,fastrpc-compute-cb";
8820 dma-coherent;
8828 compatible = "arm,armv8-timer";
8836 thermal_zones: thermal-zones {
8837 aoss0-thermal {
8838 thermal-sensors = <&tsens0 0>;
8841 trip-point0 {
8847 aoss0-critical {
8855 cpu0-0-top-thermal {
8856 thermal-sensors = <&tsens0 1>;
8859 cpu-critical {
8867 cpu0-0-btm-thermal {
8868 thermal-sensors = <&tsens0 2>;
8871 cpu-critical {
8879 cpu0-1-top-thermal {
8880 thermal-sensors = <&tsens0 3>;
8883 cpu-critical {
8891 cpu0-1-btm-thermal {
8892 thermal-sensors = <&tsens0 4>;
8895 cpu-critical {
8903 cpu0-2-top-thermal {
8904 thermal-sensors = <&tsens0 5>;
8907 cpu-critical {
8915 cpu0-2-btm-thermal {
8916 thermal-sensors = <&tsens0 6>;
8919 cpu-critical {
8927 cpu0-3-top-thermal {
8928 thermal-sensors = <&tsens0 7>;
8931 cpu-critical {
8939 cpu0-3-btm-thermal {
8940 thermal-sensors = <&tsens0 8>;
8943 cpu-critical {
8951 cpuss0-top-thermal {
8952 thermal-sensors = <&tsens0 9>;
8955 cpuss2-critical {
8963 cpuss0-btm-thermal {
8964 thermal-sensors = <&tsens0 10>;
8967 cpuss2-critical {
8975 mem-thermal {
8976 thermal-sensors = <&tsens0 11>;
8979 trip-point0 {
8985 mem-critical {
8993 video-thermal {
8994 thermal-sensors = <&tsens0 12>;
8997 trip-point0 {
9003 video-critical {
9011 aoss1-thermal {
9012 thermal-sensors = <&tsens1 0>;
9015 trip-point0 {
9021 aoss0-critical {
9029 cpu1-0-top-thermal {
9030 thermal-sensors = <&tsens1 1>;
9033 cpu-critical {
9041 cpu1-0-btm-thermal {
9042 thermal-sensors = <&tsens1 2>;
9045 cpu-critical {
9053 cpu1-1-top-thermal {
9054 thermal-sensors = <&tsens1 3>;
9057 cpu-critical {
9065 cpu1-1-btm-thermal {
9066 thermal-sensors = <&tsens1 4>;
9069 cpu-critical {
9077 cpu1-2-top-thermal {
9078 thermal-sensors = <&tsens1 5>;
9081 cpu-critical {
9089 cpu1-2-btm-thermal {
9090 thermal-sensors = <&tsens1 6>;
9093 cpu-critical {
9101 cpu1-3-top-thermal {
9102 thermal-sensors = <&tsens1 7>;
9105 cpu-critical {
9113 cpu1-3-btm-thermal {
9114 thermal-sensors = <&tsens1 8>;
9117 cpu-critical {
9125 cpuss1-top-thermal {
9126 thermal-sensors = <&tsens1 9>;
9129 cpuss2-critical {
9137 cpuss1-btm-thermal {
9138 thermal-sensors = <&tsens1 10>;
9141 cpuss2-critical {
9149 aoss2-thermal {
9150 thermal-sensors = <&tsens2 0>;
9153 trip-point0 {
9159 aoss0-critical {
9167 cpu2-0-top-thermal {
9168 thermal-sensors = <&tsens2 1>;
9171 cpu-critical {
9179 cpu2-0-btm-thermal {
9180 thermal-sensors = <&tsens2 2>;
9183 cpu-critical {
9191 cpu2-1-top-thermal {
9192 thermal-sensors = <&tsens2 3>;
9195 cpu-critical {
9203 cpu2-1-btm-thermal {
9204 thermal-sensors = <&tsens2 4>;
9207 cpu-critical {
9215 cpu2-2-top-thermal {
9216 thermal-sensors = <&tsens2 5>;
9219 cpu-critical {
9227 cpu2-2-btm-thermal {
9228 thermal-sensors = <&tsens2 6>;
9231 cpu-critical {
9239 cpu2-3-top-thermal {
9240 thermal-sensors = <&tsens2 7>;
9243 cpu-critical {
9251 cpu2-3-btm-thermal {
9252 thermal-sensors = <&tsens2 8>;
9255 cpu-critical {
9263 cpuss2-top-thermal {
9264 thermal-sensors = <&tsens2 9>;
9267 cpuss2-critical {
9275 cpuss2-btm-thermal {
9276 thermal-sensors = <&tsens2 10>;
9279 cpuss2-critical {
9287 aoss3-thermal {
9288 thermal-sensors = <&tsens3 0>;
9291 trip-point0 {
9297 aoss0-critical {
9305 nsp0-thermal {
9306 thermal-sensors = <&tsens3 1>;
9309 trip-point0 {
9315 nsp0-critical {
9323 nsp1-thermal {
9324 thermal-sensors = <&tsens3 2>;
9327 trip-point0 {
9333 nsp1-critical {
9341 nsp2-thermal {
9342 thermal-sensors = <&tsens3 3>;
9345 trip-point0 {
9351 nsp2-critical {
9359 nsp3-thermal {
9360 thermal-sensors = <&tsens3 4>;
9363 trip-point0 {
9369 nsp3-critical {
9377 gpuss-0-thermal {
9378 polling-delay-passive = <200>;
9380 thermal-sensors = <&tsens3 5>;
9382 cooling-maps {
9385 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9390 gpuss0_alert0: trip-point0 {
9396 gpu-critical {
9404 gpuss-1-thermal {
9405 polling-delay-passive = <200>;
9407 thermal-sensors = <&tsens3 6>;
9409 cooling-maps {
9412 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9417 gpuss1_alert0: trip-point0 {
9423 gpu-critical {
9431 gpuss-2-thermal {
9432 polling-delay-passive = <200>;
9434 thermal-sensors = <&tsens3 7>;
9436 cooling-maps {
9439 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9444 gpuss2_alert0: trip-point0 {
9450 gpu-critical {
9458 gpuss-3-thermal {
9459 polling-delay-passive = <200>;
9461 thermal-sensors = <&tsens3 8>;
9463 cooling-maps {
9466 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9471 gpuss3_alert0: trip-point0 {
9477 gpu-critical {
9485 gpuss-4-thermal {
9486 polling-delay-passive = <200>;
9488 thermal-sensors = <&tsens3 9>;
9490 cooling-maps {
9493 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9498 gpuss4_alert0: trip-point0 {
9504 gpu-critical {
9512 gpuss-5-thermal {
9513 polling-delay-passive = <200>;
9515 thermal-sensors = <&tsens3 10>;
9517 cooling-maps {
9520 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9525 gpuss5_alert0: trip-point0 {
9531 gpu-critical {
9539 gpuss-6-thermal {
9540 polling-delay-passive = <200>;
9542 thermal-sensors = <&tsens3 11>;
9544 cooling-maps {
9547 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9552 gpuss6_alert0: trip-point0 {
9558 gpu-critical {
9566 gpuss-7-thermal {
9567 polling-delay-passive = <200>;
9569 thermal-sensors = <&tsens3 12>;
9571 cooling-maps {
9574 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9579 gpuss7_alert0: trip-point0 {
9585 gpu-critical {
9593 camera0-thermal {
9594 thermal-sensors = <&tsens3 13>;
9597 trip-point0 {
9603 camera0-critical {
9611 camera1-thermal {
9612 thermal-sensors = <&tsens3 14>;
9615 trip-point0 {
9621 camera0-critical {