Lines Matching +full:1 +full:c600000
37 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
158 #dma-cells = <1>;
205 #address-cells = <1>;
216 i2s1_port: port@1 {
217 reg = <1>;
241 #address-cells = <1>;
252 i2s2_port: port@1 {
253 reg = <1>;
277 #address-cells = <1>;
288 i2s3_port: port@1 {
289 reg = <1>;
313 #address-cells = <1>;
324 i2s4_port: port@1 {
325 reg = <1>;
349 #address-cells = <1>;
360 i2s5_port: port@1 {
361 reg = <1>;
385 #address-cells = <1>;
396 i2s6_port: port@1 {
397 reg = <1>;
414 #address-cells = <1>;
425 sfc1_out_port: port@1 {
426 reg = <1>;
442 #address-cells = <1>;
453 sfc2_out_port: port@1 {
454 reg = <1>;
470 #address-cells = <1>;
481 sfc3_out_port: port@1 {
482 reg = <1>;
498 #address-cells = <1>;
509 sfc4_out_port: port@1 {
510 reg = <1>;
526 #address-cells = <1>;
537 port@1 {
538 reg = <1>;
578 #address-cells = <1>;
589 port@1 {
590 reg = <1>;
630 #address-cells = <1>;
641 port@1 {
642 reg = <1>;
682 #address-cells = <1>;
693 port@1 {
694 reg = <1>;
734 #address-cells = <1>;
745 adx1_out1_port: port@1 {
746 reg = <1>;
786 #address-cells = <1>;
797 adx2_out1_port: port@1 {
798 reg = <1>;
838 #address-cells = <1>;
849 adx3_out1_port: port@1 {
850 reg = <1>;
890 #address-cells = <1>;
901 adx4_out1_port: port@1 {
902 reg = <1>;
949 #address-cells = <1>;
960 dmic1_port: port@1 {
961 reg = <1>;
983 #address-cells = <1>;
994 dmic2_port: port@1 {
995 reg = <1>;
1017 #address-cells = <1>;
1028 dmic3_port: port@1 {
1029 reg = <1>;
1051 #address-cells = <1>;
1062 dmic4_port: port@1 {
1063 reg = <1>;
1085 #address-cells = <1>;
1096 dspk1_port: port@1 {
1097 reg = <1>;
1119 #address-cells = <1>;
1130 dspk2_port: port@1 {
1131 reg = <1>;
1163 #address-cells = <1>;
1175 ope1_out_port: port@1 {
1193 #address-cells = <1>;
1204 mvc1_out_port: port@1 {
1205 reg = <1>;
1221 #address-cells = <1>;
1232 mvc2_out_port: port@1 {
1233 reg = <1>;
1249 #address-cells = <1>;
1260 port@1 {
1378 dmas = <&adma 1>, <&adma 1>,
1424 #address-cells = <1>;
1435 admaif1_port: port@1 {
1596 #address-cells = <1>;
1608 port@1 {
1719 #address-cells = <1>;
1730 port@1 {
1930 xbar_dmic1_port: port@1a {
1938 xbar_dmic2_port: port@1b {
1946 xbar_dmic3_port: port@1c {
1954 xbar_dmic4_port: port@1d {
1962 xbar_dspk1_port: port@1e {
1970 xbar_dspk2_port: port@1f {
2642 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
2673 #dma-cells = <1>;
2719 #interconnect-cells = <1>;
2787 #address-cells = <1>;
2805 #address-cells = <1>;
2824 #address-cells = <1>;
2843 #address-cells = <1>;
2862 #address-cells = <1>;
2888 #address-cells = <1>;
2907 #address-cells = <1>;
2926 #address-cells = <1>;
2945 #address-cells = <1>;
3028 #address-cells = <1>;
3054 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
3056 pinctrl-1 = <&sdmmc1_1v8>;
3059 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
3060 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
3090 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
3091 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
3143 usb2-1 {
3171 usb3-1 {
3197 usb2-1 {
3213 usb3-1 {
3298 nvidia,int-threshold = <1>;
3299 #timestamp-cells = <1>;
3808 #iommu-cells = <1>;
3847 nvidia,int-threshold = <1>;
3849 #timestamp-cells = <1>;
3856 #address-cells = <1>;
3875 #address-cells = <1>;
3894 #address-cells = <1>;
3962 sdmmc1_1v8: sdmmc1-1v8 {
3972 sdmmc3_1v8: sdmmc3-1v8 {
3983 aon-fabric@c600000 {
4018 #redistributor-regions = <1>;
4156 #global-interrupts = <1>;
4157 #iommu-cells = <1>;
4299 #iommu-cells = <1>;
4342 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
4343 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
4344 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
4345 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
4346 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
4347 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
4348 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
4349 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
4350 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
4351 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
4352 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
4353 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
4354 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
4355 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
4356 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
4357 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
4457 #interrupt-cells = <1>;
4471 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4511 #interrupt-cells = <1>;
4525 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4565 #interrupt-cells = <1>;
4579 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4642 num-lanes = <1>;
4644 linux,pci-domain = <1>;
4657 #interrupt-cells = <1>;
4661 nvidia,bpmp = <&bpmp 1>;
4671 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4696 num-lanes = <1>;
4711 #interrupt-cells = <1>;
4725 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4750 num-lanes = <1>;
4765 #interrupt-cells = <1>;
4779 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4819 #interrupt-cells = <1>;
4833 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4904 #interrupt-cells = <1>;
4918 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4958 #interrupt-cells = <1>;
4972 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5050 #interrupt-cells = <1>;
5064 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5142 #interrupt-cells = <1>;
5156 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5211 #address-cells = <1>;
5212 #size-cells = <1>;
5235 #clock-cells = <1>;
5236 #reset-cells = <1>;
5237 #power-domain-cells = <1>;
5248 #address-cells = <1>;
5254 #thermal-sensor-cells = <1>;
5259 #address-cells = <1>;
5727 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;