Lines Matching +full:0 +full:x3aa0000
19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
123 reg = <0x0 0x2600000 0x0 0x210000>;
160 dma-channel-mask = <0xfffffffe>;
175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
179 reg = <0x0 0x02900800 0x0 0x800>;
189 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
194 reg = <0x0 0x2901000 0x0 0x100>;
206 #size-cells = <0>;
208 port@0 {
209 reg = <0>;
230 reg = <0x0 0x2901100 0x0 0x100>;
242 #size-cells = <0>;
244 port@0 {
245 reg = <0>;
266 reg = <0x0 0x2901200 0x0 0x100>;
278 #size-cells = <0>;
280 port@0 {
281 reg = <0>;
302 reg = <0x0 0x2901300 0x0 0x100>;
314 #size-cells = <0>;
316 port@0 {
317 reg = <0>;
338 reg = <0x0 0x2901400 0x0 0x100>;
350 #size-cells = <0>;
352 port@0 {
353 reg = <0>;
374 reg = <0x0 0x2901500 0x0 0x100>;
386 #size-cells = <0>;
388 port@0 {
389 reg = <0>;
410 reg = <0x0 0x2902000 0x0 0x200>;
415 #size-cells = <0>;
417 port@0 {
418 reg = <0>;
438 reg = <0x0 0x2902200 0x0 0x200>;
443 #size-cells = <0>;
445 port@0 {
446 reg = <0>;
466 reg = <0x0 0x2902400 0x0 0x200>;
471 #size-cells = <0>;
473 port@0 {
474 reg = <0>;
494 reg = <0x0 0x2902600 0x0 0x200>;
499 #size-cells = <0>;
501 port@0 {
502 reg = <0>;
522 reg = <0x0 0x2903000 0x0 0x100>;
527 #size-cells = <0>;
529 port@0 {
530 reg = <0>;
574 reg = <0x0 0x2903100 0x0 0x100>;
579 #size-cells = <0>;
581 port@0 {
582 reg = <0>;
626 reg = <0x0 0x2903200 0x0 0x100>;
631 #size-cells = <0>;
633 port@0 {
634 reg = <0>;
678 reg = <0x0 0x2903300 0x0 0x100>;
683 #size-cells = <0>;
685 port@0 {
686 reg = <0>;
730 reg = <0x0 0x2903800 0x0 0x100>;
735 #size-cells = <0>;
737 port@0 {
738 reg = <0>;
782 reg = <0x0 0x2903900 0x0 0x100>;
787 #size-cells = <0>;
789 port@0 {
790 reg = <0>;
834 reg = <0x0 0x2903a00 0x0 0x100>;
839 #size-cells = <0>;
841 port@0 {
842 reg = <0>;
886 reg = <0x0 0x2903b00 0x0 0x100>;
891 #size-cells = <0>;
893 port@0 {
894 reg = <0>;
939 reg = <0x0 0x2904000 0x0 0x100>;
950 #size-cells = <0>;
952 port@0 {
953 reg = <0>;
973 reg = <0x0 0x2904100 0x0 0x100>;
984 #size-cells = <0>;
986 port@0 {
987 reg = <0>;
1007 reg = <0x0 0x2904200 0x0 0x100>;
1018 #size-cells = <0>;
1020 port@0 {
1021 reg = <0>;
1041 reg = <0x0 0x2904300 0x0 0x100>;
1052 #size-cells = <0>;
1054 port@0 {
1055 reg = <0>;
1075 reg = <0x0 0x2905000 0x0 0x100>;
1086 #size-cells = <0>;
1088 port@0 {
1089 reg = <0>;
1109 reg = <0x0 0x2905100 0x0 0x100>;
1120 #size-cells = <0>;
1122 port@0 {
1123 reg = <0>;
1143 reg = <0x0 0x2908000 0x0 0x100>;
1153 reg = <0x0 0x2908100 0x0 0x100>;
1159 reg = <0x0 0x2908200 0x0 0x200>;
1164 #size-cells = <0>;
1166 port@0 {
1167 reg = <0x0>;
1176 reg = <0x1>;
1189 reg = <0x0 0x290a000 0x0 0x200>;
1194 #size-cells = <0>;
1196 port@0 {
1197 reg = <0>;
1217 reg = <0x0 0x290a200 0x0 0x200>;
1222 #size-cells = <0>;
1224 port@0 {
1225 reg = <0>;
1245 reg = <0x0 0x290bb00 0x0 0x800>;
1250 #size-cells = <0>;
1252 port@0 {
1253 reg = <0x0>;
1261 reg = <0x1>;
1269 reg = <0x2>;
1277 reg = <0x3>;
1285 reg = <0x4>;
1293 reg = <0x5>;
1301 reg = <0x6>;
1309 reg = <0x7>;
1317 reg = <0x8>;
1325 reg = <0x9>;
1333 reg = <0xa>;
1341 reg = <0xb>;
1349 reg = <0xc>;
1357 reg = <0xd>;
1365 reg = <0xe>;
1377 reg = <0x0 0x0290f000 0x0 0x1000>;
1425 #size-cells = <0>;
1427 admaif0_port: port@0 {
1428 reg = <0x0>;
1436 reg = <0x1>;
1444 reg = <0x2>;
1452 reg = <0x3>;
1460 reg = <0x4>;
1468 reg = <0x5>;
1476 reg = <0x6>;
1484 reg = <0x7>;
1492 reg = <0x8>;
1500 reg = <0x9>;
1508 reg = <0xa>;
1516 reg = <0xb>;
1524 reg = <0xc>;
1532 reg = <0xd>;
1540 reg = <0xe>;
1548 reg = <0xf>;
1556 reg = <0x10>;
1564 reg = <0x11>;
1572 reg = <0x12>;
1580 reg = <0x13>;
1592 reg = <0x0 0x2910000 0x0 0x2000>;
1597 #size-cells = <0>;
1599 port@0 {
1600 reg = <0x0>;
1609 reg = <0x1>;
1618 reg = <0x2>;
1627 reg = <0x3>;
1636 reg = <0x4>;
1645 reg = <0x5>;
1654 reg = <0x6>;
1663 reg = <0x7>;
1672 reg = <0x8>;
1681 reg = <0x9>;
1690 reg = <0xa>;
1699 reg = <0xb>;
1708 reg = <0xc>;
1720 #size-cells = <0>;
1722 port@0 {
1723 reg = <0x0>;
1731 reg = <0x1>;
1739 reg = <0x2>;
1747 reg = <0x3>;
1755 reg = <0x4>;
1763 reg = <0x5>;
1771 reg = <0x6>;
1779 reg = <0x7>;
1787 reg = <0x8>;
1795 reg = <0x9>;
1803 reg = <0xa>;
1811 reg = <0xb>;
1819 reg = <0xc>;
1827 reg = <0xd>;
1835 reg = <0xe>;
1843 reg = <0xf>;
1851 reg = <0x10>;
1859 reg = <0x11>;
1867 reg = <0x12>;
1875 reg = <0x13>;
1883 reg = <0x14>;
1891 reg = <0x15>;
1899 reg = <0x16>;
1907 reg = <0x17>;
1915 reg = <0x18>;
1923 reg = <0x19>;
1931 reg = <0x1a>;
1939 reg = <0x1b>;
1947 reg = <0x1c>;
1955 reg = <0x1d>;
1963 reg = <0x1e>;
1971 reg = <0x1f>;
1979 reg = <0x20>;
1987 reg = <0x21>;
1995 reg = <0x22>;
2003 reg = <0x23>;
2011 reg = <0x24>;
2019 reg = <0x25>;
2027 reg = <0x26>;
2035 reg = <0x27>;
2043 reg = <0x28>;
2051 reg = <0x29>;
2059 reg = <0x2a>;
2067 reg = <0x2b>;
2075 reg = <0x2c>;
2083 reg = <0x2d>;
2091 reg = <0x2e>;
2099 reg = <0x2f>;
2107 reg = <0x30>;
2115 reg = <0x31>;
2123 reg = <0x32>;
2131 reg = <0x33>;
2139 reg = <0x34>;
2147 reg = <0x35>;
2155 reg = <0x36>;
2163 reg = <0x37>;
2171 reg = <0x38>;
2179 reg = <0x39>;
2187 reg = <0x3a>;
2195 reg = <0x3b>;
2203 reg = <0x3c>;
2211 reg = <0x3d>;
2219 reg = <0x3e>;
2227 reg = <0x3f>;
2235 reg = <0x40>;
2243 reg = <0x41>;
2251 reg = <0x42>;
2259 reg = <0x43>;
2267 reg = <0x44>;
2275 reg = <0x45>;
2283 reg = <0x46>;
2291 reg = <0x47>;
2299 reg = <0x48>;
2307 reg = <0x49>;
2315 reg = <0x4a>;
2323 reg = <0x4b>;
2331 reg = <0x4c>;
2339 reg = <0x4d>;
2347 reg = <0x4e>;
2355 reg = <0x4f>;
2363 reg = <0x50>;
2371 reg = <0x51>;
2379 reg = <0x52>;
2387 reg = <0x53>;
2395 reg = <0x54>;
2403 reg = <0x55>;
2411 reg = <0x56>;
2419 reg = <0x57>;
2427 reg = <0x58>;
2435 reg = <0x59>;
2443 reg = <0x5a>;
2451 reg = <0x5b>;
2459 reg = <0x5c>;
2467 reg = <0x5d>;
2475 reg = <0x5e>;
2483 reg = <0x5f>;
2491 reg = <0x60>;
2499 reg = <0x61>;
2507 reg = <0x62>;
2515 reg = <0x63>;
2523 reg = <0x64>;
2531 reg = <0x65>;
2539 reg = <0x66>;
2547 reg = <0x67>;
2555 reg = <0x68>;
2563 reg = <0x69>;
2571 reg = <0x6a>;
2579 reg = <0x6b>;
2587 reg = <0x6c>;
2595 reg = <0x6d>;
2603 reg = <0x6e>;
2611 reg = <0x6f>;
2619 reg = <0x70>;
2627 reg = <0x71>;
2639 reg = <0x0 0x02930000 0x0 0x20000>;
2641 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
2684 reg = <0x0 0x02a41000 0x0 0x1000>,
2685 <0x0 0x02a42000 0x0 0x2000>;
2697 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
2698 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
2699 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
2700 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
2701 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
2702 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
2703 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
2704 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
2705 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
2706 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
2707 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
2708 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
2709 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
2710 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
2711 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
2712 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
2713 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
2714 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
2724 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
2725 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
2726 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
2741 * Limit the DMA range for memory clients to [38:0].
2743 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
2747 reg = <0x0 0x02c60000 0x0 0x90000>,
2748 <0x0 0x01780000 0x0 0x80000>;
2754 #interconnect-cells = <0>;
2762 reg = <0x0 0x03100000 0x0 0x10000>;
2773 reg = <0x0 0x03140000 0x0 0x10000>;
2784 reg = <0x0 0x3160000 0x0 0x100>;
2788 #size-cells = <0>;
2803 reg = <0x0 0x3180000 0x0 0x100>;
2806 #size-cells = <0>;
2822 reg = <0x0 0x3190000 0x0 0x100>;
2825 #size-cells = <0>;
2841 reg = <0x0 0x31b0000 0x0 0x100>;
2844 #size-cells = <0>;
2860 reg = <0x0 0x31c0000 0x0 0x100>;
2863 #size-cells = <0>;
2879 reg = <0x0 0x31d0000 0x0 0x10000>;
2886 reg = <0x0 0x31e0000 0x0 0x100>;
2889 #size-cells = <0>;
2905 reg = <0x0 0x03210000 0x0 0x1000>;
2908 #size-cells = <0>;
2924 reg = <0x0 0x03230000 0x0 0x1000>;
2927 #size-cells = <0>;
2943 reg = <0x0 0x3270000 0x0 0x1000>;
2946 #size-cells = <0>;
2956 reg = <0x0 0x3280000 0x0 0x10000>;
2966 reg = <0x0 0x3290000 0x0 0x10000>;
2976 reg = <0x0 0x32a0000 0x0 0x10000>;
2986 reg = <0x0 0x32c0000 0x0 0x10000>;
2996 reg = <0x0 0x32d0000 0x0 0x10000>;
3006 reg = <0x0 0x32e0000 0x0 0x10000>;
3016 reg = <0x0 0x32f0000 0x0 0x10000>;
3026 reg = <0x0 0x3300000 0x0 0x1000>;
3029 #size-cells = <0>;
3039 reg = <0x0 0x03400000 0x0 0x20000>;
3055 pinctrl-0 = <&sdmmc1_3v3>;
3057 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
3058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
3059 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
3060 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
3061 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
3062 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
3064 nvidia,default-trim = <0x8>;
3074 reg = <0x0 0x03460000 0x0 0x20000>;
3088 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
3089 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
3090 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
3091 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
3092 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
3093 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
3094 nvidia,default-tap = <0x8>;
3095 nvidia,default-trim = <0x14>;
3103 reg = <0x0 0x3510000 0x0 0x10000>;
3121 reg = <0x0 0x03520000 0x0 0x20000>,
3122 <0x0 0x03540000 0x0 0x10000>;
3137 usb2-0 {
3140 #phy-cells = <0>;
3146 #phy-cells = <0>;
3152 #phy-cells = <0>;
3158 #phy-cells = <0>;
3165 usb3-0 {
3168 #phy-cells = <0>;
3174 #phy-cells = <0>;
3180 #phy-cells = <0>;
3186 #phy-cells = <0>;
3193 usb2-0 {
3209 usb3-0 {
3229 reg = <0x0 0x03550000 0x0 0x8000>,
3230 <0x0 0x03558000 0x0 0x8000>;
3252 reg = <0x0 0x03610000 0x0 0x40000>,
3253 <0x0 0x03600000 0x0 0x10000>,
3254 <0x0 0x03650000 0x0 0x10000>;
3289 reg = <0x0 0x03810000 0x0 0x10000>;
3296 reg = <0x0 0x3aa0000 0x0 0x10000>;
3304 reg = <0x0 0x03c00000 0x0 0xa0000>;
3322 reg = <0x0 0x03e00000 0x0 0x10000>;
3325 #phy-cells = <0>;
3330 reg = <0x0 0x03e10000 0x0 0x10000>;
3333 #phy-cells = <0>;
3338 reg = <0x0 0x03e20000 0x0 0x10000>;
3341 #phy-cells = <0>;
3346 reg = <0x0 0x03e30000 0x0 0x10000>;
3349 #phy-cells = <0>;
3354 reg = <0x0 0x03e40000 0x0 0x10000>;
3357 #phy-cells = <0>;
3362 reg = <0x0 0x03e50000 0x0 0x10000>;
3365 #phy-cells = <0>;
3370 reg = <0x0 0x03e60000 0x0 0x10000>;
3373 #phy-cells = <0>;
3378 reg = <0x0 0x03e70000 0x0 0x10000>;
3381 #phy-cells = <0>;
3386 reg = <0x0 0x03e90000 0x0 0x10000>;
3389 #phy-cells = <0>;
3394 reg = <0x0 0x03ea0000 0x0 0x10000>;
3397 #phy-cells = <0>;
3402 reg = <0x0 0x03eb0000 0x0 0x10000>;
3405 #phy-cells = <0>;
3410 reg = <0x0 0x03ec0000 0x0 0x10000>;
3413 #phy-cells = <0>;
3418 reg = <0x0 0x03ed0000 0x0 0x10000>;
3421 #phy-cells = <0>;
3426 reg = <0x0 0x03ee0000 0x0 0x10000>;
3429 #phy-cells = <0>;
3434 reg = <0x0 0x03ef0000 0x0 0x10000>;
3437 #phy-cells = <0>;
3442 reg = <0x0 0x03f00000 0x0 0x10000>;
3445 #phy-cells = <0>;
3450 reg = <0x0 0x03f20000 0x0 0x10000>;
3453 #phy-cells = <0>;
3458 reg = <0x0 0x03f30000 0x0 0x10000>;
3461 #phy-cells = <0>;
3466 reg = <0x0 0x03f40000 0x0 0x10000>;
3469 #phy-cells = <0>;
3474 reg = <0x0 0x03f50000 0x0 0x10000>;
3477 #phy-cells = <0>;
3482 reg = <0x0 0x03f60000 0x0 0x10000>;
3485 #phy-cells = <0>;
3490 reg = <0x0 0x03f70000 0x0 0x10000>;
3493 #phy-cells = <0>;
3498 reg = <0x0 0x03f80000 0x0 0x10000>;
3501 #phy-cells = <0>;
3506 reg = <0x0 0x03f90000 0x0 0x10000>;
3509 #phy-cells = <0>;
3514 reg = <0x0 0x06800000 0x0 0x10000>,
3515 <0x0 0x06810000 0x0 0x10000>,
3516 <0x0 0x068a0000 0x0 0x10000>;
3556 reg = <0x0 0x06900000 0x0 0x10000>,
3557 <0x0 0x06910000 0x0 0x10000>,
3558 <0x0 0x069a0000 0x0 0x10000>;
3598 reg = <0x0 0x06a00000 0x0 0x10000>,
3599 <0x0 0x06a10000 0x0 0x10000>,
3600 <0x0 0x06aa0000 0x0 0x10000>;
3640 reg = <0x0 0x06b00000 0x0 0x10000>,
3641 <0x0 0x06b10000 0x0 0x10000>,
3642 <0x0 0x06ba0000 0x0 0x10000>;
3674 reg = <0x0 0x8000000 0x0 0x1000000>,
3675 <0x0 0x7000000 0x0 0x1000000>;
3806 stream-match-mask = <0x7f80>;
3816 reg = <0x0 0xb600000 0x0 0x40000>;
3823 reg = <0x0 0xbe00000 0x0 0x40000>;
3830 reg = <0x0 0x0c150000 0x0 0x90000>;
3836 * Shared interrupt 0 is routed only to AON/SPE, so
3845 reg = <0x0 0xc1e0000 0x0 0x10000>;
3854 reg = <0x0 0xc240000 0x0 0x100>;
3857 #size-cells = <0>;
3873 reg = <0x0 0xc250000 0x0 0x100>;
3876 #size-cells = <0>;
3886 dmas = <&gpcdma 0>, <&gpcdma 0>;
3892 reg = <0x0 0x0c260000 0x0 0x1000>;
3895 #size-cells = <0>;
3911 reg = <0x0 0x0c2a0000 0x0 0x10000>;
3922 reg = <0x0 0x0c2f0000 0x0 0x1000>,
3923 <0x0 0x0c2f1000 0x0 0x1000>;
3932 gpio-ranges = <&pinmux_aon 0 0 32>;
3937 reg = <0x0 0xc300000 0x0 0x4000>;
3942 reg = <0x0 0xc340000 0x0 0x10000>;
3952 reg = <0x0 0x0c360000 0x0 0x10000>,
3953 <0x0 0x0c370000 0x0 0x10000>,
3954 <0x0 0x0c380000 0x0 0x10000>,
3955 <0x0 0x0c390000 0x0 0x10000>,
3956 <0x0 0x0c3a0000 0x0 0x10000>;
3985 reg = <0x0 0xc600000 0x0 0x40000>;
3992 reg = <0x0 0xd600000 0x0 0x40000>;
3999 reg = <0x0 0xde00000 0x0 0x40000>;
4006 reg = <0x0 0x0e000000 0x0 0x5ffff>;
4013 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
4014 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
4025 reg = <0x0 0x10000000 0x0 0x1000000>;
4155 stream-match-mask = <0x7f80>;
4165 reg = <0x0 0x12000000 0x0 0x1000000>,
4166 <0x0 0x11000000 0x0 0x1000000>;
4297 stream-match-mask = <0x7f80>;
4307 reg = <0x0 0x13a00000 0x0 0x400000>;
4314 reg = <0x0 0x13e00000 0x0 0x10000>,
4315 <0x0 0x13e10000 0x0 0x10000>,
4316 <0x0 0x13e40000 0x0 0x10000>;
4334 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
4342 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
4361 reg = <0x0 0x15340000 0x0 0x00040000>;
4378 reg = <0x0 0x15480000 0x0 0x00040000>;
4398 nvidia,bl-manifest-offset = <0>;
4399 nvidia,bl-data-offset = <0>;
4400 nvidia,bl-code-offset = <0>;
4401 nvidia,os-manifest-offset = <0>;
4402 nvidia,os-data-offset = <0>;
4403 nvidia,os-code-offset = <0>;
4414 reg = <0x00 0x15820000 0x00 0x10000>;
4422 reg = <0x00 0x15840000 0x00 0x10000>;
4432 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
4433 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
4434 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4435 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4436 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4458 interrupt-map-mask = <0 0 0 0>;
4459 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
4467 bus-range = <0x0 0xff>;
4469 …ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4470 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4471 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4476 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
4477 iommu-map-mask = <0x0>;
4486 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
4487 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
4488 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4489 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
4490 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4512 interrupt-map-mask = <0 0 0 0>;
4513 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
4521 bus-range = <0x0 0xff>;
4523 …ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (1126…
4524 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4525 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4530 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
4531 iommu-map-mask = <0x0>;
4540 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
4541 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
4542 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4543 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
4544 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4566 interrupt-map-mask = <0 0 0 0>;
4567 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4575 bus-range = <0x0 0xff>;
4577 …ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4578 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4579 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4584 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4585 iommu-map-mask = <0x0>;
4594 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
4595 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4596 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
4597 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
4622 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4623 iommu-map-mask = <0x0>;
4632 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
4633 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
4634 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4635 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
4636 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
4658 interrupt-map-mask = <0 0 0 0>;
4659 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
4667 bus-range = <0x0 0xff>;
4669 …ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 …
4670 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4671 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4676 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
4677 iommu-map-mask = <0x0>;
4686 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
4687 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
4688 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4689 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
4690 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
4712 interrupt-map-mask = <0 0 0 0>;
4713 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
4721 bus-range = <0x0 0xff>;
4723 …ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 …
4724 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4725 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4730 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
4731 iommu-map-mask = <0x0>;
4740 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
4741 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
4742 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4743 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
4744 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4766 interrupt-map-mask = <0 0 0 0>;
4767 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4775 bus-range = <0x0 0xff>;
4777 …ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 …
4778 …<0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4779 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4784 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
4785 iommu-map-mask = <0x0>;
4794 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
4795 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
4796 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4797 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
4798 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4820 interrupt-map-mask = <0 0 0 0>;
4821 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4829 bus-range = <0x0 0xff>;
4831 …ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4832 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4833 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4838 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
4839 iommu-map-mask = <0x0>;
4848 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
4849 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
4850 0x00 0x36080000 0x0 0x00040000 /* DBI space (256K) */
4851 0x21 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
4879 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
4880 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
4881 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4882 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
4883 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4891 linux,pci-domain = <0>;
4905 interrupt-map-mask = <0 0 0 0>;
4906 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4908 nvidia,bpmp = <&bpmp 0>;
4914 bus-range = <0x0 0xff>;
4916 …ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4917 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4918 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4923 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
4924 iommu-map-mask = <0x0>;
4933 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
4934 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
4935 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4936 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4937 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4959 interrupt-map-mask = <0 0 0 0>;
4960 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4968 bus-range = <0x0 0xff>;
4970 …ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (1292…
4971 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4972 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4977 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
4978 iommu-map-mask = <0x0>;
4987 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
4988 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4989 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4990 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
5015 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
5016 iommu-map-mask = <0x0>;
5025 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
5026 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
5027 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5028 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
5029 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
5051 interrupt-map-mask = <0 0 0 0>;
5052 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
5060 bus-range = <0x0 0xff>;
5062 …ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
5063 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5064 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5069 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5070 iommu-map-mask = <0x0>;
5079 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
5080 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5081 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
5082 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
5107 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5108 iommu-map-mask = <0x0>;
5117 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
5118 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
5119 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5120 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
5121 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
5143 interrupt-map-mask = <0 0 0 0>;
5144 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
5152 bus-range = <0x0 0xff>;
5154 …ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832…
5155 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5156 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5161 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5162 iommu-map-mask = <0x0>;
5171 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
5172 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5173 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
5174 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
5199 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5200 iommu-map-mask = <0x0>;
5209 reg = <0x0 0x40000000 0x0 0x80000>;
5213 ranges = <0x0 0x0 0x40000000 0x80000>;
5218 reg = <0x70000 0x1000>;
5224 reg = <0x71000 0x1000>;
5249 #size-cells = <0>;
5260 #size-cells = <0>;
5262 cpu0_0: cpu@0 {
5265 reg = <0x00000>;
5284 reg = <0x00100>;
5303 reg = <0x00200>;
5322 reg = <0x00300>;
5341 reg = <0x10000>;
5360 reg = <0x10100>;
5379 reg = <0x10200>;
5398 reg = <0x10300>;
5417 reg = <0x20000>;
5436 reg = <0x20100>;
5455 reg = <0x20200>;
5474 reg = <0x20300>;
5726 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
5741 assigned-clock-parents = <0>,