Lines Matching +full:aspm +full:- +full:cmrt +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 compatible = "simple-bus";
23 #address-cells = <2>;
24 #size-cells = <2>;
28 compatible = "nvidia,tegra194-misc";
34 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security", "gpio";
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pinmux 0 0 169>;
93 cbb-noc@2300000 {
94 compatible = "nvidia,tegra194-cbb-noc";
104 compatible = "nvidia,tegra194-axi2apb";
115 compatible = "nvidia,tegra194-pinmux";
119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir {
123 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
124 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
134 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
135 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
143 compatible = "nvidia,tegra194-eqos",
144 "nvidia,tegra186-eqos",
145 "snps,dwc-qos-ethernet-4.10";
153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
155 reset-names = "eqos";
158 interconnect-names = "dma-mem", "write";
162 snps,write-requests = <1>;
163 snps,read-requests = <3>;
164 snps,burst-map = <0x7>;
169 gpcdma: dma-controller@2600000 {
170 compatible = "nvidia,tegra194-gpcdma",
171 "nvidia,tegra186-gpcdma";
174 reset-names = "gpcdma";
207 #dma-cells = <1>;
209 dma-coherent;
210 dma-channel-mask = <0xfffffffe>;
215 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,tegra210-aconnect";
219 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
223 #address-cells = <2>;
224 #size-cells = <2>;
228 compatible = "nvidia,tegra194-ahub",
229 "nvidia,tegra186-ahub";
232 clock-names = "ahub";
233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
235 assigned-clock-rates = <81600000>;
238 #address-cells = <2>;
239 #size-cells = <2>;
243 compatible = "nvidia,tegra194-i2s",
244 "nvidia,tegra210-i2s";
248 clock-names = "i2s", "sync_input";
249 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assigned-clock-rates = <1536000>;
252 sound-name-prefix = "I2S1";
257 compatible = "nvidia,tegra194-i2s",
258 "nvidia,tegra210-i2s";
262 clock-names = "i2s", "sync_input";
263 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assigned-clock-rates = <1536000>;
266 sound-name-prefix = "I2S2";
271 compatible = "nvidia,tegra194-i2s",
272 "nvidia,tegra210-i2s";
276 clock-names = "i2s", "sync_input";
277 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assigned-clock-rates = <1536000>;
280 sound-name-prefix = "I2S3";
285 compatible = "nvidia,tegra194-i2s",
286 "nvidia,tegra210-i2s";
290 clock-names = "i2s", "sync_input";
291 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assigned-clock-rates = <1536000>;
294 sound-name-prefix = "I2S4";
299 compatible = "nvidia,tegra194-i2s",
300 "nvidia,tegra210-i2s";
304 clock-names = "i2s", "sync_input";
305 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assigned-clock-rates = <1536000>;
308 sound-name-prefix = "I2S5";
313 compatible = "nvidia,tegra194-i2s",
314 "nvidia,tegra210-i2s";
318 clock-names = "i2s", "sync_input";
319 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assigned-clock-rates = <1536000>;
322 sound-name-prefix = "I2S6";
327 compatible = "nvidia,tegra194-sfc",
328 "nvidia,tegra210-sfc";
330 sound-name-prefix = "SFC1";
335 compatible = "nvidia,tegra194-sfc",
336 "nvidia,tegra210-sfc";
338 sound-name-prefix = "SFC2";
343 compatible = "nvidia,tegra194-sfc",
344 "nvidia,tegra210-sfc";
346 sound-name-prefix = "SFC3";
351 compatible = "nvidia,tegra194-sfc",
352 "nvidia,tegra210-sfc";
354 sound-name-prefix = "SFC4";
359 compatible = "nvidia,tegra194-amx";
361 sound-name-prefix = "AMX1";
366 compatible = "nvidia,tegra194-amx";
368 sound-name-prefix = "AMX2";
373 compatible = "nvidia,tegra194-amx";
375 sound-name-prefix = "AMX3";
380 compatible = "nvidia,tegra194-amx";
382 sound-name-prefix = "AMX4";
387 compatible = "nvidia,tegra194-adx",
388 "nvidia,tegra210-adx";
390 sound-name-prefix = "ADX1";
395 compatible = "nvidia,tegra194-adx",
396 "nvidia,tegra210-adx";
398 sound-name-prefix = "ADX2";
403 compatible = "nvidia,tegra194-adx",
404 "nvidia,tegra210-adx";
406 sound-name-prefix = "ADX3";
411 compatible = "nvidia,tegra194-adx",
412 "nvidia,tegra210-adx";
414 sound-name-prefix = "ADX4";
419 compatible = "nvidia,tegra194-dmic",
420 "nvidia,tegra210-dmic";
423 clock-names = "dmic";
424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assigned-clock-rates = <3072000>;
427 sound-name-prefix = "DMIC1";
432 compatible = "nvidia,tegra194-dmic",
433 "nvidia,tegra210-dmic";
436 clock-names = "dmic";
437 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assigned-clock-rates = <3072000>;
440 sound-name-prefix = "DMIC2";
445 compatible = "nvidia,tegra194-dmic",
446 "nvidia,tegra210-dmic";
449 clock-names = "dmic";
450 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assigned-clock-rates = <3072000>;
453 sound-name-prefix = "DMIC3";
458 compatible = "nvidia,tegra194-dmic",
459 "nvidia,tegra210-dmic";
462 clock-names = "dmic";
463 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assigned-clock-rates = <3072000>;
466 sound-name-prefix = "DMIC4";
471 compatible = "nvidia,tegra194-dspk",
472 "nvidia,tegra186-dspk";
475 clock-names = "dspk";
476 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assigned-clock-rates = <12288000>;
479 sound-name-prefix = "DSPK1";
484 compatible = "nvidia,tegra194-dspk",
485 "nvidia,tegra186-dspk";
488 clock-names = "dspk";
489 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assigned-clock-rates = <12288000>;
492 sound-name-prefix = "DSPK2";
496 tegra_ope1: processing-engine@2908000 {
497 compatible = "nvidia,tegra194-ope",
498 "nvidia,tegra210-ope";
500 sound-name-prefix = "OPE1";
503 #address-cells = <2>;
504 #size-cells = <2>;
508 compatible = "nvidia,tegra194-peq",
509 "nvidia,tegra210-peq";
513 dynamic-range-compressor@2908200 {
514 compatible = "nvidia,tegra194-mbdrc",
515 "nvidia,tegra210-mbdrc";
521 compatible = "nvidia,tegra194-mvc",
522 "nvidia,tegra210-mvc";
524 sound-name-prefix = "MVC1";
529 compatible = "nvidia,tegra194-mvc",
530 "nvidia,tegra210-mvc";
532 sound-name-prefix = "MVC2";
537 compatible = "nvidia,tegra194-amixer",
538 "nvidia,tegra210-amixer";
540 sound-name-prefix = "MIXER1";
545 compatible = "nvidia,tegra194-admaif",
546 "nvidia,tegra186-admaif";
568 dma-names = "rx1", "tx1",
591 interconnect-names = "dma-mem", "write";
596 compatible = "nvidia,tegra194-asrc",
597 "nvidia,tegra186-asrc";
599 sound-name-prefix = "ASRC1";
604 adma: dma-controller@2930000 {
605 compatible = "nvidia,tegra194-adma",
606 "nvidia,tegra186-adma";
608 interrupt-parent = <&agic>;
641 #dma-cells = <1>;
643 clock-names = "d_audio";
647 agic: interrupt-controller@2a40000 {
648 compatible = "nvidia,tegra194-agic",
649 "nvidia,tegra210-agic";
650 #interrupt-cells = <3>;
651 interrupt-controller;
658 clock-names = "clk";
663 mc: memory-controller@2c00000 {
664 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
683 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
687 #interconnect-cells = <1>;
690 #address-cells = <2>;
691 #size-cells = <2>;
711 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
713 emc: external-memory-controller@2c60000 {
714 compatible = "nvidia,tegra194-emc";
719 clock-names = "emc";
721 #interconnect-cells = <0>;
728 compatible = "nvidia,tegra186-timer";
744 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
746 reg-shift = <2>;
751 dma-names = "rx", "tx";
756 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
758 reg-shift = <2>;
763 dma-names = "rx", "tx";
768 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
770 reg-shift = <2>;
775 dma-names = "rx", "tx";
780 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
782 reg-shift = <2>;
787 dma-names = "rx", "tx";
792 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
794 reg-shift = <2>;
799 dma-names = "rx", "tx";
804 compatible = "nvidia,tegra194-i2c";
807 #address-cells = <1>;
808 #size-cells = <0>;
810 clock-names = "div-clk";
812 reset-names = "i2c";
814 dma-names = "rx", "tx";
819 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
821 reg-shift = <2>;
826 dma-names = "rx", "tx";
831 compatible = "nvidia,tegra194-i2c";
834 #address-cells = <1>;
835 #size-cells = <0>;
837 clock-names = "div-clk";
839 reset-names = "i2c";
841 dma-names = "rx", "tx";
847 compatible = "nvidia,tegra194-i2c";
850 #address-cells = <1>;
851 #size-cells = <0>;
853 clock-names = "div-clk";
855 reset-names = "i2c";
856 pinctrl-0 = <&state_dpaux1_i2c>;
857 pinctrl-1 = <&state_dpaux1_off>;
858 pinctrl-names = "default", "idle";
860 dma-names = "rx", "tx";
866 compatible = "nvidia,tegra194-i2c";
869 #address-cells = <1>;
870 #size-cells = <0>;
872 clock-names = "div-clk";
874 reset-names = "i2c";
875 pinctrl-0 = <&state_dpaux0_i2c>;
876 pinctrl-1 = <&state_dpaux0_off>;
877 pinctrl-names = "default", "idle";
879 dma-names = "rx", "tx";
885 compatible = "nvidia,tegra194-i2c";
888 #address-cells = <1>;
889 #size-cells = <0>;
891 clock-names = "div-clk";
893 reset-names = "i2c";
894 pinctrl-0 = <&state_dpaux2_i2c>;
895 pinctrl-1 = <&state_dpaux2_off>;
896 pinctrl-names = "default", "idle";
898 dma-names = "rx", "tx";
904 compatible = "nvidia,tegra194-i2c";
907 #address-cells = <1>;
908 #size-cells = <0>;
910 clock-names = "div-clk";
912 reset-names = "i2c";
913 pinctrl-0 = <&state_dpaux3_i2c>;
914 pinctrl-1 = <&state_dpaux3_off>;
915 pinctrl-names = "default", "idle";
917 dma-names = "rx", "tx";
922 compatible = "nvidia,tegra194-qspi";
925 #address-cells = <1>;
926 #size-cells = <0>;
929 clock-names = "qspi", "qspi_out";
935 compatible = "nvidia,tegra194-pwm",
936 "nvidia,tegra186-pwm";
940 reset-names = "pwm";
942 #pwm-cells = <2>;
946 compatible = "nvidia,tegra194-pwm",
947 "nvidia,tegra186-pwm";
951 reset-names = "pwm";
953 #pwm-cells = <2>;
957 compatible = "nvidia,tegra194-pwm",
958 "nvidia,tegra186-pwm";
962 reset-names = "pwm";
964 #pwm-cells = <2>;
968 compatible = "nvidia,tegra194-pwm",
969 "nvidia,tegra186-pwm";
973 reset-names = "pwm";
975 #pwm-cells = <2>;
979 compatible = "nvidia,tegra194-pwm",
980 "nvidia,tegra186-pwm";
984 reset-names = "pwm";
986 #pwm-cells = <2>;
990 compatible = "nvidia,tegra194-pwm",
991 "nvidia,tegra186-pwm";
995 reset-names = "pwm";
997 #pwm-cells = <2>;
1001 compatible = "nvidia,tegra194-pwm",
1002 "nvidia,tegra186-pwm";
1006 reset-names = "pwm";
1008 #pwm-cells = <2>;
1012 compatible = "nvidia,tegra194-qspi";
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1019 clock-names = "qspi", "qspi_out";
1025 compatible = "nvidia,tegra194-sdhci";
1030 clock-names = "sdhci", "tmclk";
1031 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1033 assigned-clock-parents =
1037 reset-names = "sdhci";
1040 interconnect-names = "dma-mem", "write";
1042 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1043 pinctrl-0 = <&sdmmc1_3v3>;
1044 pinctrl-1 = <&sdmmc1_1v8>;
1045 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1047 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1049 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1050 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1052 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1053 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1054 nvidia,default-tap = <0x9>;
1055 nvidia,default-trim = <0x5>;
1056 sd-uhs-sdr25;
1057 sd-uhs-sdr50;
1058 sd-uhs-ddr50;
1059 sd-uhs-sdr104;
1064 compatible = "nvidia,tegra194-sdhci";
1069 clock-names = "sdhci", "tmclk";
1070 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1072 assigned-clock-parents =
1076 reset-names = "sdhci";
1079 interconnect-names = "dma-mem", "write";
1081 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1082 pinctrl-0 = <&sdmmc3_3v3>;
1083 pinctrl-1 = <&sdmmc3_1v8>;
1084 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1085 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1086 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1087 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1089 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1090 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1092 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1093 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1094 nvidia,default-tap = <0x9>;
1095 nvidia,default-trim = <0x5>;
1096 sd-uhs-sdr25;
1097 sd-uhs-sdr50;
1098 sd-uhs-ddr50;
1099 sd-uhs-sdr104;
1104 compatible = "nvidia,tegra194-sdhci";
1109 clock-names = "sdhci", "tmclk";
1110 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1112 assigned-clock-parents =
1115 reset-names = "sdhci";
1118 interconnect-names = "dma-mem", "write";
1120 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1121 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1122 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1123 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1125 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1126 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1128 nvidia,default-tap = <0x8>;
1129 nvidia,default-trim = <0x14>;
1130 nvidia,dqs-trim = <40>;
1131 cap-mmc-highspeed;
1132 mmc-ddr-1_8v;
1133 mmc-hs200-1_8v;
1134 mmc-hs400-1_8v;
1135 mmc-hs400-enhanced-strobe;
1136 supports-cqe;
1141 compatible = "nvidia,tegra194-hda";
1147 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1150 reset-names = "hda", "hda2hdmi";
1151 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1154 interconnect-names = "dma-mem", "write";
1160 compatible = "nvidia,tegra194-xusb-padctl";
1163 reg-names = "padctl", "ao";
1167 reset-names = "padctl";
1174 clock-names = "trk";
1177 usb2-0 {
1180 #phy-cells = <0>;
1183 usb2-1 {
1186 #phy-cells = <0>;
1189 usb2-2 {
1192 #phy-cells = <0>;
1195 usb2-3 {
1198 #phy-cells = <0>;
1205 usb3-0 {
1208 #phy-cells = <0>;
1211 usb3-1 {
1214 #phy-cells = <0>;
1217 usb3-2 {
1220 #phy-cells = <0>;
1223 usb3-3 {
1226 #phy-cells = <0>;
1233 usb2-0 {
1237 usb2-1 {
1241 usb2-2 {
1245 usb2-3 {
1249 usb3-0 {
1253 usb3-1 {
1257 usb3-2 {
1261 usb3-3 {
1268 compatible = "nvidia,tegra194-xudc";
1271 reg-names = "base", "fpci";
1277 clock-names = "dev", "ss", "ss_src", "fs_src";
1280 interconnect-names = "dma-mem", "write";
1282 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1284 power-domain-names = "dev", "ss";
1285 nvidia,xusb-padctl = <&xusb_padctl>;
1286 dma-coherent;
1291 compatible = "nvidia,tegra194-xusb";
1294 reg-names = "hcd", "fpci";
1308 clock-names = "xusb_host", "xusb_falcon_src",
1314 interconnect-names = "dma-mem", "write";
1317 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1319 power-domain-names = "xusb_host", "xusb_ss";
1321 nvidia,xusb-padctl = <&xusb_padctl>;
1326 compatible = "nvidia,tegra194-efuse";
1329 clock-names = "fuse";
1332 gic: interrupt-controller@3881000 {
1333 compatible = "arm,gic-400";
1334 #interrupt-cells = <3>;
1335 interrupt-controller;
1342 interrupt-parent = <&gic>;
1346 compatible = "nvidia,tegra194-cec", "nvidia,tegra210-cec";
1350 clock-names = "cec";
1354 hte_lic: hardware-timestamp@3aa0000 {
1355 compatible = "nvidia,tegra194-gte-lic";
1358 nvidia,int-threshold = <1>;
1360 #timestamp-cells = <1>;
1365 compatible = "nvidia,tegra194-hsp";
1376 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1379 #mbox-cells = <2>;
1383 compatible = "nvidia,tegra194-p2u";
1385 reg-names = "ctl";
1387 #phy-cells = <0>;
1391 compatible = "nvidia,tegra194-p2u";
1393 reg-names = "ctl";
1395 #phy-cells = <0>;
1399 compatible = "nvidia,tegra194-p2u";
1401 reg-names = "ctl";
1403 #phy-cells = <0>;
1407 compatible = "nvidia,tegra194-p2u";
1409 reg-names = "ctl";
1411 #phy-cells = <0>;
1415 compatible = "nvidia,tegra194-p2u";
1417 reg-names = "ctl";
1419 #phy-cells = <0>;
1423 compatible = "nvidia,tegra194-p2u";
1425 reg-names = "ctl";
1427 #phy-cells = <0>;
1431 compatible = "nvidia,tegra194-p2u";
1433 reg-names = "ctl";
1435 #phy-cells = <0>;
1439 compatible = "nvidia,tegra194-p2u";
1441 reg-names = "ctl";
1443 #phy-cells = <0>;
1447 compatible = "nvidia,tegra194-p2u";
1449 reg-names = "ctl";
1451 #phy-cells = <0>;
1455 compatible = "nvidia,tegra194-p2u";
1457 reg-names = "ctl";
1459 #phy-cells = <0>;
1463 compatible = "nvidia,tegra194-p2u";
1465 reg-names = "ctl";
1467 #phy-cells = <0>;
1471 compatible = "nvidia,tegra194-p2u";
1473 reg-names = "ctl";
1475 #phy-cells = <0>;
1479 compatible = "nvidia,tegra194-p2u";
1481 reg-names = "ctl";
1483 #phy-cells = <0>;
1487 compatible = "nvidia,tegra194-p2u";
1489 reg-names = "ctl";
1491 #phy-cells = <0>;
1495 compatible = "nvidia,tegra194-p2u";
1497 reg-names = "ctl";
1499 #phy-cells = <0>;
1503 compatible = "nvidia,tegra194-p2u";
1505 reg-names = "ctl";
1507 #phy-cells = <0>;
1511 compatible = "nvidia,tegra194-p2u";
1513 reg-names = "ctl";
1515 #phy-cells = <0>;
1519 compatible = "nvidia,tegra194-p2u";
1521 reg-names = "ctl";
1523 #phy-cells = <0>;
1527 compatible = "nvidia,tegra194-p2u";
1529 reg-names = "ctl";
1531 #phy-cells = <0>;
1535 compatible = "nvidia,tegra194-p2u";
1537 reg-names = "ctl";
1539 #phy-cells = <0>;
1542 sce-noc@b600000 {
1543 compatible = "nvidia,tegra194-sce-noc";
1552 rce-noc@be00000 {
1553 compatible = "nvidia,tegra194-rce-noc";
1563 compatible = "nvidia,tegra194-hsp";
1573 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1574 #mbox-cells = <2>;
1577 hte_aon: hardware-timestamp@c1e0000 {
1578 compatible = "nvidia,tegra194-gte-aon";
1581 nvidia,int-threshold = <1>;
1583 #timestamp-cells = <1>;
1588 compatible = "nvidia,tegra194-i2c";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1594 clock-names = "div-clk";
1596 reset-names = "i2c";
1598 dma-names = "rx", "tx";
1603 compatible = "nvidia,tegra194-i2c";
1606 #address-cells = <1>;
1607 #size-cells = <0>;
1609 clock-names = "div-clk";
1611 reset-names = "i2c";
1613 dma-names = "rx", "tx";
1618 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1620 reg-shift = <2>;
1625 dma-names = "rx", "tx";
1630 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1632 reg-shift = <2>;
1637 dma-names = "rx", "tx";
1642 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1644 interrupt-parent = <&pmc>;
1647 clock-names = "rtc";
1652 compatible = "nvidia,tegra194-gpio-aon";
1653 reg-names = "security", "gpio";
1660 gpio-controller;
1661 #gpio-cells = <2>;
1662 interrupt-controller;
1663 #interrupt-cells = <2>;
1664 gpio-ranges = <&pinmux_aon 0 0 30>;
1668 compatible = "nvidia,tegra194-pinmux-aon";
1675 compatible = "nvidia,tegra194-pwm",
1676 "nvidia,tegra186-pwm";
1680 reset-names = "pwm";
1682 #pwm-cells = <2>;
1686 compatible = "nvidia,tegra194-pmc";
1692 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1694 #interrupt-cells = <2>;
1695 interrupt-controller;
1697 sdmmc1_1v8: sdmmc1-1v8 {
1698 pins = "sdmmc1-hv";
1699 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1702 sdmmc1_3v3: sdmmc1-3v3 {
1703 pins = "sdmmc1-hv";
1704 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1707 sdmmc3_1v8: sdmmc3-1v8 {
1708 pins = "sdmmc3-hv";
1709 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1712 sdmmc3_3v3: sdmmc3-3v3 {
1713 pins = "sdmmc3-hv";
1714 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1718 aon-noc@c600000 {
1719 compatible = "nvidia,tegra194-aon-noc";
1727 bpmp-noc@d600000 {
1728 compatible = "nvidia,tegra194-bpmp-noc";
1738 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1805 stream-match-mask = <0x7f80>;
1806 #global-interrupts = <1>;
1807 #iommu-cells = <1>;
1809 nvidia,memory-controller = <&mc>;
1814 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1883 stream-match-mask = <0x7f80>;
1884 #global-interrupts = <2>;
1885 #iommu-cells = <1>;
1887 nvidia,memory-controller = <&mc>;
1892 compatible = "nvidia,tegra194-host1x";
1895 reg-names = "hypervisor", "vm";
1898 interrupt-names = "syncpt", "host1x";
1900 clock-names = "host1x";
1902 reset-names = "host1x";
1904 #address-cells = <2>;
1905 #size-cells = <2>;
1909 interconnect-names = "dma-mem";
1911 dma-coherent;
1914 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1924 compatible = "nvidia,tegra194-nvdec";
1927 clock-names = "nvdec";
1929 reset-names = "nvdec";
1931 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1935 interconnect-names = "dma-mem", "read-1", "write";
1937 dma-coherent;
1939 nvidia,host1x-class = <0xf5>;
1942 display-hub@15200000 {
1943 compatible = "nvidia,tegra194-display";
1952 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1956 clock-names = "disp", "hub";
1959 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1961 #address-cells = <2>;
1962 #size-cells = <2>;
1966 compatible = "nvidia,tegra194-dc";
1970 clock-names = "dc";
1972 reset-names = "dc";
1974 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1977 interconnect-names = "dma-mem", "read-1";
1984 compatible = "nvidia,tegra194-dc";
1988 clock-names = "dc";
1990 reset-names = "dc";
1992 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1995 interconnect-names = "dma-mem", "read-1";
2002 compatible = "nvidia,tegra194-dc";
2006 clock-names = "dc";
2008 reset-names = "dc";
2010 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2013 interconnect-names = "dma-mem", "read-1";
2020 compatible = "nvidia,tegra194-dc";
2024 clock-names = "dc";
2026 reset-names = "dc";
2028 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2031 interconnect-names = "dma-mem", "read-1";
2039 compatible = "nvidia,tegra194-vic";
2043 clock-names = "vic";
2045 reset-names = "vic";
2047 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2050 interconnect-names = "dma-mem", "write";
2052 dma-coherent;
2056 compatible = "nvidia,tegra194-nvjpg";
2059 clock-names = "nvjpg";
2061 reset-names = "nvjpg";
2063 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2066 interconnect-names = "dma-mem", "write";
2068 dma-coherent;
2072 compatible = "nvidia,tegra194-nvdec";
2075 clock-names = "nvdec";
2077 reset-names = "nvdec";
2079 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2083 interconnect-names = "dma-mem", "read-1", "write";
2085 dma-coherent;
2087 nvidia,host1x-class = <0xf0>;
2091 compatible = "nvidia,tegra194-nvenc";
2094 clock-names = "nvenc";
2096 reset-names = "nvenc";
2098 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2102 interconnect-names = "dma-mem", "read-1", "write";
2104 dma-coherent;
2106 nvidia,host1x-class = <0x21>;
2110 compatible = "nvidia,tegra194-dpaux";
2115 clock-names = "dpaux", "parent";
2117 reset-names = "dpaux";
2120 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2122 state_dpaux0_aux: pinmux-aux {
2123 groups = "dpaux-io";
2127 state_dpaux0_i2c: pinmux-i2c {
2128 groups = "dpaux-io";
2132 state_dpaux0_off: pinmux-off {
2133 groups = "dpaux-io";
2137 i2c-bus {
2138 #address-cells = <1>;
2139 #size-cells = <0>;
2144 compatible = "nvidia,tegra194-dpaux";
2149 clock-names = "dpaux", "parent";
2151 reset-names = "dpaux";
2154 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2156 state_dpaux1_aux: pinmux-aux {
2157 groups = "dpaux-io";
2161 state_dpaux1_i2c: pinmux-i2c {
2162 groups = "dpaux-io";
2166 state_dpaux1_off: pinmux-off {
2167 groups = "dpaux-io";
2171 i2c-bus {
2172 #address-cells = <1>;
2173 #size-cells = <0>;
2178 compatible = "nvidia,tegra194-dpaux";
2183 clock-names = "dpaux", "parent";
2185 reset-names = "dpaux";
2188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2190 state_dpaux2_aux: pinmux-aux {
2191 groups = "dpaux-io";
2195 state_dpaux2_i2c: pinmux-i2c {
2196 groups = "dpaux-io";
2200 state_dpaux2_off: pinmux-off {
2201 groups = "dpaux-io";
2205 i2c-bus {
2206 #address-cells = <1>;
2207 #size-cells = <0>;
2212 compatible = "nvidia,tegra194-dpaux";
2217 clock-names = "dpaux", "parent";
2219 reset-names = "dpaux";
2222 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2224 state_dpaux3_aux: pinmux-aux {
2225 groups = "dpaux-io";
2229 state_dpaux3_i2c: pinmux-i2c {
2230 groups = "dpaux-io";
2234 state_dpaux3_off: pinmux-off {
2235 groups = "dpaux-io";
2239 i2c-bus {
2240 #address-cells = <1>;
2241 #size-cells = <0>;
2246 compatible = "nvidia,tegra194-nvenc";
2249 clock-names = "nvenc";
2251 reset-names = "nvenc";
2253 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2257 interconnect-names = "dma-mem", "read-1", "write";
2259 dma-coherent;
2261 nvidia,host1x-class = <0x22>;
2265 compatible = "nvidia,tegra194-sor";
2274 clock-names = "sor", "out", "parent", "dp", "safe",
2277 reset-names = "sor";
2278 pinctrl-0 = <&state_dpaux0_aux>;
2279 pinctrl-1 = <&state_dpaux0_i2c>;
2280 pinctrl-2 = <&state_dpaux0_off>;
2281 pinctrl-names = "aux", "i2c", "off";
2284 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2289 compatible = "nvidia,tegra194-sor";
2298 clock-names = "sor", "out", "parent", "dp", "safe",
2301 reset-names = "sor";
2302 pinctrl-0 = <&state_dpaux1_aux>;
2303 pinctrl-1 = <&state_dpaux1_i2c>;
2304 pinctrl-2 = <&state_dpaux1_off>;
2305 pinctrl-names = "aux", "i2c", "off";
2308 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2313 compatible = "nvidia,tegra194-sor";
2322 clock-names = "sor", "out", "parent", "dp", "safe",
2325 reset-names = "sor";
2326 pinctrl-0 = <&state_dpaux2_aux>;
2327 pinctrl-1 = <&state_dpaux2_i2c>;
2328 pinctrl-2 = <&state_dpaux2_off>;
2329 pinctrl-names = "aux", "i2c", "off";
2332 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2337 compatible = "nvidia,tegra194-sor";
2346 clock-names = "sor", "out", "parent", "dp", "safe",
2349 reset-names = "sor";
2350 pinctrl-0 = <&state_dpaux3_aux>;
2351 pinctrl-1 = <&state_dpaux3_i2c>;
2352 pinctrl-2 = <&state_dpaux3_off>;
2353 pinctrl-names = "aux", "i2c", "off";
2356 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2362 compatible = "nvidia,tegra194-pcie";
2363 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2368 reg-names = "appl", "config", "atu_dma", "dbi";
2372 #address-cells = <3>;
2373 #size-cells = <2>;
2375 num-lanes = <1>;
2376 linux,pci-domain = <1>;
2379 clock-names = "core";
2383 reset-names = "apb", "core";
2387 interrupt-names = "intr", "msi";
2389 #interrupt-cells = <1>;
2390 interrupt-map-mask = <0 0 0 0>;
2391 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2395 nvidia,aspm-cmrt-us = <60>;
2396 nvidia,aspm-pwr-on-t-us = <20>;
2397 nvidia,aspm-l0s-entrance-latency-us = <3>;
2399 bus-range = <0x0 0xff>;
2402 …00000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2407 interconnect-names = "dma-mem", "write";
2408 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2409 iommu-map-mask = <0x0>;
2410 dma-coherent;
2414 compatible = "nvidia,tegra194-pcie";
2415 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2420 reg-names = "appl", "config", "atu_dma", "dbi";
2424 #address-cells = <3>;
2425 #size-cells = <2>;
2427 num-lanes = <1>;
2428 linux,pci-domain = <2>;
2431 clock-names = "core";
2435 reset-names = "apb", "core";
2439 interrupt-names = "intr", "msi";
2441 #interrupt-cells = <1>;
2442 interrupt-map-mask = <0 0 0 0>;
2443 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2447 nvidia,aspm-cmrt-us = <60>;
2448 nvidia,aspm-pwr-on-t-us = <20>;
2449 nvidia,aspm-l0s-entrance-latency-us = <3>;
2451 bus-range = <0x0 0xff>;
2454 …00000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2459 interconnect-names = "dma-mem", "write";
2460 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2461 iommu-map-mask = <0x0>;
2462 dma-coherent;
2466 compatible = "nvidia,tegra194-pcie";
2467 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2472 reg-names = "appl", "config", "atu_dma", "dbi";
2476 #address-cells = <3>;
2477 #size-cells = <2>;
2479 num-lanes = <1>;
2480 linux,pci-domain = <3>;
2483 clock-names = "core";
2487 reset-names = "apb", "core";
2491 interrupt-names = "intr", "msi";
2493 #interrupt-cells = <1>;
2494 interrupt-map-mask = <0 0 0 0>;
2495 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2499 nvidia,aspm-cmrt-us = <60>;
2500 nvidia,aspm-pwr-on-t-us = <20>;
2501 nvidia,aspm-l0s-entrance-latency-us = <3>;
2503 bus-range = <0x0 0xff>;
2506 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
2511 interconnect-names = "dma-mem", "write";
2512 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2513 iommu-map-mask = <0x0>;
2514 dma-coherent;
2518 compatible = "nvidia,tegra194-pcie";
2519 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2524 reg-names = "appl", "config", "atu_dma", "dbi";
2528 #address-cells = <3>;
2529 #size-cells = <2>;
2531 num-lanes = <4>;
2532 linux,pci-domain = <4>;
2535 clock-names = "core";
2539 reset-names = "apb", "core";
2543 interrupt-names = "intr", "msi";
2545 #interrupt-cells = <1>;
2546 interrupt-map-mask = <0 0 0 0>;
2547 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2551 nvidia,aspm-cmrt-us = <60>;
2552 nvidia,aspm-pwr-on-t-us = <20>;
2553 nvidia,aspm-l0s-entrance-latency-us = <3>;
2555 bus-range = <0x0 0xff>;
2558 …000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2563 interconnect-names = "dma-mem", "write";
2564 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2565 iommu-map-mask = <0x0>;
2566 dma-coherent;
2569 pcie-ep@14160000 {
2570 compatible = "nvidia,tegra194-pcie-ep";
2571 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2576 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2580 num-lanes = <4>;
2581 num-ib-windows = <2>;
2582 num-ob-windows = <8>;
2585 clock-names = "core";
2589 reset-names = "apb", "core";
2592 interrupt-names = "intr";
2596 nvidia,aspm-cmrt-us = <60>;
2597 nvidia,aspm-pwr-on-t-us = <20>;
2598 nvidia,aspm-l0s-entrance-latency-us = <3>;
2602 interconnect-names = "dma-mem", "write";
2603 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2604 iommu-map-mask = <0x0>;
2605 dma-coherent;
2609 compatible = "nvidia,tegra194-pcie";
2610 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2615 reg-names = "appl", "config", "atu_dma", "dbi";
2619 #address-cells = <3>;
2620 #size-cells = <2>;
2622 num-lanes = <8>;
2623 linux,pci-domain = <0>;
2626 clock-names = "core";
2630 reset-names = "apb", "core";
2634 interrupt-names = "intr", "msi";
2636 #interrupt-cells = <1>;
2637 interrupt-map-mask = <0 0 0 0>;
2638 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2642 nvidia,aspm-cmrt-us = <60>;
2643 nvidia,aspm-pwr-on-t-us = <20>;
2644 nvidia,aspm-l0s-entrance-latency-us = <3>;
2646 bus-range = <0x0 0xff>;
2649 …000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2654 interconnect-names = "dma-mem", "write";
2655 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2656 iommu-map-mask = <0x0>;
2657 dma-coherent;
2660 pcie-ep@14180000 {
2661 compatible = "nvidia,tegra194-pcie-ep";
2662 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2667 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2671 num-lanes = <8>;
2672 num-ib-windows = <2>;
2673 num-ob-windows = <8>;
2676 clock-names = "core";
2680 reset-names = "apb", "core";
2683 interrupt-names = "intr";
2687 nvidia,aspm-cmrt-us = <60>;
2688 nvidia,aspm-pwr-on-t-us = <20>;
2689 nvidia,aspm-l0s-entrance-latency-us = <3>;
2693 interconnect-names = "dma-mem", "write";
2694 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2695 iommu-map-mask = <0x0>;
2696 dma-coherent;
2700 compatible = "nvidia,tegra194-pcie";
2701 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2706 reg-names = "appl", "config", "atu_dma", "dbi";
2710 #address-cells = <3>;
2711 #size-cells = <2>;
2713 num-lanes = <8>;
2714 linux,pci-domain = <5>;
2716 pinctrl-names = "default";
2717 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>;
2720 clock-names = "core";
2724 reset-names = "apb", "core";
2728 interrupt-names = "intr", "msi";
2732 #interrupt-cells = <1>;
2733 interrupt-map-mask = <0 0 0 0>;
2734 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2736 nvidia,aspm-cmrt-us = <60>;
2737 nvidia,aspm-pwr-on-t-us = <20>;
2738 nvidia,aspm-l0s-entrance-latency-us = <3>;
2740 bus-range = <0x0 0xff>;
2743 …000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2748 interconnect-names = "dma-mem", "write";
2749 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2750 iommu-map-mask = <0x0>;
2751 dma-coherent;
2754 pcie-ep@141a0000 {
2755 compatible = "nvidia,tegra194-pcie-ep";
2756 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2761 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2765 num-lanes = <8>;
2766 num-ib-windows = <2>;
2767 num-ob-windows = <8>;
2769 pinctrl-names = "default";
2770 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>;
2773 clock-names = "core";
2777 reset-names = "apb", "core";
2780 interrupt-names = "intr";
2784 nvidia,aspm-cmrt-us = <60>;
2785 nvidia,aspm-pwr-on-t-us = <20>;
2786 nvidia,aspm-l0s-entrance-latency-us = <3>;
2790 interconnect-names = "dma-mem", "write";
2791 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2792 iommu-map-mask = <0x0>;
2793 dma-coherent;
2802 interrupt-names = "stall", "nonstall";
2806 clock-names = "gpu", "pwr", "fuse";
2808 reset-names = "gpu";
2809 dma-coherent;
2811 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2824 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2825 "read-1", "read-1-hp", "write-1",
2826 "read-2", "read-2-hp", "write-2",
2827 "read-3", "read-3-hp", "write-3";
2832 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2835 #address-cells = <1>;
2836 #size-cells = <1>;
2839 no-memory-wc;
2843 label = "cpu-bpmp-tx";
2849 label = "cpu-bpmp-rx";
2855 compatible = "nvidia,tegra186-bpmp";
2859 #clock-cells = <1>;
2860 #reset-cells = <1>;
2861 #power-domain-cells = <1>;
2866 interconnect-names = "read", "write", "dma-mem", "dma-write";
2870 compatible = "nvidia,tegra186-bpmp-i2c";
2871 nvidia,bpmp-bus-id = <5>;
2872 #address-cells = <1>;
2873 #size-cells = <0>;
2877 compatible = "nvidia,tegra186-bpmp-thermal";
2878 #thermal-sensor-cells = <1>;
2883 compatible = "nvidia,tegra194-ccplex";
2885 #address-cells = <1>;
2886 #size-cells = <0>;
2889 compatible = "nvidia,tegra194-carmel";
2892 enable-method = "psci";
2893 i-cache-size = <131072>;
2894 i-cache-line-size = <64>;
2895 i-cache-sets = <512>;
2896 d-cache-size = <65536>;
2897 d-cache-line-size = <64>;
2898 d-cache-sets = <256>;
2899 next-level-cache = <&l2c_0>;
2903 compatible = "nvidia,tegra194-carmel";
2906 enable-method = "psci";
2907 i-cache-size = <131072>;
2908 i-cache-line-size = <64>;
2909 i-cache-sets = <512>;
2910 d-cache-size = <65536>;
2911 d-cache-line-size = <64>;
2912 d-cache-sets = <256>;
2913 next-level-cache = <&l2c_0>;
2917 compatible = "nvidia,tegra194-carmel";
2920 enable-method = "psci";
2921 i-cache-size = <131072>;
2922 i-cache-line-size = <64>;
2923 i-cache-sets = <512>;
2924 d-cache-size = <65536>;
2925 d-cache-line-size = <64>;
2926 d-cache-sets = <256>;
2927 next-level-cache = <&l2c_1>;
2931 compatible = "nvidia,tegra194-carmel";
2934 enable-method = "psci";
2935 i-cache-size = <131072>;
2936 i-cache-line-size = <64>;
2937 i-cache-sets = <512>;
2938 d-cache-size = <65536>;
2939 d-cache-line-size = <64>;
2940 d-cache-sets = <256>;
2941 next-level-cache = <&l2c_1>;
2945 compatible = "nvidia,tegra194-carmel";
2948 enable-method = "psci";
2949 i-cache-size = <131072>;
2950 i-cache-line-size = <64>;
2951 i-cache-sets = <512>;
2952 d-cache-size = <65536>;
2953 d-cache-line-size = <64>;
2954 d-cache-sets = <256>;
2955 next-level-cache = <&l2c_2>;
2959 compatible = "nvidia,tegra194-carmel";
2962 enable-method = "psci";
2963 i-cache-size = <131072>;
2964 i-cache-line-size = <64>;
2965 i-cache-sets = <512>;
2966 d-cache-size = <65536>;
2967 d-cache-line-size = <64>;
2968 d-cache-sets = <256>;
2969 next-level-cache = <&l2c_2>;
2973 compatible = "nvidia,tegra194-carmel";
2976 enable-method = "psci";
2977 i-cache-size = <131072>;
2978 i-cache-line-size = <64>;
2979 i-cache-sets = <512>;
2980 d-cache-size = <65536>;
2981 d-cache-line-size = <64>;
2982 d-cache-sets = <256>;
2983 next-level-cache = <&l2c_3>;
2987 compatible = "nvidia,tegra194-carmel";
2990 enable-method = "psci";
2991 i-cache-size = <131072>;
2992 i-cache-line-size = <64>;
2993 i-cache-sets = <512>;
2994 d-cache-size = <65536>;
2995 d-cache-line-size = <64>;
2996 d-cache-sets = <256>;
2997 next-level-cache = <&l2c_3>;
3000 cpu-map {
3042 l2c_0: l2-cache0 {
3044 cache-unified;
3045 cache-size = <2097152>;
3046 cache-line-size = <64>;
3047 cache-sets = <2048>;
3048 cache-level = <2>;
3049 next-level-cache = <&l3c>;
3052 l2c_1: l2-cache1 {
3054 cache-unified;
3055 cache-size = <2097152>;
3056 cache-line-size = <64>;
3057 cache-sets = <2048>;
3058 cache-level = <2>;
3059 next-level-cache = <&l3c>;
3062 l2c_2: l2-cache2 {
3064 cache-unified;
3065 cache-size = <2097152>;
3066 cache-line-size = <64>;
3067 cache-sets = <2048>;
3068 cache-level = <2>;
3069 next-level-cache = <&l3c>;
3072 l2c_3: l2-cache3 {
3074 cache-unified;
3075 cache-size = <2097152>;
3076 cache-line-size = <64>;
3077 cache-sets = <2048>;
3078 cache-level = <2>;
3079 next-level-cache = <&l3c>;
3082 l3c: l3-cache {
3084 cache-unified;
3085 cache-size = <4194304>;
3086 cache-line-size = <64>;
3087 cache-level = <3>;
3088 cache-sets = <4096>;
3093 compatible = "nvidia,carmel-pmu";
3102 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3107 compatible = "arm,psci-1.0";
3113 compatible = "nvidia,tegra194-tcu";
3116 mbox-names = "rx", "tx";
3124 clock-names = "pll_a", "plla_out0";
3125 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3128 assigned-clock-parents = <0>,
3136 assigned-clock-rates = <258000000>;
3139 thermal-zones {
3140 cpu-thermal {
3141 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3145 gpu-thermal {
3146 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3150 aux-thermal {
3151 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3155 pllx-thermal {
3156 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3160 ao-thermal {
3161 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3165 tj-thermal {
3166 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3172 compatible = "arm,armv8-timer";
3181 interrupt-parent = <&gic>;
3182 always-on;