Lines Matching +full:tegra20 +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "nvidia,tegra186-misc";
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
62 reset-names = "eqos";
65 interconnect-names = "dma-mem", "write";
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
76 gpcdma: dma-controller@2600000 {
77 compatible = "nvidia,tegra186-gpcdma";
80 reset-names = "gpcdma";
113 #dma-cells = <1>;
115 dma-coherent;
116 dma-channel-mask = <0xfffffffe>;
121 compatible = "nvidia,tegra186-aconnect",
122 "nvidia,tegra210-aconnect";
125 clock-names = "ape", "apb2ape";
126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
127 #address-cells = <2>;
128 #size-cells = <2>;
133 compatible = "nvidia,tegra186-ahub";
136 clock-names = "ahub";
137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
139 assigned-clock-rates = <81600000>;
140 #address-cells = <2>;
141 #size-cells = <2>;
145 tegra_i2s1: i2s@2901000 {
146 compatible = "nvidia,tegra186-i2s",
147 "nvidia,tegra210-i2s";
151 clock-names = "i2s", "sync_input";
152 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
154 assigned-clock-rates = <1536000>;
155 sound-name-prefix = "I2S1";
159 tegra_i2s2: i2s@2901100 {
160 compatible = "nvidia,tegra186-i2s",
161 "nvidia,tegra210-i2s";
165 clock-names = "i2s", "sync_input";
166 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
168 assigned-clock-rates = <1536000>;
169 sound-name-prefix = "I2S2";
173 tegra_i2s3: i2s@2901200 {
174 compatible = "nvidia,tegra186-i2s",
175 "nvidia,tegra210-i2s";
179 clock-names = "i2s", "sync_input";
180 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
182 assigned-clock-rates = <1536000>;
183 sound-name-prefix = "I2S3";
187 tegra_i2s4: i2s@2901300 {
188 compatible = "nvidia,tegra186-i2s",
189 "nvidia,tegra210-i2s";
193 clock-names = "i2s", "sync_input";
194 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
196 assigned-clock-rates = <1536000>;
197 sound-name-prefix = "I2S4";
201 tegra_i2s5: i2s@2901400 {
202 compatible = "nvidia,tegra186-i2s",
203 "nvidia,tegra210-i2s";
207 clock-names = "i2s", "sync_input";
208 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
210 assigned-clock-rates = <1536000>;
211 sound-name-prefix = "I2S5";
215 tegra_i2s6: i2s@2901500 {
216 compatible = "nvidia,tegra186-i2s",
217 "nvidia,tegra210-i2s";
221 clock-names = "i2s", "sync_input";
222 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
224 assigned-clock-rates = <1536000>;
225 sound-name-prefix = "I2S6";
230 compatible = "nvidia,tegra186-sfc",
231 "nvidia,tegra210-sfc";
233 sound-name-prefix = "SFC1";
238 compatible = "nvidia,tegra186-sfc",
239 "nvidia,tegra210-sfc";
241 sound-name-prefix = "SFC2";
246 compatible = "nvidia,tegra186-sfc",
247 "nvidia,tegra210-sfc";
249 sound-name-prefix = "SFC3";
254 compatible = "nvidia,tegra186-sfc",
255 "nvidia,tegra210-sfc";
257 sound-name-prefix = "SFC4";
262 compatible = "nvidia,tegra186-amx",
263 "nvidia,tegra210-amx";
265 sound-name-prefix = "AMX1";
270 compatible = "nvidia,tegra186-amx",
271 "nvidia,tegra210-amx";
273 sound-name-prefix = "AMX2";
278 compatible = "nvidia,tegra186-amx",
279 "nvidia,tegra210-amx";
281 sound-name-prefix = "AMX3";
286 compatible = "nvidia,tegra186-amx",
287 "nvidia,tegra210-amx";
289 sound-name-prefix = "AMX4";
294 compatible = "nvidia,tegra186-adx",
295 "nvidia,tegra210-adx";
297 sound-name-prefix = "ADX1";
302 compatible = "nvidia,tegra186-adx",
303 "nvidia,tegra210-adx";
305 sound-name-prefix = "ADX2";
310 compatible = "nvidia,tegra186-adx",
311 "nvidia,tegra210-adx";
313 sound-name-prefix = "ADX3";
318 compatible = "nvidia,tegra186-adx",
319 "nvidia,tegra210-adx";
321 sound-name-prefix = "ADX4";
326 compatible = "nvidia,tegra210-dmic";
329 clock-names = "dmic";
330 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
332 assigned-clock-rates = <3072000>;
333 sound-name-prefix = "DMIC1";
338 compatible = "nvidia,tegra210-dmic";
341 clock-names = "dmic";
342 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
344 assigned-clock-rates = <3072000>;
345 sound-name-prefix = "DMIC2";
350 compatible = "nvidia,tegra210-dmic";
353 clock-names = "dmic";
354 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
356 assigned-clock-rates = <3072000>;
357 sound-name-prefix = "DMIC3";
362 compatible = "nvidia,tegra210-dmic";
365 clock-names = "dmic";
366 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
368 assigned-clock-rates = <3072000>;
369 sound-name-prefix = "DMIC4";
374 compatible = "nvidia,tegra186-dspk";
377 clock-names = "dspk";
378 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
379 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
380 assigned-clock-rates = <12288000>;
381 sound-name-prefix = "DSPK1";
386 compatible = "nvidia,tegra186-dspk";
389 clock-names = "dspk";
390 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
391 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
392 assigned-clock-rates = <12288000>;
393 sound-name-prefix = "DSPK2";
397 tegra_ope1: processing-engine@2908000 {
398 compatible = "nvidia,tegra186-ope",
399 "nvidia,tegra210-ope";
401 #address-cells = <2>;
402 #size-cells = <2>;
404 sound-name-prefix = "OPE1";
408 compatible = "nvidia,tegra186-peq",
409 "nvidia,tegra210-peq";
413 dynamic-range-compressor@2908200 {
414 compatible = "nvidia,tegra186-mbdrc",
415 "nvidia,tegra210-mbdrc";
421 compatible = "nvidia,tegra186-mvc",
422 "nvidia,tegra210-mvc";
424 sound-name-prefix = "MVC1";
429 compatible = "nvidia,tegra186-mvc",
430 "nvidia,tegra210-mvc";
432 sound-name-prefix = "MVC2";
437 compatible = "nvidia,tegra186-amixer",
438 "nvidia,tegra210-amixer";
440 sound-name-prefix = "MIXER1";
445 compatible = "nvidia,tegra186-admaif";
467 dma-names = "rx1", "tx1",
491 compatible = "nvidia,tegra186-asrc";
493 sound-name-prefix = "ASRC1";
498 adma: dma-controller@2930000 {
499 compatible = "nvidia,tegra186-adma";
501 interrupt-parent = <&agic>;
534 #dma-cells = <1>;
536 clock-names = "d_audio";
540 agic: interrupt-controller@2a40000 {
541 compatible = "nvidia,tegra186-agic",
542 "nvidia,tegra210-agic";
543 #interrupt-cells = <3>;
544 interrupt-controller;
550 clock-names = "clk";
555 mc: memory-controller@2c00000 {
556 compatible = "nvidia,tegra186-mc";
557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
563 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
567 #interconnect-cells = <1>;
568 #address-cells = <2>;
569 #size-cells = <2>;
577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
579 emc: external-memory-controller@2c60000 {
580 compatible = "nvidia,tegra186-emc";
584 clock-names = "emc";
586 #interconnect-cells = <0>;
593 compatible = "nvidia,tegra186-timer";
609 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
611 reg-shift = <2>;
616 dma-names = "rx", "tx";
621 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
623 reg-shift = <2>;
628 dma-names = "rx", "tx";
633 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
635 reg-shift = <2>;
640 dma-names = "rx", "tx";
645 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
647 reg-shift = <2>;
652 dma-names = "rx", "tx";
657 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
659 reg-shift = <2>;
664 dma-names = "rx", "tx";
669 compatible = "nvidia,tegra186-i2c";
672 #address-cells = <1>;
673 #size-cells = <0>;
675 clock-names = "div-clk";
677 reset-names = "i2c";
679 dma-names = "rx", "tx";
684 compatible = "nvidia,tegra186-i2c";
687 #address-cells = <1>;
688 #size-cells = <0>;
690 clock-names = "div-clk";
692 reset-names = "i2c";
694 dma-names = "rx", "tx";
700 compatible = "nvidia,tegra186-i2c";
703 #address-cells = <1>;
704 #size-cells = <0>;
706 clock-names = "div-clk";
708 reset-names = "i2c";
709 pinctrl-names = "default", "idle";
710 pinctrl-0 = <&state_dpaux1_i2c>;
711 pinctrl-1 = <&state_dpaux1_off>;
713 dma-names = "rx", "tx";
719 compatible = "nvidia,tegra186-i2c";
722 #address-cells = <1>;
723 #size-cells = <0>;
725 clock-names = "div-clk";
727 reset-names = "i2c";
733 compatible = "nvidia,tegra186-i2c";
736 #address-cells = <1>;
737 #size-cells = <0>;
739 clock-names = "div-clk";
741 reset-names = "i2c";
742 pinctrl-names = "default", "idle";
743 pinctrl-0 = <&state_dpaux_i2c>;
744 pinctrl-1 = <&state_dpaux_off>;
746 dma-names = "rx", "tx";
751 compatible = "nvidia,tegra186-i2c";
754 #address-cells = <1>;
755 #size-cells = <0>;
757 clock-names = "div-clk";
759 reset-names = "i2c";
761 dma-names = "rx", "tx";
766 compatible = "nvidia,tegra186-i2c";
769 #address-cells = <1>;
770 #size-cells = <0>;
772 clock-names = "div-clk";
774 reset-names = "i2c";
776 dma-names = "rx", "tx";
781 compatible = "nvidia,tegra186-pwm";
785 reset-names = "pwm";
787 #pwm-cells = <2>;
791 compatible = "nvidia,tegra186-pwm";
795 reset-names = "pwm";
797 #pwm-cells = <2>;
801 compatible = "nvidia,tegra186-pwm";
805 reset-names = "pwm";
807 #pwm-cells = <2>;
811 compatible = "nvidia,tegra186-pwm";
815 reset-names = "pwm";
817 #pwm-cells = <2>;
821 compatible = "nvidia,tegra186-pwm";
825 reset-names = "pwm";
827 #pwm-cells = <2>;
831 compatible = "nvidia,tegra186-pwm";
835 reset-names = "pwm";
837 #pwm-cells = <2>;
841 compatible = "nvidia,tegra186-pwm";
845 reset-names = "pwm";
847 #pwm-cells = <2>;
851 compatible = "nvidia,tegra186-sdhci";
856 clock-names = "sdhci", "tmclk";
858 reset-names = "sdhci";
861 interconnect-names = "dma-mem", "write";
863 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
864 pinctrl-0 = <&sdmmc1_3v3>;
865 pinctrl-1 = <&sdmmc1_1v8>;
866 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
867 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
868 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
869 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
870 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
871 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
872 nvidia,default-tap = <0x5>;
873 nvidia,default-trim = <0xb>;
874 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
876 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
881 compatible = "nvidia,tegra186-sdhci";
886 clock-names = "sdhci", "tmclk";
888 reset-names = "sdhci";
891 interconnect-names = "dma-mem", "write";
893 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
894 pinctrl-0 = <&sdmmc2_3v3>;
895 pinctrl-1 = <&sdmmc2_1v8>;
896 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
897 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
898 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
899 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
900 nvidia,default-tap = <0x5>;
901 nvidia,default-trim = <0xb>;
906 compatible = "nvidia,tegra186-sdhci";
911 clock-names = "sdhci", "tmclk";
913 reset-names = "sdhci";
916 interconnect-names = "dma-mem", "write";
918 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
919 pinctrl-0 = <&sdmmc3_3v3>;
920 pinctrl-1 = <&sdmmc3_1v8>;
921 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
922 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
923 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
924 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
925 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
926 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
927 nvidia,default-tap = <0x5>;
928 nvidia,default-trim = <0xb>;
933 compatible = "nvidia,tegra186-sdhci";
938 clock-names = "sdhci", "tmclk";
939 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
941 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
943 reset-names = "sdhci";
946 interconnect-names = "dma-mem", "write";
948 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
949 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
950 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
951 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
952 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
953 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
954 nvidia,default-tap = <0x9>;
955 nvidia,default-trim = <0x5>;
956 nvidia,dqs-trim = <63>;
957 mmc-hs400-1_8v;
958 supports-cqe;
963 compatible = "nvidia,tegra186-ahci";
969 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
972 interconnect-names = "dma-mem", "write";
977 clock-names = "sata", "sata-oob";
978 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
980 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
982 assigned-clock-rates = <102000000>,
986 reset-names = "sata", "sata-cold";
991 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
997 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1001 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1002 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1005 interconnect-names = "dma-mem", "write";
1011 compatible = "nvidia,tegra186-xusb-padctl";
1014 reg-names = "padctl", "ao";
1018 reset-names = "padctl";
1025 clock-names = "trk";
1029 usb2-0 {
1031 #phy-cells = <0>;
1034 usb2-1 {
1036 #phy-cells = <0>;
1039 usb2-2 {
1041 #phy-cells = <0>;
1048 clock-names = "trk";
1052 hsic-0 {
1054 #phy-cells = <0>;
1063 usb3-0 {
1065 #phy-cells = <0>;
1068 usb3-1 {
1070 #phy-cells = <0>;
1073 usb3-2 {
1075 #phy-cells = <0>;
1082 usb2-0 {
1086 usb2-1 {
1090 usb2-2 {
1094 hsic-0 {
1098 usb3-0 {
1102 usb3-1 {
1106 usb3-2 {
1113 compatible = "nvidia,tegra186-xusb";
1116 reg-names = "hcd", "fpci";
1128 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1131 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1133 power-domain-names = "xusb_host", "xusb_ss";
1136 interconnect-names = "dma-mem", "write";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1142 nvidia,xusb-padctl = <&padctl>;
1146 compatible = "nvidia,tegra186-xudc";
1149 reg-names = "base", "fpci";
1155 clock-names = "dev", "ss", "ss_src", "fs_src";
1158 interconnect-names = "dma-mem", "write";
1160 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1162 power-domain-names = "dev", "ss";
1163 nvidia,xusb-padctl = <&padctl>;
1168 compatible = "nvidia,tegra186-efuse";
1171 clock-names = "fuse";
1174 gic: interrupt-controller@3881000 {
1175 compatible = "arm,gic-400";
1176 #interrupt-cells = <3>;
1177 interrupt-controller;
1184 interrupt-parent = <&gic>;
1188 compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec";
1192 clock-names = "cec";
1197 compatible = "nvidia,tegra186-hsp";
1200 interrupt-names = "doorbell";
1201 #mbox-cells = <2>;
1206 compatible = "nvidia,tegra186-i2c";
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1212 clock-names = "div-clk";
1214 reset-names = "i2c";
1216 dma-names = "rx", "tx";
1221 compatible = "nvidia,tegra186-i2c";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1227 clock-names = "div-clk";
1229 reset-names = "i2c";
1231 dma-names = "rx", "tx";
1236 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1238 reg-shift = <2>;
1243 dma-names = "rx", "tx";
1248 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1250 reg-shift = <2>;
1255 dma-names = "rx", "tx";
1260 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1262 interrupt-parent = <&pmc>;
1265 clock-names = "rtc";
1270 compatible = "nvidia,tegra186-gpio-aon";
1271 reg-names = "security", "gpio";
1275 gpio-controller;
1276 #gpio-cells = <2>;
1277 interrupt-controller;
1278 #interrupt-cells = <2>;
1282 compatible = "nvidia,tegra186-pwm";
1286 reset-names = "pwm";
1288 #pwm-cells = <2>;
1292 compatible = "nvidia,tegra186-pmc";
1297 reg-names = "pmc", "wake", "aotag", "scratch";
1299 #interrupt-cells = <2>;
1300 interrupt-controller;
1302 sdmmc1_1v8: sdmmc1-1v8 {
1303 pins = "sdmmc1-hv";
1304 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1307 sdmmc1_3v3: sdmmc1-3v3 {
1308 pins = "sdmmc1-hv";
1309 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1312 sdmmc2_1v8: sdmmc2-1v8 {
1313 pins = "sdmmc2-hv";
1314 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1317 sdmmc2_3v3: sdmmc2-3v3 {
1318 pins = "sdmmc2-hv";
1319 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1322 sdmmc3_1v8: sdmmc3-1v8 {
1323 pins = "sdmmc3-hv";
1324 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1327 sdmmc3_3v3: sdmmc3-3v3 {
1328 pins = "sdmmc3-hv";
1329 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1334 compatible = "nvidia,tegra186-ccplex-cluster";
1341 compatible = "nvidia,tegra186-pcie";
1342 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1347 reg-names = "pads", "afi", "cs";
1351 interrupt-names = "intr", "msi";
1353 #interrupt-cells = <1>;
1354 interrupt-map-mask = <0 0 0 0>;
1355 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1357 bus-range = <0x00 0xff>;
1358 #address-cells = <3>;
1359 #size-cells = <2>;
1365 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1371 clock-names = "pex", "afi", "pll_e";
1376 reset-names = "pex", "afi", "pcie_x";
1380 interconnect-names = "dma-mem", "write";
1383 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1384 iommu-map-mask = <0x0>;
1390 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1394 #address-cells = <3>;
1395 #size-cells = <2>;
1398 nvidia,num-lanes = <2>;
1403 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1407 #address-cells = <3>;
1408 #size-cells = <2>;
1411 nvidia,num-lanes = <1>;
1416 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1420 #address-cells = <3>;
1421 #size-cells = <2>;
1424 nvidia,num-lanes = <1>;
1429 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1496 stream-match-mask = <0x7f80>;
1497 #global-interrupts = <1>;
1498 #iommu-cells = <1>;
1500 nvidia,memory-controller = <&mc>;
1504 compatible = "nvidia,tegra186-host1x";
1507 reg-names = "hypervisor", "vm";
1510 interrupt-names = "syncpt", "host1x";
1512 clock-names = "host1x";
1514 reset-names = "host1x";
1516 #address-cells = <2>;
1517 #size-cells = <2>;
1522 interconnect-names = "dma-mem";
1527 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1537 compatible = "nvidia,tegra186-dpaux";
1542 clock-names = "dpaux", "parent";
1544 reset-names = "dpaux";
1547 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1549 state_dpaux1_aux: pinmux-aux {
1550 groups = "dpaux-io";
1554 state_dpaux1_i2c: pinmux-i2c {
1555 groups = "dpaux-io";
1559 state_dpaux1_off: pinmux-off {
1560 groups = "dpaux-io";
1564 i2c-bus {
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1570 display-hub@15200000 {
1571 compatible = "nvidia,tegra186-display";
1580 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1585 clock-names = "disp", "dsc", "hub";
1588 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1590 #address-cells = <2>;
1591 #size-cells = <2>;
1596 compatible = "nvidia,tegra186-dc";
1600 clock-names = "dc";
1602 reset-names = "dc";
1604 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1607 interconnect-names = "dma-mem", "read-1";
1615 compatible = "nvidia,tegra186-dc";
1619 clock-names = "dc";
1621 reset-names = "dc";
1623 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1626 interconnect-names = "dma-mem", "read-1";
1634 compatible = "nvidia,tegra186-dc";
1638 clock-names = "dc";
1640 reset-names = "dc";
1642 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1645 interconnect-names = "dma-mem", "read-1";
1654 compatible = "nvidia,tegra186-dsi";
1660 clock-names = "dsi", "lp", "parent";
1662 reset-names = "dsi";
1665 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1669 compatible = "nvidia,tegra186-vic";
1673 clock-names = "vic";
1675 reset-names = "vic";
1677 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1680 interconnect-names = "dma-mem", "write";
1685 compatible = "nvidia,tegra186-nvjpg";
1688 clock-names = "nvjpg";
1690 reset-names = "nvjpg";
1692 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1695 interconnect-names = "dma-mem", "write";
1700 compatible = "nvidia,tegra186-dsi";
1706 clock-names = "dsi", "lp", "parent";
1708 reset-names = "dsi";
1711 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1715 compatible = "nvidia,tegra186-nvdec";
1718 clock-names = "nvdec";
1720 reset-names = "nvdec";
1722 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1726 interconnect-names = "dma-mem", "read-1", "write";
1731 compatible = "nvidia,tegra186-nvenc";
1734 clock-names = "nvenc";
1736 reset-names = "nvenc";
1738 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1741 interconnect-names = "dma-mem", "write";
1746 compatible = "nvidia,tegra186-sor";
1755 clock-names = "sor", "out", "parent", "dp", "safe",
1758 reset-names = "sor";
1759 pinctrl-0 = <&state_dpaux_aux>;
1760 pinctrl-1 = <&state_dpaux_i2c>;
1761 pinctrl-2 = <&state_dpaux_off>;
1762 pinctrl-names = "aux", "i2c", "off";
1765 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1770 compatible = "nvidia,tegra186-sor";
1779 clock-names = "sor", "out", "parent", "dp", "safe",
1782 reset-names = "sor";
1783 pinctrl-0 = <&state_dpaux1_aux>;
1784 pinctrl-1 = <&state_dpaux1_i2c>;
1785 pinctrl-2 = <&state_dpaux1_off>;
1786 pinctrl-names = "aux", "i2c", "off";
1789 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1794 compatible = "nvidia,tegra186-dpaux";
1799 clock-names = "dpaux", "parent";
1801 reset-names = "dpaux";
1804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1806 state_dpaux_aux: pinmux-aux {
1807 groups = "dpaux-io";
1811 state_dpaux_i2c: pinmux-i2c {
1812 groups = "dpaux-io";
1816 state_dpaux_off: pinmux-off {
1817 groups = "dpaux-io";
1821 i2c-bus {
1822 #address-cells = <1>;
1823 #size-cells = <0>;
1828 compatible = "nvidia,tegra186-dsi-padctl";
1831 reset-names = "dsi";
1836 compatible = "nvidia,tegra186-dsi";
1842 clock-names = "dsi", "lp", "parent";
1844 reset-names = "dsi";
1847 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1851 compatible = "nvidia,tegra186-dsi";
1857 clock-names = "dsi", "lp", "parent";
1859 reset-names = "dsi";
1862 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1872 interrupt-names = "stall", "nonstall";
1876 clock-names = "gpu", "pwr";
1878 reset-names = "gpu";
1881 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1886 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1890 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1892 #address-cells = <1>;
1893 #size-cells = <1>;
1895 no-memory-wc;
1899 label = "cpu-bpmp-tx";
1905 label = "cpu-bpmp-rx";
1911 compatible = "nvidia,tegra186-bpmp";
1916 interconnect-names = "read", "write", "dma-mem", "dma-write";
1921 #clock-cells = <1>;
1922 #reset-cells = <1>;
1923 #power-domain-cells = <1>;
1926 compatible = "nvidia,tegra186-bpmp-i2c";
1927 nvidia,bpmp-bus-id = <5>;
1928 #address-cells = <1>;
1929 #size-cells = <0>;
1934 compatible = "nvidia,tegra186-bpmp-thermal";
1935 #thermal-sensor-cells = <1>;
1940 #address-cells = <1>;
1941 #size-cells = <0>;
1944 compatible = "nvidia,tegra186-denver";
1946 i-cache-size = <0x20000>;
1947 i-cache-line-size = <64>;
1948 i-cache-sets = <512>;
1949 d-cache-size = <0x10000>;
1950 d-cache-line-size = <64>;
1951 d-cache-sets = <256>;
1952 next-level-cache = <&L2_DENVER>;
1957 compatible = "nvidia,tegra186-denver";
1959 i-cache-size = <0x20000>;
1960 i-cache-line-size = <64>;
1961 i-cache-sets = <512>;
1962 d-cache-size = <0x10000>;
1963 d-cache-line-size = <64>;
1964 d-cache-sets = <256>;
1965 next-level-cache = <&L2_DENVER>;
1970 compatible = "arm,cortex-a57";
1972 i-cache-size = <0xC000>;
1973 i-cache-line-size = <64>;
1974 i-cache-sets = <256>;
1975 d-cache-size = <0x8000>;
1976 d-cache-line-size = <64>;
1977 d-cache-sets = <256>;
1978 next-level-cache = <&L2_A57>;
1983 compatible = "arm,cortex-a57";
1985 i-cache-size = <0xC000>;
1986 i-cache-line-size = <64>;
1987 i-cache-sets = <256>;
1988 d-cache-size = <0x8000>;
1989 d-cache-line-size = <64>;
1990 d-cache-sets = <256>;
1991 next-level-cache = <&L2_A57>;
1996 compatible = "arm,cortex-a57";
1998 i-cache-size = <0xC000>;
1999 i-cache-line-size = <64>;
2000 i-cache-sets = <256>;
2001 d-cache-size = <0x8000>;
2002 d-cache-line-size = <64>;
2003 d-cache-sets = <256>;
2004 next-level-cache = <&L2_A57>;
2009 compatible = "arm,cortex-a57";
2011 i-cache-size = <0xC000>;
2012 i-cache-line-size = <64>;
2013 i-cache-sets = <256>;
2014 d-cache-size = <0x8000>;
2015 d-cache-line-size = <64>;
2016 d-cache-sets = <256>;
2017 next-level-cache = <&L2_A57>;
2021 L2_DENVER: l2-cache0 {
2023 cache-unified;
2024 cache-level = <2>;
2025 cache-size = <0x200000>;
2026 cache-line-size = <64>;
2027 cache-sets = <2048>;
2030 L2_A57: l2-cache1 {
2032 cache-unified;
2033 cache-level = <2>;
2034 cache-size = <0x200000>;
2035 cache-line-size = <64>;
2036 cache-sets = <2048>;
2040 pmu-a57 {
2041 compatible = "arm,cortex-a57-pmu";
2046 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2049 pmu-denver {
2050 compatible = "nvidia,denver-pmu";
2053 interrupt-affinity = <&denver_0 &denver_1>;
2061 clock-names = "pll_a", "plla_out0";
2062 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2065 assigned-clock-parents = <0>,
2073 assigned-clock-rates = <258000000>;
2078 thermal-zones {
2079 /* Cortex-A57 cluster */
2080 cpu-thermal {
2081 polling-delay = <0>;
2082 polling-delay-passive = <1000>;
2084 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2094 cooling-maps {
2099 aux-thermal {
2100 polling-delay = <0>;
2101 polling-delay-passive = <1000>;
2103 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2113 cooling-maps {
2117 gpu-thermal {
2118 polling-delay = <0>;
2119 polling-delay-passive = <1000>;
2121 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2131 cooling-maps {
2135 pll-thermal {
2136 polling-delay = <0>;
2137 polling-delay-passive = <1000>;
2139 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2149 cooling-maps {
2153 ao-thermal {
2154 polling-delay = <0>;
2155 polling-delay-passive = <1000>;
2157 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2167 cooling-maps {
2173 compatible = "arm,armv8-timer";
2182 interrupt-parent = <&gic>;
2183 always-on;