Lines Matching +full:sgpio +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 next-level-cache = <&L2_0>;
47 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
53 L2_0: l2-cache0 {
55 cache-level = <2>;
56 cache-unified;
60 arm-pmu {
61 compatible = "arm,cortex-a53-pmu";
63 interrupt-affinity = <&cpu0>, <&cpu1>;
67 compatible = "arm,psci-0.2";
72 compatible = "arm,armv8-timer";
79 lcpll_clk: lcpll-clk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <2500000000>;
85 clks: clock-controller@61110000c {
86 compatible = "microchip,sparx5-dpll";
87 #clock-cells = <1>;
92 ahb_clk: ahb-clk {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <250000000>;
98 sys_clk: sys-clk {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <625000000>;
105 compatible = "simple-bus";
106 #address-cells = <2>;
107 #size-cells = <1>;
110 gic: interrupt-controller@600300000 {
111 compatible = "arm,gic-v3";
112 #interrupt-cells = <3>;
113 #address-cells = <2>;
114 #size-cells = <2>;
115 interrupt-controller;
125 compatible = "microchip,sparx5-cpu-syscon", "syscon",
126 "simple-mfd";
128 mux: mux-controller {
129 compatible = "mmio-mux";
130 #mux-control-cells = <0>;
133 * SPI: value 9 - (SIMC,SIBM) = 0b1001
134 * SPI2: value 6 - (SIBM,SIMC) = 0b0110
136 mux-reg-masks = <0x88 0xf0>;
140 reset: reset-controller@611010008 {
141 compatible = "microchip,sparx5-switch-reset";
143 reg-names = "gcb";
144 #reset-cells = <1>;
145 cpu-syscon = <&cpu_ctrl>;
149 pinctrl-0 = <&uart_pins>;
150 pinctrl-names = "default";
154 reg-io-width = <4>;
155 reg-shift = <2>;
162 pinctrl-0 = <&uart2_pins>;
163 pinctrl-names = "default";
167 reg-io-width = <4>;
168 reg-shift = <2>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "microchip,sparx5-spi";
179 num-cs = <16>;
180 reg-io-width = <4>;
181 reg-shift = <2>;
188 compatible = "snps,dw-apb-timer";
191 clock-names = "timer";
196 compatible = "microchip,dw-sparx5-sdhci";
199 pinctrl-0 = <&emmc_pins>;
200 pinctrl-names = "default";
202 clock-names = "core";
203 assigned-clocks = <&clks CLK_ID_AUX1>;
204 assigned-clock-rates = <800000000>;
206 bus-width = <8>;
209 gpio: pinctrl@6110101e0 { label
210 compatible = "microchip,sparx5-pinctrl";
212 gpio-controller;
213 #gpio-cells = <2>;
214 gpio-ranges = <&gpio 0 0 64>;
215 interrupt-controller;
217 #interrupt-cells = <2>;
219 cs1_pins: cs1-pins {
224 cs2_pins: cs2-pins {
229 cs3_pins: cs3-pins {
234 si2_pins: si2-pins {
239 sgpio0_pins: sgpio-pins {
244 sgpio1_pins: sgpio1-pins {
249 sgpio2_pins: sgpio2-pins {
255 uart_pins: uart-pins {
260 uart2_pins: uart2-pins {
265 i2c_pins: i2c-pins {
270 i2c2_pins: i2c2-pins {
275 emmc_pins: emmc-pins {
284 miim1_pins: miim1-pins {
289 miim2_pins: miim2-pins {
294 miim3_pins: miim3-pins {
300 sgpio0: gpio@61101036c {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 compatible = "microchip,sparx5-sgpio";
306 pinctrl-0 = <&sgpio0_pins>;
307 pinctrl-names = "default";
309 reset-names = "switch";
311 sgpio_in0: gpio@0 {
312 compatible = "microchip,sparx5-sgpio-bank";
314 gpio-controller;
315 #gpio-cells = <3>;
318 interrupt-controller;
319 #interrupt-cells = <3>;
321 sgpio_out0: gpio@1 {
322 compatible = "microchip,sparx5-sgpio-bank";
324 gpio-controller;
325 #gpio-cells = <3>;
330 sgpio1: gpio@611010484 {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 compatible = "microchip,sparx5-sgpio";
336 pinctrl-0 = <&sgpio1_pins>;
337 pinctrl-names = "default";
339 reset-names = "switch";
341 sgpio_in1: gpio@0 {
342 compatible = "microchip,sparx5-sgpio-bank";
344 gpio-controller;
345 #gpio-cells = <3>;
348 interrupt-controller;
349 #interrupt-cells = <3>;
351 sgpio_out1: gpio@1 {
352 compatible = "microchip,sparx5-sgpio-bank";
354 gpio-controller;
355 #gpio-cells = <3>;
360 sgpio2: gpio@61101059c {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 compatible = "microchip,sparx5-sgpio";
366 pinctrl-0 = <&sgpio2_pins>;
367 pinctrl-names = "default";
369 reset-names = "switch";
371 sgpio_in2: gpio@0 {
373 compatible = "microchip,sparx5-sgpio-bank";
374 gpio-controller;
375 #gpio-cells = <3>;
378 interrupt-controller;
379 #interrupt-cells = <3>;
381 sgpio_out2: gpio@1 {
382 compatible = "microchip,sparx5-sgpio-bank";
384 gpio-controller;
385 #gpio-cells = <3>;
391 compatible = "snps,designware-i2c";
393 pinctrl-0 = <&i2c_pins>;
394 pinctrl-names = "default";
396 #address-cells = <1>;
397 #size-cells = <0>;
399 i2c-sda-hold-time-ns = <300>;
400 clock-frequency = <100000>;
405 compatible = "snps,designware-i2c";
407 pinctrl-0 = <&i2c2_pins>;
408 pinctrl-names = "default";
410 #address-cells = <1>;
411 #size-cells = <0>;
413 i2c-sda-hold-time-ns = <300>;
414 clock-frequency = <100000>;
419 compatible = "microchip,sparx5-temp";
421 #thermal-sensor-cells = <0>;
426 compatible = "mscc,ocelot-miim";
428 #address-cells = <1>;
429 #size-cells = <0>;
434 compatible = "mscc,ocelot-miim";
436 pinctrl-0 = <&miim1_pins>;
437 pinctrl-names = "default";
438 #address-cells = <1>;
439 #size-cells = <0>;
444 compatible = "mscc,ocelot-miim";
446 pinctrl-0 = <&miim2_pins>;
447 pinctrl-names = "default";
448 #address-cells = <1>;
449 #size-cells = <0>;
454 compatible = "mscc,ocelot-miim";
456 pinctrl-0 = <&miim3_pins>;
457 pinctrl-names = "default";
458 #address-cells = <1>;
459 #size-cells = <0>;
464 compatible = "microchip,sparx5-serdes";
465 #phy-cells = <1>;
471 compatible = "microchip,sparx5-switch";
475 reg-names = "cpu", "dev", "gcb";
476 interrupt-names = "xtr", "fdma", "ptp";
481 reset-names = "switch";