Lines Matching +full:- +full:topckgen
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8516-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "mt8516-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 cluster0_opp: opp-table-0 {
22 compatible = "operating-points-v2";
23 opp-shared;
24 opp-598000000 {
25 opp-hz = /bits/ 64 <598000000>;
26 opp-microvolt = <1150000>;
28 opp-747500000 {
29 opp-hz = /bits/ 64 <747500000>;
30 opp-microvolt = <1150000>;
32 opp-1040000000 {
33 opp-hz = /bits/ 64 <1040000000>;
34 opp-microvolt = <1200000>;
36 opp-1196000000 {
37 opp-hz = /bits/ 64 <1196000000>;
38 opp-microvolt = <1250000>;
40 opp-1300000000 {
41 opp-hz = /bits/ 64 <1300000000>;
42 opp-microvolt = <1300000>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a35";
54 enable-method = "psci";
55 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
58 <&topckgen CLK_TOP_MAINPLL_D2>;
59 clock-names = "cpu", "intermediate";
60 operating-points-v2 = <&cluster0_opp>;
65 compatible = "arm,cortex-a35";
67 enable-method = "psci";
68 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
71 <&topckgen CLK_TOP_MAINPLL_D2>;
72 clock-names = "cpu", "intermediate";
73 operating-points-v2 = <&cluster0_opp>;
78 compatible = "arm,cortex-a35";
80 enable-method = "psci";
81 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
84 <&topckgen CLK_TOP_MAINPLL_D2>;
85 clock-names = "cpu", "intermediate";
86 operating-points-v2 = <&cluster0_opp>;
91 compatible = "arm,cortex-a35";
93 enable-method = "psci";
94 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
97 <&topckgen CLK_TOP_MAINPLL_D2>;
98 clock-names = "cpu", "intermediate", "armpll";
99 operating-points-v2 = <&cluster0_opp>;
102 idle-states {
103 entry-method = "psci";
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
106 compatible = "arm,idle-state";
107 entry-latency-us = <600>;
108 exit-latency-us = <600>;
109 min-residency-us = <1200>;
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
114 compatible = "arm,idle-state";
115 entry-latency-us = <800>;
116 exit-latency-us = <1000>;
117 min-residency-us = <2000>;
118 arm,psci-suspend-param = <0x2010000>;
124 compatible = "arm,psci-1.0";
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <26000000>;
132 clock-output-names = "clk26m";
136 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 clock-frequency = <32000>;
139 clock-output-names = "clk32k";
142 reserved-memory {
143 #address-cells = <2>;
144 #size-cells = <2>;
149 no-map;
155 compatible = "arm,armv8-timer";
156 interrupt-parent = <&gic>;
168 compatible = "arm,cortex-a35-pmu";
173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
177 #address-cells = <2>;
178 #size-cells = <2>;
179 compatible = "simple-bus";
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
185 #clock-cells = <1>;
189 compatible = "mediatek,mt8516-infracfg", "syscon";
191 #clock-cells = <1>;
195 compatible = "mediatek,mt8516-pericfg", "syscon";
200 compatible = "mediatek,mt8516-apmixedsys", "syscon";
202 #clock-cells = <1>;
206 compatible = "mediatek,mt8516-wdt",
207 "mediatek,mt6589-wdt";
210 #reset-cells = <1>;
214 compatible = "mediatek,mt8516-timer",
215 "mediatek,mt6577-timer";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
220 clock-names = "clk13m", "bus";
223 syscfg_pctl: syscfg-pctl@10005000 {
229 compatible = "mediatek,mt8516-pinctrl";
231 mediatek,pctl-regmap = <&syscfg_pctl>;
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
240 compatible = "mediatek,mt8516-efuse", "mediatek,efuse";
242 #address-cells = <1>;
243 #size-cells = <1>;
247 compatible = "mediatek,mt8516-pwrap";
249 reg-names = "pwrap";
251 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
252 <&topckgen CLK_TOP_PMICWRAP_AP>;
253 clock-names = "spi", "wrap";
256 sysirq: interrupt-controller@10200620 {
257 compatible = "mediatek,mt8516-sysirq",
258 "mediatek,mt6577-sysirq";
259 interrupt-controller;
260 #interrupt-cells = <3>;
261 interrupt-parent = <&gic>;
265 gic: interrupt-controller@10310000 {
266 compatible = "arm,gic-400";
267 #interrupt-cells = <3>;
268 interrupt-parent = <&gic>;
269 interrupt-controller;
278 apdma: dma-controller@11000480 {
279 compatible = "mediatek,mt8516-uart-dma",
280 "mediatek,mt6577-uart-dma";
293 dma-requests = <6>;
294 clocks = <&topckgen CLK_TOP_APDMA>;
295 clock-names = "apdma";
296 #dma-cells = <1>;
300 compatible = "mediatek,mt8516-uart",
301 "mediatek,mt6577-uart";
304 clocks = <&topckgen CLK_TOP_UART0_SEL>,
305 <&topckgen CLK_TOP_UART0>;
306 clock-names = "baud", "bus";
309 dma-names = "tx", "rx";
314 compatible = "mediatek,mt8516-uart",
315 "mediatek,mt6577-uart";
318 clocks = <&topckgen CLK_TOP_UART1_SEL>,
319 <&topckgen CLK_TOP_UART1>;
320 clock-names = "baud", "bus";
323 dma-names = "tx", "rx";
328 compatible = "mediatek,mt8516-uart",
329 "mediatek,mt6577-uart";
332 clocks = <&topckgen CLK_TOP_UART2_SEL>,
333 <&topckgen CLK_TOP_UART2>;
334 clock-names = "baud", "bus";
337 dma-names = "tx", "rx";
342 compatible = "mediatek,mt8516-i2c",
343 "mediatek,mt2712-i2c";
347 clocks = <&topckgen CLK_TOP_I2C0>,
348 <&topckgen CLK_TOP_APDMA>;
349 clock-names = "main", "dma";
350 #address-cells = <1>;
351 #size-cells = <0>;
356 compatible = "mediatek,mt8516-i2c",
357 "mediatek,mt2712-i2c";
361 clocks = <&topckgen CLK_TOP_I2C1>,
362 <&topckgen CLK_TOP_APDMA>;
363 clock-names = "main", "dma";
364 #address-cells = <1>;
365 #size-cells = <0>;
370 compatible = "mediatek,mt8516-i2c",
371 "mediatek,mt2712-i2c";
375 clocks = <&topckgen CLK_TOP_I2C2>,
376 <&topckgen CLK_TOP_APDMA>;
377 clock-names = "main", "dma";
378 #address-cells = <1>;
379 #size-cells = <0>;
384 compatible = "mediatek,mt8516-spi",
385 "mediatek,mt2712-spi";
386 #address-cells = <1>;
387 #size-cells = <0>;
390 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
391 <&topckgen CLK_TOP_SPI_SEL>,
392 <&topckgen CLK_TOP_SPI>;
393 clock-names = "parent-clk", "sel-clk", "spi-clk";
398 compatible = "mediatek,mt8516-mmc";
401 clocks = <&topckgen CLK_TOP_MSDC0>,
402 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
403 <&topckgen CLK_TOP_MSDC0_INFRA>;
404 clock-names = "source", "hclk", "source_cg";
409 compatible = "mediatek,mt8516-mmc";
412 clocks = <&topckgen CLK_TOP_MSDC1>,
413 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
414 <&topckgen CLK_TOP_MSDC1_INFRA>;
415 clock-names = "source", "hclk", "source_cg";
420 compatible = "mediatek,mt8516-mmc";
423 clocks = <&topckgen CLK_TOP_MSDC2>,
424 <&topckgen CLK_TOP_RG_MSDC2>,
425 <&topckgen CLK_TOP_MSDC2_INFRA>;
426 clock-names = "source", "hclk", "source_cg";
431 compatible = "mediatek,mt8516-eth";
435 clocks = <&topckgen CLK_TOP_RG_ETH>,
436 <&topckgen CLK_TOP_66M_ETH>,
437 <&topckgen CLK_TOP_133M_ETH>;
438 clock-names = "core", "reg", "trans";
443 compatible = "mediatek,mt8516-rng",
444 "mediatek,mt7623-rng";
446 clocks = <&topckgen CLK_TOP_TRNG>;
447 clock-names = "rng";
451 compatible = "mediatek,mt8516-pwm";
453 #pwm-cells = <2>;
455 clocks = <&topckgen CLK_TOP_PWM>,
456 <&topckgen CLK_TOP_PWM_B>,
457 <&topckgen CLK_TOP_PWM1_FB>,
458 <&topckgen CLK_TOP_PWM2_FB>,
459 <&topckgen CLK_TOP_PWM3_FB>,
460 <&topckgen CLK_TOP_PWM4_FB>,
461 <&topckgen CLK_TOP_PWM5_FB>;
462 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
467 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
470 interrupt-names = "mc";
472 clocks = <&topckgen CLK_TOP_USB>,
473 <&topckgen CLK_TOP_USBIF>,
474 <&topckgen CLK_TOP_USB_1P>;
475 clock-names = "main","mcu","univpll";
480 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
483 interrupt-names = "mc";
485 clocks = <&topckgen CLK_TOP_USB>,
486 <&topckgen CLK_TOP_USBIF>,
487 <&topckgen CLK_TOP_USB_1P>;
488 clock-names = "main","mcu","univpll";
493 usb_phy: t-phy@11110000 {
494 compatible = "mediatek,mt8516-tphy",
495 "mediatek,generic-tphy-v1";
497 #address-cells = <2>;
498 #size-cells = <2>;
502 usb0_port: usb-phy@11110800 {
504 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
505 clock-names = "ref";
506 #phy-cells = <1>;
509 usb1_port: usb-phy@11110900 {
511 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
512 clock-names = "ref";
513 #phy-cells = <1>;
518 compatible = "mediatek,mt8516-auxadc",
519 "mediatek,mt8173-auxadc";
521 clocks = <&topckgen CLK_TOP_AUX_ADC>;
522 clock-names = "main";
523 #io-channel-cells = <1>;