Lines Matching +full:pinmux +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
20 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
27 stdout-path = "serial0:921600n8";
32 compatible = "linaro,optee-tz";
37 gpio-keys {
38 compatible = "gpio-keys";
39 pinctrl-names = "default";
40 pinctrl-0 = <&gpio_keys>;
42 key-volume-up {
46 wakeup-source;
47 debounce-interval = <15>;
56 usb_otg_vbus: regulator-0 {
57 compatible = "regulator-fixed";
58 regulator-name = "otg_vbus";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
62 enable-active-high;
65 reserved-memory {
66 #address-cells = <2>;
67 #size-cells = <2>;
72 no-map;
76 /* 12 MiB reserved for OP-TEE (BL32)
77 * +-----------------------+ 0x43e0_0000
79 * +-----------------------+ 0x43c0_0000
81 * + TZDRAM +--------------+ 0x4340_0000
83 * +-----------------------+ 0x4320_0000
86 no-map;
92 compatible = "mediatek,mt8365-mt6357";
93 pinctrl-names = "default",
99 pinctrl-0 = <&aud_default_pins>;
100 pinctrl-1 = <&aud_dmic_pins>;
101 pinctrl-2 = <&aud_miso_off_pins>;
102 pinctrl-3 = <&aud_miso_on_pins>;
103 pinctrl-4 = <&aud_mosi_off_pins>;
104 pinctrl-5 = <&aud_mosi_on_pins>;
110 mediatek,dmic-mode = <1>;
115 proc-supply = <&mt6357_vproc_reg>;
116 sram-supply = <&mt6357_vsram_proc_reg>;
120 proc-supply = <&mt6357_vproc_reg>;
121 sram-supply = <&mt6357_vsram_proc_reg>;
125 proc-supply = <&mt6357_vproc_reg>;
126 sram-supply = <&mt6357_vsram_proc_reg>;
130 proc-supply = <&mt6357_vproc_reg>;
131 sram-supply = <&mt6357_vsram_proc_reg>;
135 pinctrl-0 = <ðernet_pins>;
136 pinctrl-names = "default";
137 phy-handle = <ð_phy>;
138 phy-mode = "rmii";
148 #address-cells = <1>;
149 #size-cells = <0>;
151 eth_phy: ethernet-phy@0 {
158 clock-frequency = <100000>;
159 pinctrl-0 = <&i2c0_pins>;
160 pinctrl-names = "default";
165 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
166 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
167 bus-width = <8>;
168 cap-mmc-highspeed;
169 cap-mmc-hw-reset;
170 hs400-ds-delay = <0x12012>;
171 max-frequency = <200000000>;
172 mmc-hs200-1_8v;
173 mmc-hs400-1_8v;
174 no-sd;
175 no-sdio;
176 non-removable;
177 pinctrl-0 = <&mmc0_default_pins>;
178 pinctrl-1 = <&mmc0_uhs_pins>;
179 pinctrl-names = "default", "state_uhs";
180 vmmc-supply = <&mt6357_vemc_reg>;
181 vqmmc-supply = <&mt6357_vio18_reg>;
186 bus-width = <4>;
187 cap-sd-highspeed;
188 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
189 max-frequency = <200000000>;
190 pinctrl-0 = <&mmc1_default_pins>;
191 pinctrl-1 = <&mmc1_uhs_pins>;
192 pinctrl-names = "default", "state_uhs";
193 sd-uhs-sdr104;
194 sd-uhs-sdr50;
195 vmmc-supply = <&mt6357_vmch_reg>;
196 vqmmc-supply = <&mt6357_vmc_reg>;
201 interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 mediatek,micbias0-microvolt = <1900000>;
205 mediatek,micbias1-microvolt = <1700000>;
209 aud_default_pins: audiodefault-pins {
210 clk-dat-pins {
211 pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
218 aud_dmic_pins: audiodmic-pins {
219 clk-dat-pins {
220 pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
226 aud_miso_off_pins: misooff-pins {
227 clk-dat-pins {
228 pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
232 input-enable;
233 bias-pull-down;
234 drive-strength = <2>;
238 aud_miso_on_pins: misoon-pins {
239 clk-dat-pins {
240 pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
244 drive-strength = <6>;
248 aud_mosi_off_pins: mosioff-pins {
249 clk-dat-pins {
250 pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
254 input-enable;
255 bias-pull-down;
256 drive-strength = <2>;
260 aud_mosi_on_pins: mosion-pins {
261 clk-dat-pins {
262 pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
266 drive-strength = <6>;
270 ethernet_pins: ethernet-pins {
272 pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
276 pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
295 gpio_keys: gpio-keys-pins {
297 pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
298 bias-pull-up;
299 input-enable;
303 i2c0_pins: i2c0-pins {
305 pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
307 bias-pull-up;
311 mmc0_default_pins: mmc0-default-pins {
312 clk-pins {
313 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
314 bias-pull-down;
317 cmd-dat-pins {
318 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
327 input-enable;
328 bias-pull-up;
331 rst-pins {
332 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
333 bias-pull-up;
337 mmc0_uhs_pins: mmc0-uhs-pins {
338 clk-pins {
339 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
340 drive-strength = <MTK_DRIVE_10mA>;
341 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
344 cmd-dat-pins {
345 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
354 input-enable;
355 drive-strength = <MTK_DRIVE_10mA>;
356 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
359 ds-pins {
360 pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
361 drive-strength = <MTK_DRIVE_10mA>;
362 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
365 rst-pins {
366 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
367 drive-strength = <MTK_DRIVE_10mA>;
368 bias-pull-up;
372 mmc1_default_pins: mmc1-default-pins {
373 cd-pins {
374 pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
375 bias-pull-up;
378 clk-pins {
379 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
380 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
383 cmd-dat-pins {
384 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
389 input-enable;
390 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
394 mmc1_uhs_pins: mmc1-uhs-pins {
395 clk-pins {
396 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
397 drive-strength = <8>;
398 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
401 cmd-dat-pins {
402 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
407 input-enable;
408 drive-strength = <6>;
409 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
413 uart0_pins: uart0-pins {
415 pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
420 uart1_pins: uart1-pins {
422 pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
427 uart2_pins: uart2-pins {
429 pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
434 usb_pins: usb-pins {
435 id-pins {
436 pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
437 input-enable;
438 bias-pull-up;
441 usb0-vbus-pins {
442 pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
443 output-high;
446 usb1-vbus-pins {
447 pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
448 output-high;
452 pwm_pins: pwm-pins {
454 pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
461 pinctrl-0 = <&pwm_pins>;
462 pinctrl-names = "default";
468 maximum-speed = "high-speed";
469 pinctrl-0 = <&usb_pins>;
470 pinctrl-names = "default";
471 usb-role-switch;
472 vusb33-supply = <&mt6357_vusb33_reg>;
476 compatible = "gpio-usb-b-connector", "usb-b-connector";
477 id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
479 vbus-supply = <&usb_otg_vbus>;
484 vusb33-supply = <&mt6357_vusb33_reg>;
489 pinctrl-0 = <&uart0_pins>;
490 pinctrl-names = "default";
495 pinctrl-0 = <&uart1_pins>;
496 pinctrl-names = "default";
501 pinctrl-0 = <&uart2_pins>;
502 pinctrl-names = "default";