Lines Matching +full:dmic +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
20 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
28 stdout-path = "serial0:921600n8";
32 compatible = "hdmi-connector";
37 #address-cells = <1>;
38 #size-cells = <0>;
41 remote-endpoint = <&hdmi_connector_out>;
48 compatible = "linaro,optee-tz";
53 gpio-keys {
54 compatible = "gpio-keys";
55 pinctrl-names = "default";
56 pinctrl-0 = <&gpio_keys>;
58 key-volume-up {
59 gpios = <&pio 24 GPIO_ACTIVE_LOW>;
62 wakeup-source;
63 debounce-interval = <15>;
72 usb_otg_vbus: regulator-0 {
73 compatible = "regulator-fixed";
74 regulator-name = "otg_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
78 enable-active-high;
81 reserved-memory {
82 #address-cells = <2>;
83 #size-cells = <2>;
88 no-map;
92 /* 12 MiB reserved for OP-TEE (BL32)
93 * +-----------------------+ 0x43e0_0000
95 * +-----------------------+ 0x43c0_0000
97 * + TZDRAM +--------------+ 0x4340_0000
99 * +-----------------------+ 0x4320_0000
102 no-map;
108 compatible = "mediatek,mt8365-mt6357";
109 pinctrl-names = "default",
110 "dmic",
115 pinctrl-0 = <&aud_default_pins>;
116 pinctrl-1 = <&aud_dmic_pins>;
117 pinctrl-2 = <&aud_miso_off_pins>;
118 pinctrl-3 = <&aud_miso_on_pins>;
119 pinctrl-4 = <&aud_mosi_off_pins>;
120 pinctrl-5 = <&aud_mosi_on_pins>;
124 vsys_lcm_reg: regulator-vsys-lcm {
125 compatible = "regulator-fixed";
126 enable-active-high;
128 regulator-max-microvolt = <5000000>;
129 regulator-min-microvolt = <5000000>;
130 regulator-name = "vsys_lcm";
136 mediatek,dmic-mode = <1>;
141 proc-supply = <&mt6357_vproc_reg>;
142 sram-supply = <&mt6357_vsram_proc_reg>;
146 proc-supply = <&mt6357_vproc_reg>;
147 sram-supply = <&mt6357_vsram_proc_reg>;
151 proc-supply = <&mt6357_vproc_reg>;
152 sram-supply = <&mt6357_vsram_proc_reg>;
156 proc-supply = <&mt6357_vproc_reg>;
157 sram-supply = <&mt6357_vsram_proc_reg>;
161 remote-endpoint = <&dsi0_in>;
165 pinctrl-0 = <&dpi_default_pins>;
166 pinctrl-1 = <&dpi_idle_pins>;
167 pinctrl-names = "default", "sleep";
176 #address-cells = <1>;
177 #size-cells = <0>;
180 #address-cells = <1>;
181 #size-cells = <0>;
185 remote-endpoint = <&rdma1_out>;
190 #address-cells = <1>;
191 #size-cells = <0>;
195 remote-endpoint = <&it66121_in>;
202 #address-cells = <1>;
203 #size-cells = <0>;
209 enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>;
210 reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
211 iovcc-supply = <&mt6357_vsim1_reg>;
212 power-supply = <&vsys_lcm_reg>;
215 #address-cells = <1>;
216 #size-cells = <0>;
219 remote-endpoint = <&dsi0_out>;
224 #address-cells = <1>;
225 #size-cells = <0>;
228 #address-cells = <1>;
229 #size-cells = <0>;
233 remote-endpoint = <&dither0_out>;
238 #address-cells = <1>;
239 #size-cells = <0>;
243 remote-endpoint = <&panel_in>;
250 pinctrl-0 = <ðernet_pins>;
251 pinctrl-names = "default";
252 phy-handle = <ð_phy>;
253 phy-mode = "rmii";
263 #address-cells = <1>;
264 #size-cells = <0>;
266 eth_phy: ethernet-phy@0 {
273 clock-frequency = <100000>;
274 pinctrl-0 = <&i2c0_pins>;
275 pinctrl-names = "default";
280 #address-cells = <1>;
281 #size-cells = <0>;
282 clock-div = <2>;
283 clock-frequency = <100000>;
284 pinctrl-0 = <&i2c1_pins>;
285 pinctrl-names = "default";
291 #sound-dai-cells = <0>;
292 interrupt-parent = <&pio>;
294 pinctrl-0 = <&ite_pins>;
295 pinctrl-names = "default";
296 reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
297 vcn18-supply = <&mt6357_vsim2_reg>;
298 vcn33-supply = <&mt6357_vibr_reg>;
299 vrf12-supply = <&mt6357_vrf12_reg>;
302 #address-cells = <1>;
303 #size-cells = <0>;
306 #address-cells = <1>;
307 #size-cells = <0>;
311 bus-width = <12>;
312 remote-endpoint = <&dpi0_out>;
317 #address-cells = <1>;
318 #size-cells = <0>;
322 remote-endpoint = <&hdmi_connector_in>;
330 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
331 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
332 bus-width = <8>;
333 cap-mmc-highspeed;
334 cap-mmc-hw-reset;
335 hs400-ds-delay = <0x12012>;
336 max-frequency = <200000000>;
337 mmc-hs200-1_8v;
338 mmc-hs400-1_8v;
339 no-sd;
340 no-sdio;
341 non-removable;
342 pinctrl-0 = <&mmc0_default_pins>;
343 pinctrl-1 = <&mmc0_uhs_pins>;
344 pinctrl-names = "default", "state_uhs";
345 vmmc-supply = <&mt6357_vemc_reg>;
346 vqmmc-supply = <&mt6357_vio18_reg>;
351 bus-width = <4>;
352 cap-sd-highspeed;
353 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
354 max-frequency = <200000000>;
355 pinctrl-0 = <&mmc1_default_pins>;
356 pinctrl-1 = <&mmc1_uhs_pins>;
357 pinctrl-names = "default", "state_uhs";
358 sd-uhs-sdr104;
359 sd-uhs-sdr50;
360 vmmc-supply = <&mt6357_vmch_reg>;
361 vqmmc-supply = <&mt6357_vmc_reg>;
366 interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 mediatek,micbias0-microvolt = <1900000>;
370 mediatek,micbias1-microvolt = <1700000>;
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <1800000>;
379 aud_default_pins: audiodefault-pins {
380 clk-dat-pins {
388 aud_dmic_pins: audiodmic-pins {
389 clk-dat-pins {
396 aud_miso_off_pins: misooff-pins {
397 clk-dat-pins {
402 input-enable;
403 bias-pull-down;
404 drive-strength = <2>;
408 aud_miso_on_pins: misoon-pins {
409 clk-dat-pins {
414 drive-strength = <6>;
418 aud_mosi_off_pins: mosioff-pins {
419 clk-dat-pins {
424 input-enable;
425 bias-pull-down;
426 drive-strength = <2>;
430 aud_mosi_on_pins: mosion-pins {
431 clk-dat-pins {
436 drive-strength = <6>;
440 dpi_default_pins: dpi-default-pins {
458 drive-strength = <4>;
462 dpi_idle_pins: dpi-idle-pins {
483 ethernet_pins: ethernet-pins {
508 gpio_keys: gpio-keys-pins {
511 bias-pull-up;
512 input-enable;
516 i2c0_pins: i2c0-pins {
520 bias-pull-up;
524 i2c1_pins: i2c1-pins {
528 bias-pull-up;
532 ite_pins: ite-pins {
535 input-enable;
536 bias-pull-up;
542 output-high;
547 output-high;
551 mmc0_default_pins: mmc0-default-pins {
552 clk-pins {
554 bias-pull-down;
557 cmd-dat-pins {
567 input-enable;
568 bias-pull-up;
571 rst-pins {
573 bias-pull-up;
577 mmc0_uhs_pins: mmc0-uhs-pins {
578 clk-pins {
580 drive-strength = <MTK_DRIVE_10mA>;
581 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
584 cmd-dat-pins {
594 input-enable;
595 drive-strength = <MTK_DRIVE_10mA>;
596 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
599 ds-pins {
601 drive-strength = <MTK_DRIVE_10mA>;
602 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
605 rst-pins {
607 drive-strength = <MTK_DRIVE_10mA>;
608 bias-pull-up;
612 mmc1_default_pins: mmc1-default-pins {
613 cd-pins {
615 bias-pull-up;
618 clk-pins {
620 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
623 cmd-dat-pins {
629 input-enable;
630 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
634 mmc1_uhs_pins: mmc1-uhs-pins {
635 clk-pins {
637 drive-strength = <8>;
638 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
641 cmd-dat-pins {
647 input-enable;
648 drive-strength = <6>;
649 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
653 uart0_pins: uart0-pins {
660 uart1_pins: uart1-pins {
667 uart2_pins: uart2-pins {
674 usb_pins: usb-pins {
675 id-pins {
677 input-enable;
678 bias-pull-up;
681 usb0-vbus-pins {
683 output-high;
686 usb1-vbus-pins {
688 output-high;
692 pwm_pins: pwm-pins {
701 pinctrl-0 = <&pwm_pins>;
702 pinctrl-names = "default";
707 remote-endpoint = <&dpi0_in>;
712 maximum-speed = "high-speed";
713 pinctrl-0 = <&usb_pins>;
714 pinctrl-names = "default";
715 usb-role-switch;
716 vusb33-supply = <&mt6357_vusb33_reg>;
720 compatible = "gpio-usb-b-connector", "usb-b-connector";
721 id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
723 vbus-supply = <&usb_otg_vbus>;
728 vusb33-supply = <&mt6357_vusb33_reg>;
733 pinctrl-0 = <&uart0_pins>;
734 pinctrl-names = "default";
739 pinctrl-0 = <&uart1_pins>;
740 pinctrl-names = "default";
745 pinctrl-0 = <&uart2_pins>;
746 pinctrl-names = "default";