Lines Matching +full:vcodec +full:- +full:lat
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
623 clock-names = "vdec1-0";
625 #power-domain-cells = <0>;
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
631 clock-names = "venc1-larb";
633 #power-domain-cells = <0>;
636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 "vdosys0-2", "vdosys0-3",
647 "vdosys0-4", "vdosys0-5";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 #power-domain-cells = <1>;
653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
658 clock-names = "vppsys1", "vppsys1-0",
659 "vppsys1-1";
661 #power-domain-cells = <0>;
664 power-domain@MT8195_POWER_DOMAIN_WPESYS {
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 "wepsys-3";
673 #power-domain-cells = <0>;
676 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
679 clock-names = "vdec0-0";
681 #power-domain-cells = <0>;
684 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
687 clock-names = "vdec2-0";
689 #power-domain-cells = <0>;
692 power-domain@MT8195_POWER_DOMAIN_VENC {
695 clock-names = "venc0-larb";
697 #power-domain-cells = <0>;
700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 #power-domain-cells = <1>;
713 power-domain@MT8195_POWER_DOMAIN_DP_TX {
716 #power-domain-cells = <0>;
719 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
722 #power-domain-cells = <0>;
725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
728 clock-names = "hdmi_tx";
729 #power-domain-cells = <0>;
733 power-domain@MT8195_POWER_DOMAIN_IMG {
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 #power-domain-cells = <1>;
743 power-domain@MT8195_POWER_DOMAIN_DIP {
745 #power-domain-cells = <0>;
748 power-domain@MT8195_POWER_DOMAIN_IPE {
753 clock-names = "ipe", "ipe-0", "ipe-1";
755 #power-domain-cells = <0>;
759 power-domain@MT8195_POWER_DOMAIN_CAM {
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 "cam-4";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <1>;
773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
775 #power-domain-cells = <0>;
778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
780 #power-domain-cells = <0>;
783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
785 #power-domain-cells = <0>;
791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
794 #power-domain-cells = <0>;
797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
800 #power-domain-cells = <0>;
803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
805 #power-domain-cells = <0>;
808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
810 #power-domain-cells = <0>;
813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
817 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power-domain-cells = <0>;
821 power-domain@MT8195_POWER_DOMAIN_ETHER {
824 clock-names = "ether";
825 #power-domain-cells = <0>;
828 power-domain@MT8195_POWER_DOMAIN_ADSP {
832 clock-names = "adsp", "adsp1";
833 #address-cells = <1>;
834 #size-cells = <0>;
836 #power-domain-cells = <1>;
838 power-domain@MT8195_POWER_DOMAIN_AUDIO {
844 clock-names = "audio", "audio1", "audio2",
847 #power-domain-cells = <0>;
854 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrst;
857 #reset-cells = <1>;
861 compatible = "mediatek,mt8195-apmixedsys", "syscon";
863 #clock-cells = <1>;
867 compatible = "mediatek,mt8195-timer",
868 "mediatek,mt6765-timer";
875 compatible = "mediatek,mt8195-pwrap", "syscon";
877 reg-names = "pwrap";
881 clock-names = "spi", "wrap";
882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
887 compatible = "mediatek,mt8195-spmi";
890 reg-names = "pmif", "spmimst";
894 clock-names = "pmif_sys_ck",
897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
901 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek,mt8195-iommu-infra";
909 #iommu-cells = <1>;
913 compatible = "mediatek,mt8195-gce";
916 #mbox-cells = <2>;
921 compatible = "mediatek,mt8195-gce";
924 #mbox-cells = <2>;
929 compatible = "mediatek,mt8195-scp";
933 reg-names = "sram", "cfg", "l1tcm";
938 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek,mt8195-scp_adsp";
941 #clock-cells = <1>;
945 compatible = "mediatek,mt8195-dsp";
948 reg-names = "cfg", "sram";
955 clock-names = "adsp_sel",
961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx";
968 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>;
975 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>;
981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek,mt8195-audio";
985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
988 reset-names = "audiosys";
1008 clock-names = "clk26m",
1031 compatible = "mediatek,mt8195-uart",
1032 "mediatek,mt6577-uart";
1036 clock-names = "baud", "bus";
1041 compatible = "mediatek,mt8195-uart",
1042 "mediatek,mt6577-uart";
1046 clock-names = "baud", "bus";
1051 compatible = "mediatek,mt8195-uart",
1052 "mediatek,mt6577-uart";
1056 clock-names = "baud", "bus";
1061 compatible = "mediatek,mt8195-uart",
1062 "mediatek,mt6577-uart";
1066 clock-names = "baud", "bus";
1071 compatible = "mediatek,mt8195-uart",
1072 "mediatek,mt6577-uart";
1076 clock-names = "baud", "bus";
1081 compatible = "mediatek,mt8195-uart",
1082 "mediatek,mt6577-uart";
1086 clock-names = "baud", "bus";
1091 compatible = "mediatek,mt8195-auxadc",
1092 "mediatek,mt8173-auxadc";
1095 clock-names = "main";
1096 #io-channel-cells = <1>;
1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1103 #clock-cells = <1>;
1107 compatible = "mediatek,mt8195-spi",
1108 "mediatek,mt6765-spi";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1116 clock-names = "parent-clk", "sel-clk", "spi-clk";
1120 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediatek,mt8195-lvts-ap";
1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1132 compatible = "mediatek,mt8195-svs";
1136 clock-names = "main";
1137 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1138 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1140 reset-names = "svs_rst";
1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1147 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148 #pwm-cells = <2>;
1151 clock-names = "main", "mm";
1156 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1159 #pwm-cells = <2>;
1162 clock-names = "main", "mm";
1167 compatible = "mediatek,mt8195-spi",
1168 "mediatek,mt6765-spi";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1176 clock-names = "parent-clk", "sel-clk", "spi-clk";
1181 compatible = "mediatek,mt8195-spi",
1182 "mediatek,mt6765-spi";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1190 clock-names = "parent-clk", "sel-clk", "spi-clk";
1195 compatible = "mediatek,mt8195-spi",
1196 "mediatek,mt6765-spi";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1204 clock-names = "parent-clk", "sel-clk", "spi-clk";
1209 compatible = "mediatek,mt8195-spi",
1210 "mediatek,mt6765-spi";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1218 clock-names = "parent-clk", "sel-clk", "spi-clk";
1223 compatible = "mediatek,mt8195-spi",
1224 "mediatek,mt6765-spi";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1232 clock-names = "parent-clk", "sel-clk", "spi-clk";
1237 compatible = "mediatek,mt8195-spi-slave";
1241 clock-names = "spi";
1242 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1248 compatible = "mediatek,mt8195-spi-slave";
1252 clock-names = "spi";
1253 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1259 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1262 interrupt-names = "macirq";
1263 clock-names = "axi",
1275 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1278 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1281 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1283 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = <&mtl_tx_setup>;
1288 snps,clk-csr = <0>;
1292 compatible = "snps,dwmac-mdio";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1297 stmmac_axi_setup: stmmac-axi-config {
1303 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched-sp;
1307 snps,dcb-algorithm;
1308 snps,map-to-dma-channel = <0x0>;
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1315 snps,dcb-algorithm;
1316 snps,map-to-dma-channel = <0x0>;
1319 snps,dcb-algorithm;
1320 snps,map-to-dma-channel = <0x0>;
1324 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched-wrr;
1329 snps,dcb-algorithm;
1334 snps,dcb-algorithm;
1339 snps,dcb-algorithm;
1344 snps,dcb-algorithm;
1351 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1353 reg-names = "mac", "ippc";
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1361 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1363 wakeup-source;
1364 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1368 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1370 reg-names = "mac";
1372 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1374 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1381 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1387 compatible = "mediatek,mt8195-mmc",
1388 "mediatek,mt8183-mmc";
1395 clock-names = "source", "hclk", "source_cg";
1400 compatible = "mediatek,mt8195-mmc",
1401 "mediatek,mt8183-mmc";
1408 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1415 compatible = "mediatek,mt8195-mmc",
1416 "mediatek,mt8183-mmc";
1423 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1429 lvts_mcu: thermal-sensor@11278000 {
1430 compatible = "mediatek,mt8195-lvts-mcu";
1435 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1436 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1437 #thermal-sensor-cells = <1>;
1441 compatible = "mediatek,mt8195-xhci",
1442 "mediatek,mtk-xhci";
1445 reg-names = "mac", "ippc";
1448 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1457 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1459 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source;
1465 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1467 reg-names = "mac", "ippc";
1469 #address-cells = <2>;
1470 #size-cells = <2>;
1472 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1473 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1477 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1479 wakeup-source;
1480 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1484 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1486 reg-names = "mac";
1488 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1489 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1491 clock-names = "sys_ck";
1497 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1499 reg-names = "mac", "ippc";
1501 #address-cells = <2>;
1502 #size-cells = <2>;
1504 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1505 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1509 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1511 wakeup-source;
1512 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1516 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1518 reg-names = "mac";
1520 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1521 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1523 clock-names = "sys_ck";
1529 compatible = "mediatek,mt8195-pcie",
1530 "mediatek,mt8192-pcie";
1532 #address-cells = <3>;
1533 #size-cells = <2>;
1535 reg-names = "pcie-mac";
1537 bus-range = <0x00 0xff>;
1543 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1544 iommu-map-mask = <0x0>;
1552 clock-names = "pl_250m", "tl_26m", "tl_96m",
1554 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1558 phy-names = "pcie-phy";
1560 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1563 reset-names = "mac";
1565 #interrupt-cells = <1>;
1566 interrupt-map-mask = <0 0 0 7>;
1567 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1573 pcie_intc0: interrupt-controller {
1574 interrupt-controller;
1575 #address-cells = <0>;
1576 #interrupt-cells = <1>;
1581 compatible = "mediatek,mt8195-pcie",
1582 "mediatek,mt8192-pcie";
1584 #address-cells = <3>;
1585 #size-cells = <2>;
1587 reg-names = "pcie-mac";
1589 bus-range = <0x00 0xff>;
1595 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1596 iommu-map-mask = <0x0>;
1605 clock-names = "pl_250m", "tl_26m", "tl_96m",
1607 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1611 phy-names = "pcie-phy";
1612 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1614 #interrupt-cells = <1>;
1615 interrupt-map-mask = <0 0 0 7>;
1616 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1622 pcie_intc1: interrupt-controller {
1623 interrupt-controller;
1624 #address-cells = <0>;
1625 #interrupt-cells = <1>;
1630 compatible = "mediatek,mt8195-nor",
1631 "mediatek,mt8173-nor";
1637 clock-names = "spi", "sf", "axi";
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1644 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1646 #address-cells = <1>;
1647 #size-cells = <1>;
1648 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1652 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1656 u3_intr_p0: usb3-intr@185 {
1660 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1664 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1668 comb_intr_p1: usb3-intr@187 {
1672 u2_intr_p0: usb2-intr-p0@188,1 {
1676 u2_intr_p1: usb2-intr-p1@188,2 {
1680 u2_intr_p2: usb2-intr-p2@189,1 {
1684 u2_intr_p3: usb2-intr-p3@189,2 {
1688 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1692 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1696 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1700 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1704 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1708 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1712 pciephy_glb_intr: pciephy-glb-intr@193 {
1716 dp_calibration: dp-data@1ac {
1719 lvts_efuse_data1: lvts1-calib@1bc {
1722 lvts_efuse_data2: lvts2-calib@1d0 {
1725 svs_calib_data: svs-calib@580 {
1728 socinfo-data1@7a0 {
1733 u3phy2: t-phy@11c40000 {
1734 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1735 #address-cells = <1>;
1736 #size-cells = <1>;
1740 u2port2: usb-phy@0 {
1743 clock-names = "ref";
1744 #phy-cells = <1>;
1748 u3phy3: t-phy@11c50000 {
1749 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1750 #address-cells = <1>;
1751 #size-cells = <1>;
1755 u2port3: usb-phy@0 {
1758 clock-names = "ref";
1759 #phy-cells = <1>;
1763 mipi_tx0: dsi-phy@11c80000 {
1764 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1767 clock-output-names = "mipi_tx0_pll";
1768 #clock-cells = <0>;
1769 #phy-cells = <0>;
1773 mipi_tx1: dsi-phy@11c90000 {
1774 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1777 clock-output-names = "mipi_tx1_pll";
1778 #clock-cells = <0>;
1779 #phy-cells = <0>;
1784 compatible = "mediatek,mt8195-i2c",
1785 "mediatek,mt8192-i2c";
1789 clock-div = <1>;
1792 clock-names = "main", "dma";
1793 #address-cells = <1>;
1794 #size-cells = <0>;
1799 compatible = "mediatek,mt8195-i2c",
1800 "mediatek,mt8192-i2c";
1804 clock-div = <1>;
1807 clock-names = "main", "dma";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1814 compatible = "mediatek,mt8195-i2c",
1815 "mediatek,mt8192-i2c";
1819 clock-div = <1>;
1822 clock-names = "main", "dma";
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1828 imp_iic_wrap_s: clock-controller@11d03000 {
1829 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1831 #clock-cells = <1>;
1835 compatible = "mediatek,mt8195-i2c",
1836 "mediatek,mt8192-i2c";
1840 clock-div = <1>;
1843 clock-names = "main", "dma";
1844 #address-cells = <1>;
1845 #size-cells = <0>;
1850 compatible = "mediatek,mt8195-i2c",
1851 "mediatek,mt8192-i2c";
1855 clock-div = <1>;
1858 clock-names = "main", "dma";
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1865 compatible = "mediatek,mt8195-i2c",
1866 "mediatek,mt8192-i2c";
1870 clock-div = <1>;
1873 clock-names = "main", "dma";
1874 #address-cells = <1>;
1875 #size-cells = <0>;
1880 compatible = "mediatek,mt8195-i2c",
1881 "mediatek,mt8192-i2c";
1885 clock-div = <1>;
1888 clock-names = "main", "dma";
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1895 compatible = "mediatek,mt8195-i2c",
1896 "mediatek,mt8192-i2c";
1900 clock-div = <1>;
1903 clock-names = "main", "dma";
1904 #address-cells = <1>;
1905 #size-cells = <0>;
1909 imp_iic_wrap_w: clock-controller@11e05000 {
1910 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1912 #clock-cells = <1>;
1915 u3phy1: t-phy@11e30000 {
1916 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1917 #address-cells = <1>;
1918 #size-cells = <1>;
1920 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1923 u2port1: usb-phy@0 {
1927 clock-names = "ref", "da_ref";
1928 #phy-cells = <1>;
1931 u3port1: usb-phy@700 {
1935 clock-names = "ref", "da_ref";
1936 nvmem-cells = <&comb_intr_p1>,
1939 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1940 #phy-cells = <1>;
1944 u3phy0: t-phy@11e40000 {
1945 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1946 #address-cells = <1>;
1947 #size-cells = <1>;
1951 u2port0: usb-phy@0 {
1955 clock-names = "ref", "da_ref";
1956 #phy-cells = <1>;
1959 u3port0: usb-phy@700 {
1963 clock-names = "ref", "da_ref";
1964 nvmem-cells = <&u3_intr_p0>,
1967 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1968 #phy-cells = <1>;
1973 compatible = "mediatek,mt8195-pcie-phy";
1975 reg-names = "sif";
1976 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1980 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1984 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1985 #phy-cells = <0>;
1989 ufsphy: ufs-phy@11fa0000 {
1990 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1993 clock-names = "unipro", "mp";
1994 #phy-cells = <0>;
1999 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2000 "arm,mali-valhall-jm";
2007 interrupt-names = "job", "mmu", "gpu";
2008 operating-points-v2 = <&gpu_opp_table>;
2009 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2014 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2018 mfgcfg: clock-controller@13fbf000 {
2019 compatible = "mediatek,mt8195-mfgcfg";
2021 #clock-cells = <1>;
2025 compatible = "mediatek,mt8195-vppsys0", "syscon";
2027 #clock-cells = <1>;
2028 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2031 dma-controller@14001000 {
2032 compatible = "mediatek,mt8195-mdp3-rdma";
2034 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2035 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2038 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2046 #dma-cells = <1>;
2050 compatible = "mediatek,mt8195-mdp3-fg";
2052 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2057 compatible = "mediatek,mt8195-mdp3-stitch";
2059 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2064 compatible = "mediatek,mt8195-mdp3-hdr";
2066 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2071 compatible = "mediatek,mt8195-mdp3-aal";
2074 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2076 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2080 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2082 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2083 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2089 compatible = "mediatek,mt8195-mdp3-tdshp";
2091 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2096 compatible = "mediatek,mt8195-mdp3-color";
2099 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2101 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2105 compatible = "mediatek,mt8195-mdp3-ovl";
2108 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2110 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2115 compatible = "mediatek,mt8195-mdp3-padding";
2117 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2119 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2123 compatible = "mediatek,mt8195-mdp3-tcc";
2125 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2129 dma-controller@1400c000 {
2130 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2132 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2133 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2137 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2138 #dma-cells = <1>;
2142 compatible = "mediatek,mt8195-vpp-mutex";
2145 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2147 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2151 compatible = "mediatek,mt8195-smi-sub-common";
2156 clock-names = "apb", "smi", "gals0";
2158 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2162 compatible = "mediatek,mt8195-smi-sub-common";
2167 clock-names = "apb", "smi", "gals0";
2169 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2173 compatible = "mediatek,mt8195-smi-common-vpp";
2179 clock-names = "apb", "smi", "gals0", "gals1";
2180 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2184 compatible = "mediatek,mt8195-smi-larb";
2186 mediatek,larb-id = <4>;
2190 clock-names = "apb", "smi";
2191 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2195 compatible = "mediatek,mt8195-iommu-vpp";
2203 clock-names = "bclk";
2204 #iommu-cells = <1>;
2205 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2208 wpesys: clock-controller@14e00000 {
2209 compatible = "mediatek,mt8195-wpesys";
2211 #clock-cells = <1>;
2214 wpesys_vpp0: clock-controller@14e02000 {
2215 compatible = "mediatek,mt8195-wpesys_vpp0";
2217 #clock-cells = <1>;
2220 wpesys_vpp1: clock-controller@14e03000 {
2221 compatible = "mediatek,mt8195-wpesys_vpp1";
2223 #clock-cells = <1>;
2227 compatible = "mediatek,mt8195-smi-larb";
2229 mediatek,larb-id = <7>;
2233 clock-names = "apb", "smi";
2234 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2238 compatible = "mediatek,mt8195-smi-larb";
2240 mediatek,larb-id = <8>;
2245 clock-names = "apb", "smi", "gals";
2246 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2250 compatible = "mediatek,mt8195-vppsys1", "syscon";
2252 #clock-cells = <1>;
2253 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2257 compatible = "mediatek,mt8195-vpp-mutex";
2260 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2262 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2266 compatible = "mediatek,mt8195-smi-larb";
2268 mediatek,larb-id = <5>;
2273 clock-names = "apb", "smi", "gals";
2274 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2278 compatible = "mediatek,mt8195-smi-larb";
2280 mediatek,larb-id = <6>;
2285 clock-names = "apb", "smi", "gals";
2286 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2290 compatible = "mediatek,mt8195-mdp3-split";
2292 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2296 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2300 compatible = "mediatek,mt8195-mdp3-tcc";
2302 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2306 dma-controller@14f08000 {
2307 compatible = "mediatek,mt8195-mdp3-rdma";
2309 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2310 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2314 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2315 #dma-cells = <1>;
2318 dma-controller@14f09000 {
2319 compatible = "mediatek,mt8195-mdp3-rdma";
2321 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2322 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2326 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2327 #dma-cells = <1>;
2330 dma-controller@14f0a000 {
2331 compatible = "mediatek,mt8195-mdp3-rdma";
2333 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2334 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2338 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2339 #dma-cells = <1>;
2343 compatible = "mediatek,mt8195-mdp3-fg";
2345 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2350 compatible = "mediatek,mt8195-mdp3-fg";
2352 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2357 compatible = "mediatek,mt8195-mdp3-fg";
2359 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2364 compatible = "mediatek,mt8195-mdp3-hdr";
2366 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2371 compatible = "mediatek,mt8195-mdp3-hdr";
2373 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2378 compatible = "mediatek,mt8195-mdp3-hdr";
2380 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2385 compatible = "mediatek,mt8195-mdp3-aal";
2388 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2390 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2394 compatible = "mediatek,mt8195-mdp3-aal";
2397 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2399 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2403 compatible = "mediatek,mt8195-mdp3-aal";
2406 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2408 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2412 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2414 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2415 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2421 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2423 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2424 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2430 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2432 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2433 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2439 compatible = "mediatek,mt8195-mdp3-tdshp";
2441 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2446 compatible = "mediatek,mt8195-mdp3-tdshp";
2448 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2453 compatible = "mediatek,mt8195-mdp3-tdshp";
2455 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2460 compatible = "mediatek,mt8195-mdp3-merge";
2462 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2464 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2468 compatible = "mediatek,mt8195-mdp3-merge";
2470 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2472 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2476 compatible = "mediatek,mt8195-mdp3-color";
2479 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2481 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2485 compatible = "mediatek,mt8195-mdp3-color";
2487 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2490 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2494 compatible = "mediatek,mt8195-mdp3-color";
2497 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2499 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2503 compatible = "mediatek,mt8195-mdp3-ovl";
2506 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2508 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2513 compatible = "mediatek,mt8195-mdp3-padding";
2515 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2517 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2521 compatible = "mediatek,mt8195-mdp3-padding";
2523 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2525 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2529 compatible = "mediatek,mt8195-mdp3-padding";
2531 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2533 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2536 dma-controller@14f23000 {
2537 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2539 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2540 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2544 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2545 #dma-cells = <1>;
2548 dma-controller@14f24000 {
2549 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2551 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2552 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2556 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2557 #dma-cells = <1>;
2560 dma-controller@14f25000 {
2561 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2563 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2564 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2568 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2569 #dma-cells = <1>;
2572 imgsys: clock-controller@15000000 {
2573 compatible = "mediatek,mt8195-imgsys";
2575 #clock-cells = <1>;
2579 compatible = "mediatek,mt8195-smi-larb";
2581 mediatek,larb-id = <9>;
2586 clock-names = "apb", "smi", "gals";
2587 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2591 compatible = "mediatek,mt8195-smi-sub-common";
2596 clock-names = "apb", "smi", "gals0";
2598 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2602 compatible = "mediatek,mt8195-smi-sub-common";
2607 clock-names = "apb", "smi", "gals0";
2609 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2612 imgsys1_dip_top: clock-controller@15110000 {
2613 compatible = "mediatek,mt8195-imgsys1_dip_top";
2615 #clock-cells = <1>;
2619 compatible = "mediatek,mt8195-smi-larb";
2621 mediatek,larb-id = <10>;
2625 clock-names = "apb", "smi";
2626 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2629 imgsys1_dip_nr: clock-controller@15130000 {
2630 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2632 #clock-cells = <1>;
2635 imgsys1_wpe: clock-controller@15220000 {
2636 compatible = "mediatek,mt8195-imgsys1_wpe";
2638 #clock-cells = <1>;
2642 compatible = "mediatek,mt8195-smi-larb";
2644 mediatek,larb-id = <11>;
2648 clock-names = "apb", "smi";
2649 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2652 ipesys: clock-controller@15330000 {
2653 compatible = "mediatek,mt8195-ipesys";
2655 #clock-cells = <1>;
2659 compatible = "mediatek,mt8195-smi-larb";
2661 mediatek,larb-id = <12>;
2665 clock-names = "apb", "smi";
2666 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2669 camsys: clock-controller@16000000 {
2670 compatible = "mediatek,mt8195-camsys";
2672 #clock-cells = <1>;
2676 compatible = "mediatek,mt8195-smi-larb";
2678 mediatek,larb-id = <13>;
2683 clock-names = "apb", "smi", "gals";
2684 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2688 compatible = "mediatek,mt8195-smi-larb";
2690 mediatek,larb-id = <14>;
2694 clock-names = "apb", "smi";
2695 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2699 compatible = "mediatek,mt8195-smi-sub-common";
2704 clock-names = "apb", "smi", "gals0";
2706 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2710 compatible = "mediatek,mt8195-smi-sub-common";
2715 clock-names = "apb", "smi", "gals0";
2717 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2721 compatible = "mediatek,mt8195-smi-larb";
2723 mediatek,larb-id = <16>;
2727 clock-names = "apb", "smi";
2728 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2732 compatible = "mediatek,mt8195-smi-larb";
2734 mediatek,larb-id = <17>;
2738 clock-names = "apb", "smi";
2739 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2743 compatible = "mediatek,mt8195-smi-larb";
2745 mediatek,larb-id = <27>;
2749 clock-names = "apb", "smi";
2750 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2754 compatible = "mediatek,mt8195-smi-larb";
2756 mediatek,larb-id = <28>;
2760 clock-names = "apb", "smi";
2761 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2764 camsys_rawa: clock-controller@1604f000 {
2765 compatible = "mediatek,mt8195-camsys_rawa";
2767 #clock-cells = <1>;
2770 camsys_yuva: clock-controller@1606f000 {
2771 compatible = "mediatek,mt8195-camsys_yuva";
2773 #clock-cells = <1>;
2776 camsys_rawb: clock-controller@1608f000 {
2777 compatible = "mediatek,mt8195-camsys_rawb";
2779 #clock-cells = <1>;
2782 camsys_yuvb: clock-controller@160af000 {
2783 compatible = "mediatek,mt8195-camsys_yuvb";
2785 #clock-cells = <1>;
2788 camsys_mraw: clock-controller@16140000 {
2789 compatible = "mediatek,mt8195-camsys_mraw";
2791 #clock-cells = <1>;
2795 compatible = "mediatek,mt8195-smi-larb";
2797 mediatek,larb-id = <25>;
2802 clock-names = "apb", "smi", "gals";
2803 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2807 compatible = "mediatek,mt8195-smi-larb";
2809 mediatek,larb-id = <26>;
2813 clock-names = "apb", "smi";
2814 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2818 ccusys: clock-controller@17200000 {
2819 compatible = "mediatek,mt8195-ccusys";
2821 #clock-cells = <1>;
2825 compatible = "mediatek,mt8195-smi-larb";
2827 mediatek,larb-id = <18>;
2831 clock-names = "apb", "smi";
2832 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2835 video-codec@18000000 {
2836 compatible = "mediatek,mt8195-vcodec-dec";
2839 #address-cells = <2>;
2840 #size-cells = <2>;
2845 video-codec@2000 {
2846 compatible = "mediatek,mtk-vcodec-lat-soc";
2854 clock-names = "sel", "vdec", "lat", "top";
2855 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2856 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2857 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2860 video-codec@10000 {
2861 compatible = "mediatek,mtk-vcodec-lat";
2874 clock-names = "sel", "vdec", "lat", "top";
2875 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2876 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2877 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2880 video-codec@25000 {
2881 compatible = "mediatek,mtk-vcodec-core";
2898 clock-names = "sel", "vdec", "lat", "top";
2899 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2900 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2901 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2906 compatible = "mediatek,mt8195-smi-larb";
2908 mediatek,larb-id = <24>;
2912 clock-names = "apb", "smi";
2913 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2917 compatible = "mediatek,mt8195-smi-larb";
2919 mediatek,larb-id = <23>;
2923 clock-names = "apb", "smi";
2924 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2927 vdecsys_soc: clock-controller@1800f000 {
2928 compatible = "mediatek,mt8195-vdecsys_soc";
2930 #clock-cells = <1>;
2934 compatible = "mediatek,mt8195-smi-larb";
2936 mediatek,larb-id = <21>;
2940 clock-names = "apb", "smi";
2941 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2944 vdecsys: clock-controller@1802f000 {
2945 compatible = "mediatek,mt8195-vdecsys";
2947 #clock-cells = <1>;
2951 compatible = "mediatek,mt8195-smi-larb";
2953 mediatek,larb-id = <22>;
2957 clock-names = "apb", "smi";
2958 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2961 vdecsys_core1: clock-controller@1803f000 {
2962 compatible = "mediatek,mt8195-vdecsys_core1";
2964 #clock-cells = <1>;
2967 apusys_pll: clock-controller@190f3000 {
2968 compatible = "mediatek,mt8195-apusys_pll";
2970 #clock-cells = <1>;
2973 vencsys: clock-controller@1a000000 {
2974 compatible = "mediatek,mt8195-vencsys";
2976 #clock-cells = <1>;
2980 compatible = "mediatek,mt8195-smi-larb";
2982 mediatek,larb-id = <19>;
2986 clock-names = "apb", "smi";
2987 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2990 venc: video-codec@1a020000 {
2991 compatible = "mediatek,mt8195-vcodec-enc";
3005 clock-names = "venc_sel";
3006 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3007 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3008 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3009 #address-cells = <2>;
3010 #size-cells = <2>;
3013 jpgdec-master {
3014 compatible = "mediatek,mt8195-jpgdec";
3015 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3022 #address-cells = <2>;
3023 #size-cells = <2>;
3027 compatible = "mediatek,mt8195-jpgdec-hw";
3037 clock-names = "jpgdec";
3038 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3042 compatible = "mediatek,mt8195-jpgdec-hw";
3052 clock-names = "jpgdec";
3053 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3057 compatible = "mediatek,mt8195-jpgdec-hw";
3067 clock-names = "jpgdec";
3068 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3072 vencsys_core1: clock-controller@1b000000 {
3073 compatible = "mediatek,mt8195-vencsys_core1";
3075 #clock-cells = <1>;
3079 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3082 #clock-cells = <1>;
3083 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3087 jpgenc-master {
3088 compatible = "mediatek,mt8195-jpgenc";
3089 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3094 #address-cells = <2>;
3095 #size-cells = <2>;
3099 compatible = "mediatek,mt8195-jpgenc-hw";
3107 clock-names = "jpgenc";
3108 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3112 compatible = "mediatek,mt8195-jpgenc-hw";
3120 clock-names = "jpgenc";
3121 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3126 compatible = "mediatek,mt8195-smi-larb";
3128 mediatek,larb-id = <20>;
3133 clock-names = "apb", "smi", "gals";
3134 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3138 compatible = "mediatek,mt8195-disp-ovl";
3141 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3144 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3148 compatible = "mediatek,mt8195-disp-rdma";
3151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3154 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3158 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3161 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3163 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3167 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3170 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3172 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3176 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3179 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3181 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3185 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3188 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3190 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3194 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3197 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3199 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3203 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3206 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3210 clock-names = "engine", "digital", "hs";
3212 phy-names = "dphy";
3217 compatible = "mediatek,mt8195-disp-dsc";
3220 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3222 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3226 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3229 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3233 clock-names = "engine", "digital", "hs";
3235 phy-names = "dphy";
3240 compatible = "mediatek,mt8195-disp-merge";
3243 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3245 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3248 dp_intf0: dp-intf@1c015000 {
3249 compatible = "mediatek,mt8195-dp-intf";
3255 clock-names = "pixel", "engine", "pll";
3260 compatible = "mediatek,mt8195-disp-mutex";
3263 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3265 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3266 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3270 compatible = "mediatek,mt8195-smi-larb";
3272 mediatek,larb-id = <0>;
3277 clock-names = "apb", "smi", "gals";
3278 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3282 compatible = "mediatek,mt8195-smi-larb";
3284 mediatek,larb-id = <1>;
3289 clock-names = "apb", "smi", "gals";
3290 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3294 compatible = "mediatek,mt8195-vdosys1", "syscon";
3297 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3298 #clock-cells = <1>;
3299 #reset-cells = <1>;
3303 compatible = "mediatek,mt8195-smi-common-vdo";
3309 clock-names = "apb", "smi", "gals0", "gals1";
3310 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3315 compatible = "mediatek,mt8195-iommu-vdo";
3322 #iommu-cells = <1>;
3324 clock-names = "bclk";
3325 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3329 compatible = "mediatek,mt8195-disp-mutex";
3332 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3334 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3335 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3339 compatible = "mediatek,mt8195-smi-larb";
3341 mediatek,larb-id = <2>;
3346 clock-names = "apb", "smi", "gals";
3347 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3351 compatible = "mediatek,mt8195-smi-larb";
3353 mediatek,larb-id = <3>;
3358 clock-names = "apb", "smi", "gals";
3359 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3362 vdo1_rdma0: dma-controller@1c104000 {
3363 compatible = "mediatek,mt8195-vdo1-rdma";
3367 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3369 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3370 #dma-cells = <1>;
3373 vdo1_rdma1: dma-controller@1c105000 {
3374 compatible = "mediatek,mt8195-vdo1-rdma";
3378 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3380 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3381 #dma-cells = <1>;
3384 vdo1_rdma2: dma-controller@1c106000 {
3385 compatible = "mediatek,mt8195-vdo1-rdma";
3389 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3391 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3392 #dma-cells = <1>;
3395 vdo1_rdma3: dma-controller@1c107000 {
3396 compatible = "mediatek,mt8195-vdo1-rdma";
3400 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3402 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3403 #dma-cells = <1>;
3406 vdo1_rdma4: dma-controller@1c108000 {
3407 compatible = "mediatek,mt8195-vdo1-rdma";
3411 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3413 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3414 #dma-cells = <1>;
3417 vdo1_rdma5: dma-controller@1c109000 {
3418 compatible = "mediatek,mt8195-vdo1-rdma";
3422 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3424 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3425 #dma-cells = <1>;
3428 vdo1_rdma6: dma-controller@1c10a000 {
3429 compatible = "mediatek,mt8195-vdo1-rdma";
3433 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3435 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3436 #dma-cells = <1>;
3439 vdo1_rdma7: dma-controller@1c10b000 {
3440 compatible = "mediatek,mt8195-vdo1-rdma";
3444 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3446 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3447 #dma-cells = <1>;
3450 merge1: vpp-merge@1c10c000 {
3451 compatible = "mediatek,mt8195-disp-merge";
3456 clock-names = "merge","merge_async";
3457 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3458 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3459 mediatek,merge-mute;
3463 merge2: vpp-merge@1c10d000 {
3464 compatible = "mediatek,mt8195-disp-merge";
3469 clock-names = "merge","merge_async";
3470 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3471 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3472 mediatek,merge-mute;
3476 merge3: vpp-merge@1c10e000 {
3477 compatible = "mediatek,mt8195-disp-merge";
3482 clock-names = "merge","merge_async";
3483 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3484 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3485 mediatek,merge-mute;
3489 merge4: vpp-merge@1c10f000 {
3490 compatible = "mediatek,mt8195-disp-merge";
3495 clock-names = "merge","merge_async";
3496 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3497 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3498 mediatek,merge-mute;
3502 merge5: vpp-merge@1c110000 {
3503 compatible = "mediatek,mt8195-disp-merge";
3508 clock-names = "merge","merge_async";
3509 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3510 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3511 mediatek,merge-fifo-en;
3515 dp_intf1: dp-intf@1c113000 {
3516 compatible = "mediatek,mt8195-dp-intf";
3519 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3523 clock-names = "pixel", "engine", "pll";
3527 ethdr0: hdr-engine@1c114000 {
3528 compatible = "mediatek,mt8195-disp-ethdr";
3536 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3538 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3558 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3562 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3571 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3575 edp_tx: edp-tx@1c500000 {
3576 compatible = "mediatek,mt8195-edp-tx";
3578 nvmem-cells = <&dp_calibration>;
3579 nvmem-cell-names = "dp_calibration_data";
3580 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3582 max-linkrate-mhz = <8100>;
3586 dp_tx: dp-tx@1c600000 {
3587 compatible = "mediatek,mt8195-dp-tx";
3589 nvmem-cells = <&dp_calibration>;
3590 nvmem-cell-names = "dp_calibration_data";
3591 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3593 max-linkrate-mhz = <8100>;
3598 thermal_zones: thermal-zones {
3599 cpu0-thermal {
3600 polling-delay = <1000>;
3601 polling-delay-passive = <250>;
3602 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3605 cpu0_alert: trip-alert {
3611 cpu0_crit: trip-crit {
3618 cooling-maps {
3621 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3629 cpu1-thermal {
3630 polling-delay = <1000>;
3631 polling-delay-passive = <250>;
3632 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3635 cpu1_alert: trip-alert {
3641 cpu1_crit: trip-crit {
3648 cooling-maps {
3651 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3659 cpu2-thermal {
3660 polling-delay = <1000>;
3661 polling-delay-passive = <250>;
3662 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3665 cpu2_alert: trip-alert {
3671 cpu2_crit: trip-crit {
3678 cooling-maps {
3681 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689 cpu3-thermal {
3690 polling-delay = <1000>;
3691 polling-delay-passive = <250>;
3692 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3695 cpu3_alert: trip-alert {
3701 cpu3_crit: trip-crit {
3708 cooling-maps {
3711 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3719 cpu4-thermal {
3720 polling-delay = <1000>;
3721 polling-delay-passive = <250>;
3722 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3725 cpu4_alert: trip-alert {
3731 cpu4_crit: trip-crit {
3738 cooling-maps {
3741 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3749 cpu5-thermal {
3750 polling-delay = <1000>;
3751 polling-delay-passive = <250>;
3752 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3755 cpu5_alert: trip-alert {
3761 cpu5_crit: trip-crit {
3768 cooling-maps {
3771 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779 cpu6-thermal {
3780 polling-delay = <1000>;
3781 polling-delay-passive = <250>;
3782 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3785 cpu6_alert: trip-alert {
3791 cpu6_crit: trip-crit {
3798 cooling-maps {
3801 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3809 cpu7-thermal {
3810 polling-delay = <1000>;
3811 polling-delay-passive = <250>;
3812 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3815 cpu7_alert: trip-alert {
3821 cpu7_crit: trip-crit {
3828 cooling-maps {
3831 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3839 vpu0-thermal {
3840 polling-delay = <1000>;
3841 polling-delay-passive = <250>;
3842 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3845 vpu0_alert: trip-alert {
3851 vpu0_crit: trip-crit {
3859 vpu1-thermal {
3860 polling-delay = <1000>;
3861 polling-delay-passive = <250>;
3862 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3865 vpu1_alert: trip-alert {
3871 vpu1_crit: trip-crit {
3879 gpu-thermal {
3880 polling-delay = <1000>;
3881 polling-delay-passive = <250>;
3882 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3885 gpu0_alert: trip-alert {
3891 gpu0_crit: trip-crit {
3899 gpu1-thermal {
3900 polling-delay = <1000>;
3901 polling-delay-passive = <250>;
3902 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3905 gpu1_alert: trip-alert {
3911 gpu1_crit: trip-crit {
3919 vdec-thermal {
3920 polling-delay = <1000>;
3921 polling-delay-passive = <250>;
3922 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3925 vdec_alert: trip-alert {
3931 vdec_crit: trip-crit {
3939 img-thermal {
3940 polling-delay = <1000>;
3941 polling-delay-passive = <250>;
3942 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3945 img_alert: trip-alert {
3951 img_crit: trip-crit {
3959 infra-thermal {
3960 polling-delay = <1000>;
3961 polling-delay-passive = <250>;
3962 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3965 infra_alert: trip-alert {
3971 infra_crit: trip-crit {
3979 cam0-thermal {
3980 polling-delay = <1000>;
3981 polling-delay-passive = <250>;
3982 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3985 cam0_alert: trip-alert {
3991 cam0_crit: trip-crit {
3999 cam1-thermal {
4000 polling-delay = <1000>;
4001 polling-delay-passive = <250>;
4002 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
4005 cam1_alert: trip-alert {
4011 cam1_crit: trip-crit {