Lines Matching +full:power +full:- +full:reg
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
56 reg = <0x000>;
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
75 reg = <0x100>;
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
94 reg = <0x200>;
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
113 reg = <0x300>;
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
132 reg = <0x400>;
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
151 reg = <0x500>;
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
170 reg = <0x600>;
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
189 reg = <0x700>;
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
468 reg = <0 0x0c000000 0 0x40000>,
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
485 reg = <0 0x10000000 0 0x1000>;
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
491 reg = <0 0x10001000 0 0x1000>;
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
498 reg = <0 0x10003000 0 0x1000>;
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
504 reg = <0 0x10005000 0 0x1000>,
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
525 reg = <0 0x10006000 0 0x1000>;
527 /* System Power Manager */
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
534 /* power domain of the SoC */
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
542 reg = <MT8195_POWER_DOMAIN_MFG1>;
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
552 reg = <MT8195_POWER_DOMAIN_MFG2>;
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
557 reg = <MT8195_POWER_DOMAIN_MFG3>;
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
562 reg = <MT8195_POWER_DOMAIN_MFG4>;
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
567 reg = <MT8195_POWER_DOMAIN_MFG5>;
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
572 reg = <MT8195_POWER_DOMAIN_MFG6>;
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
621 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
629 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
630 "vdosys0-2", "vdosys0-3",
631 "vdosys0-4", "vdosys0-5";
633 #address-cells = <1>;
634 #size-cells = <0>;
635 #power-domain-cells = <1>;
637 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
638 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
642 clock-names = "vppsys1", "vppsys1-0",
643 "vppsys1-1";
645 #power-domain-cells = <0>;
648 power-domain@MT8195_POWER_DOMAIN_WPESYS {
649 reg = <MT8195_POWER_DOMAIN_WPESYS>;
654 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
655 "wepsys-3";
657 #power-domain-cells = <0>;
660 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
661 reg = <MT8195_POWER_DOMAIN_VDEC0>;
663 clock-names = "vdec0-0";
665 #address-cells = <1>;
666 #size-cells = <0>;
667 #power-domain-cells = <0>;
669 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
670 reg = <MT8195_POWER_DOMAIN_VDEC1>;
672 clock-names = "vdec1-0";
674 #power-domain-cells = <0>;
677 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
678 reg = <MT8195_POWER_DOMAIN_VDEC2>;
680 clock-names = "vdec2-0";
682 #power-domain-cells = <0>;
686 power-domain@MT8195_POWER_DOMAIN_VENC {
687 reg = <MT8195_POWER_DOMAIN_VENC>;
689 clock-names = "venc0-larb";
691 #address-cells = <1>;
692 #size-cells = <0>;
693 #power-domain-cells = <0>;
695 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
696 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
698 clock-names = "venc1-larb";
700 #power-domain-cells = <0>;
704 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
705 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
710 clock-names = "vdosys1", "vdosys1-0",
711 "vdosys1-1", "vdosys1-2";
713 #address-cells = <1>;
714 #size-cells = <0>;
715 #power-domain-cells = <1>;
717 power-domain@MT8195_POWER_DOMAIN_DP_TX {
718 reg = <MT8195_POWER_DOMAIN_DP_TX>;
720 #power-domain-cells = <0>;
723 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
724 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
726 #power-domain-cells = <0>;
729 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
730 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
732 clock-names = "hdmi_tx";
733 #power-domain-cells = <0>;
737 power-domain@MT8195_POWER_DOMAIN_IMG {
738 reg = <MT8195_POWER_DOMAIN_IMG>;
741 clock-names = "img-0", "img-1";
743 #address-cells = <1>;
744 #size-cells = <0>;
745 #power-domain-cells = <1>;
747 power-domain@MT8195_POWER_DOMAIN_DIP {
748 reg = <MT8195_POWER_DOMAIN_DIP>;
749 #power-domain-cells = <0>;
752 power-domain@MT8195_POWER_DOMAIN_IPE {
753 reg = <MT8195_POWER_DOMAIN_IPE>;
757 clock-names = "ipe", "ipe-0", "ipe-1";
759 #power-domain-cells = <0>;
763 power-domain@MT8195_POWER_DOMAIN_CAM {
764 reg = <MT8195_POWER_DOMAIN_CAM>;
770 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
771 "cam-4";
773 #address-cells = <1>;
774 #size-cells = <0>;
775 #power-domain-cells = <1>;
777 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
778 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
779 #power-domain-cells = <0>;
782 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
783 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
784 #power-domain-cells = <0>;
787 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
788 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
789 #power-domain-cells = <0>;
795 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
796 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
798 #power-domain-cells = <0>;
801 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
802 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
804 #power-domain-cells = <0>;
807 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
808 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
809 #power-domain-cells = <0>;
812 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
813 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
814 #power-domain-cells = <0>;
817 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
818 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
821 clock-names = "csi_rx_top", "csi_rx_top1";
822 #power-domain-cells = <0>;
825 power-domain@MT8195_POWER_DOMAIN_ETHER {
826 reg = <MT8195_POWER_DOMAIN_ETHER>;
828 clock-names = "ether";
829 #power-domain-cells = <0>;
832 power-domain@MT8195_POWER_DOMAIN_ADSP {
833 reg = <MT8195_POWER_DOMAIN_ADSP>;
836 clock-names = "adsp", "adsp1";
837 #address-cells = <1>;
838 #size-cells = <0>;
840 #power-domain-cells = <1>;
842 power-domain@MT8195_POWER_DOMAIN_AUDIO {
843 reg = <MT8195_POWER_DOMAIN_AUDIO>;
848 clock-names = "audio", "audio1", "audio2",
851 #power-domain-cells = <0>;
858 compatible = "mediatek,mt8195-wdt";
859 mediatek,disable-extrst;
860 reg = <0 0x10007000 0 0x100>;
861 #reset-cells = <1>;
865 compatible = "mediatek,mt8195-apmixedsys", "syscon";
866 reg = <0 0x1000c000 0 0x1000>;
867 #clock-cells = <1>;
871 compatible = "mediatek,mt8195-timer",
872 "mediatek,mt6765-timer";
873 reg = <0 0x10017000 0 0x1000>;
879 compatible = "mediatek,mt8195-pwrap", "syscon";
880 reg = <0 0x10024000 0 0x1000>;
881 reg-names = "pwrap";
885 clock-names = "spi", "wrap";
886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
891 compatible = "mediatek,mt8195-spmi";
892 reg = <0 0x10027000 0 0x000e00>,
894 reg-names = "pmif", "spmimst";
898 clock-names = "pmif_sys_ck",
901 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
902 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
905 iommu_infra: infra-iommu@10315000 {
906 compatible = "mediatek,mt8195-iommu-infra";
907 reg = <0 0x10315000 0 0x5000>;
913 #iommu-cells = <1>;
917 compatible = "mediatek,mt8195-gce";
918 reg = <0 0x10320000 0 0x4000>;
920 #mbox-cells = <2>;
925 compatible = "mediatek,mt8195-gce";
926 reg = <0 0x10330000 0 0x4000>;
928 #mbox-cells = <2>;
933 compatible = "mediatek,mt8195-scp";
934 reg = <0 0x10500000 0 0x100000>,
937 reg-names = "sram", "cfg", "l1tcm";
942 scp_adsp: clock-controller@10720000 {
943 compatible = "mediatek,mt8195-scp_adsp";
944 reg = <0 0x10720000 0 0x1000>;
945 #clock-cells = <1>;
949 compatible = "mediatek,mt8195-dsp";
950 reg = <0 0x10803000 0 0x1000>,
952 reg-names = "cfg", "sram";
959 clock-names = "adsp_sel",
965 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
966 mbox-names = "rx", "tx";
972 compatible = "mediatek,mt8195-adsp-mbox";
973 #mbox-cells = <0>;
974 reg = <0 0x10816000 0 0x1000>;
979 compatible = "mediatek,mt8195-adsp-mbox";
980 #mbox-cells = <0>;
981 reg = <0 0x10817000 0 0x1000>;
985 afe: mt8195-afe-pcm@10890000 {
986 compatible = "mediatek,mt8195-audio";
987 reg = <0 0x10890000 0 0x10000>;
989 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
992 reset-names = "audiosys";
1012 clock-names = "clk26m",
1035 compatible = "mediatek,mt8195-uart",
1036 "mediatek,mt6577-uart";
1037 reg = <0 0x11001100 0 0x100>;
1040 clock-names = "baud", "bus";
1045 compatible = "mediatek,mt8195-uart",
1046 "mediatek,mt6577-uart";
1047 reg = <0 0x11001200 0 0x100>;
1050 clock-names = "baud", "bus";
1055 compatible = "mediatek,mt8195-uart",
1056 "mediatek,mt6577-uart";
1057 reg = <0 0x11001300 0 0x100>;
1060 clock-names = "baud", "bus";
1065 compatible = "mediatek,mt8195-uart",
1066 "mediatek,mt6577-uart";
1067 reg = <0 0x11001400 0 0x100>;
1070 clock-names = "baud", "bus";
1075 compatible = "mediatek,mt8195-uart",
1076 "mediatek,mt6577-uart";
1077 reg = <0 0x11001500 0 0x100>;
1080 clock-names = "baud", "bus";
1085 compatible = "mediatek,mt8195-uart",
1086 "mediatek,mt6577-uart";
1087 reg = <0 0x11001600 0 0x100>;
1090 clock-names = "baud", "bus";
1095 compatible = "mediatek,mt8195-auxadc",
1096 "mediatek,mt8173-auxadc";
1097 reg = <0 0x11002000 0 0x1000>;
1099 clock-names = "main";
1100 #io-channel-cells = <1>;
1105 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1106 reg = <0 0x11003000 0 0x1000>;
1107 #clock-cells = <1>;
1111 compatible = "mediatek,mt8195-spi",
1112 "mediatek,mt6765-spi";
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1115 reg = <0 0x1100a000 0 0x1000>;
1120 clock-names = "parent-clk", "sel-clk", "spi-clk";
1124 lvts_ap: thermal-sensor@1100b000 {
1125 compatible = "mediatek,mt8195-lvts-ap";
1126 reg = <0 0x1100b000 0 0xc00>;
1130 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1131 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1132 #thermal-sensor-cells = <1>;
1136 compatible = "mediatek,mt8195-svs";
1137 reg = <0 0x1100bc00 0 0x400>;
1140 clock-names = "main";
1141 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1142 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1144 reset-names = "svs_rst";
1148 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1149 reg = <0 0x1100e000 0 0x1000>;
1151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1152 #pwm-cells = <2>;
1155 clock-names = "main", "mm";
1160 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1161 reg = <0 0x1100f000 0 0x1000>;
1163 #pwm-cells = <2>;
1166 clock-names = "main", "mm";
1171 compatible = "mediatek,mt8195-spi",
1172 "mediatek,mt6765-spi";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1175 reg = <0 0x11010000 0 0x1000>;
1180 clock-names = "parent-clk", "sel-clk", "spi-clk";
1185 compatible = "mediatek,mt8195-spi",
1186 "mediatek,mt6765-spi";
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 reg = <0 0x11012000 0 0x1000>;
1194 clock-names = "parent-clk", "sel-clk", "spi-clk";
1199 compatible = "mediatek,mt8195-spi",
1200 "mediatek,mt6765-spi";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1203 reg = <0 0x11013000 0 0x1000>;
1208 clock-names = "parent-clk", "sel-clk", "spi-clk";
1213 compatible = "mediatek,mt8195-spi",
1214 "mediatek,mt6765-spi";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 reg = <0 0x11018000 0 0x1000>;
1222 clock-names = "parent-clk", "sel-clk", "spi-clk";
1227 compatible = "mediatek,mt8195-spi",
1228 "mediatek,mt6765-spi";
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231 reg = <0 0x11019000 0 0x1000>;
1236 clock-names = "parent-clk", "sel-clk", "spi-clk";
1241 compatible = "mediatek,mt8195-spi-slave";
1242 reg = <0 0x1101d000 0 0x1000>;
1245 clock-names = "spi";
1246 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1247 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1252 compatible = "mediatek,mt8195-spi-slave";
1253 reg = <0 0x1101e000 0 0x1000>;
1256 clock-names = "spi";
1257 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1258 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1263 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1264 reg = <0 0x11021000 0 0x4000>;
1266 interrupt-names = "macirq";
1267 clock-names = "axi",
1279 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1282 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1285 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1287 snps,axi-config = <&stmmac_axi_setup>;
1288 snps,mtl-rx-config = <&mtl_rx_setup>;
1289 snps,mtl-tx-config = <&mtl_tx_setup>;
1292 snps,clk-csr = <0>;
1296 compatible = "snps,dwmac-mdio";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1301 stmmac_axi_setup: stmmac-axi-config {
1307 mtl_rx_setup: rx-queues-config {
1308 snps,rx-queues-to-use = <4>;
1309 snps,rx-sched-sp;
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1315 snps,dcb-algorithm;
1316 snps,map-to-dma-channel = <0x0>;
1319 snps,dcb-algorithm;
1320 snps,map-to-dma-channel = <0x0>;
1323 snps,dcb-algorithm;
1324 snps,map-to-dma-channel = <0x0>;
1328 mtl_tx_setup: tx-queues-config {
1329 snps,tx-queues-to-use = <4>;
1330 snps,tx-sched-wrr;
1333 snps,dcb-algorithm;
1338 snps,dcb-algorithm;
1343 snps,dcb-algorithm;
1348 snps,dcb-algorithm;
1355 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1356 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1357 reg-names = "mac", "ippc";
1359 #address-cells = <2>;
1360 #size-cells = <2>;
1365 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1367 wakeup-source;
1368 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1372 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1373 reg = <0 0 0 0x1000>;
1374 reg-names = "mac";
1376 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1378 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1385 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1391 compatible = "mediatek,mt8195-mmc",
1392 "mediatek,mt8183-mmc";
1393 reg = <0 0x11230000 0 0x10000>,
1399 clock-names = "source", "hclk", "source_cg";
1404 compatible = "mediatek,mt8195-mmc",
1405 "mediatek,mt8183-mmc";
1406 reg = <0 0x11240000 0 0x1000>,
1412 clock-names = "source", "hclk", "source_cg";
1413 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1414 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1419 compatible = "mediatek,mt8195-mmc",
1420 "mediatek,mt8183-mmc";
1421 reg = <0 0x11250000 0 0x1000>,
1427 clock-names = "source", "hclk", "source_cg";
1428 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1429 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1434 compatible = "mediatek,mt8195-ufshci";
1435 reg = <0 0x11270000 0 0x2300>;
1446 clock-names = "ufs", "ufs_aes", "ufs_tick",
1450 freq-table-hz = <0 0>, <0 0>, <0 0>,
1454 mediatek,ufs-disable-mcq;
1458 lvts_mcu: thermal-sensor@11278000 {
1459 compatible = "mediatek,mt8195-lvts-mcu";
1460 reg = <0 0x11278000 0 0x1000>;
1464 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1465 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1466 #thermal-sensor-cells = <1>;
1470 compatible = "mediatek,mt8195-xhci",
1471 "mediatek,mtk-xhci";
1472 reg = <0 0x11290000 0 0x1000>,
1474 reg-names = "mac", "ippc";
1477 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1479 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1486 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1488 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1489 wakeup-source;
1494 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1495 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
1496 reg-names = "mac", "ippc";
1498 #address-cells = <2>;
1499 #size-cells = <2>;
1501 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1502 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1506 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1508 wakeup-source;
1509 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1513 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1514 reg = <0 0 0 0x1000>;
1515 reg-names = "mac";
1517 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1518 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1520 clock-names = "sys_ck";
1526 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1527 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
1528 reg-names = "mac", "ippc";
1530 #address-cells = <2>;
1531 #size-cells = <2>;
1533 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1534 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1538 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1540 wakeup-source;
1541 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1545 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1546 reg = <0 0 0 0x1000>;
1547 reg-names = "mac";
1549 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1550 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1552 clock-names = "sys_ck";
1558 compatible = "mediatek,mt8195-pcie",
1559 "mediatek,mt8192-pcie";
1561 #address-cells = <3>;
1562 #size-cells = <2>;
1563 reg = <0 0x112f0000 0 0x4000>;
1564 reg-names = "pcie-mac";
1566 bus-range = <0x00 0xff>;
1572 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1573 iommu-map-mask = <0x0>;
1581 clock-names = "pl_250m", "tl_26m", "tl_96m",
1583 assigned-clocks = <&topckgen CLK_TOP_TL>;
1584 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1587 phy-names = "pcie-phy";
1589 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1592 reset-names = "mac";
1594 #interrupt-cells = <1>;
1595 interrupt-map-mask = <0 0 0 7>;
1596 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1602 pcie_intc0: interrupt-controller {
1603 interrupt-controller;
1604 #address-cells = <0>;
1605 #interrupt-cells = <1>;
1610 compatible = "mediatek,mt8195-pcie",
1611 "mediatek,mt8192-pcie";
1613 #address-cells = <3>;
1614 #size-cells = <2>;
1615 reg = <0 0x112f8000 0 0x4000>;
1616 reg-names = "pcie-mac";
1618 bus-range = <0x00 0xff>;
1624 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1625 iommu-map-mask = <0x0>;
1634 clock-names = "pl_250m", "tl_26m", "tl_96m",
1636 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1637 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1640 phy-names = "pcie-phy";
1641 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1643 #interrupt-cells = <1>;
1644 interrupt-map-mask = <0 0 0 7>;
1645 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1651 pcie_intc1: interrupt-controller {
1652 interrupt-controller;
1653 #address-cells = <0>;
1654 #interrupt-cells = <1>;
1659 compatible = "mediatek,mt8195-nor",
1660 "mediatek,mt8173-nor";
1661 reg = <0 0x1132c000 0 0x1000>;
1666 clock-names = "spi", "sf", "axi";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1673 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1674 reg = <0 0x11c10000 0 0x1000>;
1675 #address-cells = <1>;
1676 #size-cells = <1>;
1677 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1678 reg = <0x184 0x1>;
1681 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1682 reg = <0x184 0x2>;
1685 u3_intr_p0: usb3-intr@185 {
1686 reg = <0x185 0x1>;
1689 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1690 reg = <0x186 0x1>;
1693 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1694 reg = <0x186 0x2>;
1697 comb_intr_p1: usb3-intr@187 {
1698 reg = <0x187 0x1>;
1701 u2_intr_p0: usb2-intr-p0@188,1 {
1702 reg = <0x188 0x1>;
1705 u2_intr_p1: usb2-intr-p1@188,2 {
1706 reg = <0x188 0x2>;
1709 u2_intr_p2: usb2-intr-p2@189,1 {
1710 reg = <0x189 0x1>;
1713 u2_intr_p3: usb2-intr-p3@189,2 {
1714 reg = <0x189 0x2>;
1717 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1718 reg = <0x190 0x1>;
1721 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1722 reg = <0x190 0x1>;
1725 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1726 reg = <0x191 0x1>;
1729 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1730 reg = <0x191 0x1>;
1733 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1734 reg = <0x192 0x1>;
1737 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1738 reg = <0x192 0x1>;
1741 pciephy_glb_intr: pciephy-glb-intr@193 {
1742 reg = <0x193 0x1>;
1745 dp_calibration: dp-data@1ac {
1746 reg = <0x1ac 0x10>;
1748 lvts_efuse_data1: lvts1-calib@1bc {
1749 reg = <0x1bc 0x14>;
1751 lvts_efuse_data2: lvts2-calib@1d0 {
1752 reg = <0x1d0 0x38>;
1754 svs_calib_data: svs-calib@580 {
1755 reg = <0x580 0x64>;
1757 socinfo-data1@7a0 {
1758 reg = <0x7a0 0x4>;
1762 u3phy2: t-phy@11c40000 {
1763 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1764 #address-cells = <1>;
1765 #size-cells = <1>;
1769 u2port2: usb-phy@0 {
1770 reg = <0x0 0x700>;
1772 clock-names = "ref";
1773 #phy-cells = <1>;
1777 u3phy3: t-phy@11c50000 {
1778 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1779 #address-cells = <1>;
1780 #size-cells = <1>;
1784 u2port3: usb-phy@0 {
1785 reg = <0x0 0x700>;
1787 clock-names = "ref";
1788 #phy-cells = <1>;
1792 mipi_tx0: dsi-phy@11c80000 {
1793 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1794 reg = <0 0x11c80000 0 0x1000>;
1796 clock-output-names = "mipi_tx0_pll";
1797 #clock-cells = <0>;
1798 #phy-cells = <0>;
1802 mipi_tx1: dsi-phy@11c90000 {
1803 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1804 reg = <0 0x11c90000 0 0x1000>;
1806 clock-output-names = "mipi_tx1_pll";
1807 #clock-cells = <0>;
1808 #phy-cells = <0>;
1813 compatible = "mediatek,mt8195-i2c",
1814 "mediatek,mt8192-i2c";
1815 reg = <0 0x11d00000 0 0x1000>,
1818 clock-div = <1>;
1821 clock-names = "main", "dma";
1822 #address-cells = <1>;
1823 #size-cells = <0>;
1828 compatible = "mediatek,mt8195-i2c",
1829 "mediatek,mt8192-i2c";
1830 reg = <0 0x11d01000 0 0x1000>,
1833 clock-div = <1>;
1836 clock-names = "main", "dma";
1837 #address-cells = <1>;
1838 #size-cells = <0>;
1843 compatible = "mediatek,mt8195-i2c",
1844 "mediatek,mt8192-i2c";
1845 reg = <0 0x11d02000 0 0x1000>,
1848 clock-div = <1>;
1851 clock-names = "main", "dma";
1852 #address-cells = <1>;
1853 #size-cells = <0>;
1857 imp_iic_wrap_s: clock-controller@11d03000 {
1858 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1859 reg = <0 0x11d03000 0 0x1000>;
1860 #clock-cells = <1>;
1864 compatible = "mediatek,mt8195-i2c",
1865 "mediatek,mt8192-i2c";
1866 reg = <0 0x11e00000 0 0x1000>,
1869 clock-div = <1>;
1872 clock-names = "main", "dma";
1873 #address-cells = <1>;
1874 #size-cells = <0>;
1879 compatible = "mediatek,mt8195-i2c",
1880 "mediatek,mt8192-i2c";
1881 reg = <0 0x11e01000 0 0x1000>,
1884 clock-div = <1>;
1887 clock-names = "main", "dma";
1888 #address-cells = <1>;
1889 #size-cells = <0>;
1894 compatible = "mediatek,mt8195-i2c",
1895 "mediatek,mt8192-i2c";
1896 reg = <0 0x11e02000 0 0x1000>,
1899 clock-div = <1>;
1902 clock-names = "main", "dma";
1903 #address-cells = <1>;
1904 #size-cells = <0>;
1909 compatible = "mediatek,mt8195-i2c",
1910 "mediatek,mt8192-i2c";
1911 reg = <0 0x11e03000 0 0x1000>,
1914 clock-div = <1>;
1917 clock-names = "main", "dma";
1918 #address-cells = <1>;
1919 #size-cells = <0>;
1924 compatible = "mediatek,mt8195-i2c",
1925 "mediatek,mt8192-i2c";
1926 reg = <0 0x11e04000 0 0x1000>,
1929 clock-div = <1>;
1932 clock-names = "main", "dma";
1933 #address-cells = <1>;
1934 #size-cells = <0>;
1938 imp_iic_wrap_w: clock-controller@11e05000 {
1939 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1940 reg = <0 0x11e05000 0 0x1000>;
1941 #clock-cells = <1>;
1944 u3phy1: t-phy@11e30000 {
1945 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1946 #address-cells = <1>;
1947 #size-cells = <1>;
1949 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1952 u2port1: usb-phy@0 {
1953 reg = <0x0 0x700>;
1956 clock-names = "ref", "da_ref";
1957 #phy-cells = <1>;
1960 u3port1: usb-phy@700 {
1961 reg = <0x700 0x700>;
1964 clock-names = "ref", "da_ref";
1965 nvmem-cells = <&comb_intr_p1>,
1968 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1969 #phy-cells = <1>;
1973 u3phy0: t-phy@11e40000 {
1974 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1975 #address-cells = <1>;
1976 #size-cells = <1>;
1980 u2port0: usb-phy@0 {
1981 reg = <0x0 0x700>;
1984 clock-names = "ref", "da_ref";
1985 #phy-cells = <1>;
1988 u3port0: usb-phy@700 {
1989 reg = <0x700 0x700>;
1992 clock-names = "ref", "da_ref";
1993 nvmem-cells = <&u3_intr_p0>,
1996 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1997 #phy-cells = <1>;
2002 compatible = "mediatek,mt8195-pcie-phy";
2003 reg = <0 0x11e80000 0 0x10000>;
2004 reg-names = "sif";
2005 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
2009 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
2013 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
2014 #phy-cells = <0>;
2018 ufsphy: ufs-phy@11fa0000 {
2019 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
2020 reg = <0 0x11fa0000 0 0xc000>;
2022 clock-names = "unipro", "mp";
2023 #phy-cells = <0>;
2028 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2029 "arm,mali-valhall-jm";
2030 reg = <0 0x13000000 0 0x4000>;
2036 interrupt-names = "job", "mmu", "gpu";
2037 operating-points-v2 = <&gpu_opp_table>;
2038 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2043 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2047 mfgcfg: clock-controller@13fbf000 {
2048 compatible = "mediatek,mt8195-mfgcfg";
2049 reg = <0 0x13fbf000 0 0x1000>;
2050 #clock-cells = <1>;
2054 compatible = "mediatek,mt8195-vppsys0", "syscon";
2055 reg = <0 0x14000000 0 0x1000>;
2056 #clock-cells = <1>;
2057 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2060 dma-controller@14001000 {
2061 compatible = "mediatek,mt8195-mdp3-rdma";
2062 reg = <0 0x14001000 0 0x1000>;
2063 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2064 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2067 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2075 #dma-cells = <1>;
2079 compatible = "mediatek,mt8195-mdp3-fg";
2080 reg = <0 0x14002000 0 0x1000>;
2081 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2086 compatible = "mediatek,mt8195-mdp3-stitch";
2087 reg = <0 0x14003000 0 0x1000>;
2088 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2093 compatible = "mediatek,mt8195-mdp3-hdr";
2094 reg = <0 0x14004000 0 0x1000>;
2095 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2100 compatible = "mediatek,mt8195-mdp3-aal";
2101 reg = <0 0x14005000 0 0x1000>;
2103 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2105 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2109 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2110 reg = <0 0x14006000 0 0x1000>;
2111 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2112 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2118 compatible = "mediatek,mt8195-mdp3-tdshp";
2119 reg = <0 0x14007000 0 0x1000>;
2120 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2125 compatible = "mediatek,mt8195-mdp3-color";
2126 reg = <0 0x14008000 0 0x1000>;
2128 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2130 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2134 compatible = "mediatek,mt8195-mdp3-ovl";
2135 reg = <0 0x14009000 0 0x1000>;
2137 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2139 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2144 compatible = "mediatek,mt8195-mdp3-padding";
2145 reg = <0 0x1400a000 0 0x1000>;
2146 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2148 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2152 compatible = "mediatek,mt8195-mdp3-tcc";
2153 reg = <0 0x1400b000 0 0x1000>;
2154 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2158 dma-controller@1400c000 {
2159 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2160 reg = <0 0x1400c000 0 0x1000>;
2161 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2162 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2166 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2167 #dma-cells = <1>;
2171 compatible = "mediatek,mt8195-vpp-mutex";
2172 reg = <0 0x1400f000 0 0x1000>;
2174 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2176 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2180 compatible = "mediatek,mt8195-smi-sub-common";
2181 reg = <0 0x14010000 0 0x1000>;
2185 clock-names = "apb", "smi", "gals0";
2187 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2191 compatible = "mediatek,mt8195-smi-sub-common";
2192 reg = <0 0x14011000 0 0x1000>;
2196 clock-names = "apb", "smi", "gals0";
2198 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2202 compatible = "mediatek,mt8195-smi-common-vpp";
2203 reg = <0 0x14012000 0 0x1000>;
2208 clock-names = "apb", "smi", "gals0", "gals1";
2209 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2213 compatible = "mediatek,mt8195-smi-larb";
2214 reg = <0 0x14013000 0 0x1000>;
2215 mediatek,larb-id = <4>;
2219 clock-names = "apb", "smi";
2220 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2224 compatible = "mediatek,mt8195-iommu-vpp";
2225 reg = <0 0x14018000 0 0x1000>;
2232 clock-names = "bclk";
2233 #iommu-cells = <1>;
2234 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2237 wpesys: clock-controller@14e00000 {
2238 compatible = "mediatek,mt8195-wpesys";
2239 reg = <0 0x14e00000 0 0x1000>;
2240 #clock-cells = <1>;
2243 wpesys_vpp0: clock-controller@14e02000 {
2244 compatible = "mediatek,mt8195-wpesys_vpp0";
2245 reg = <0 0x14e02000 0 0x1000>;
2246 #clock-cells = <1>;
2249 wpesys_vpp1: clock-controller@14e03000 {
2250 compatible = "mediatek,mt8195-wpesys_vpp1";
2251 reg = <0 0x14e03000 0 0x1000>;
2252 #clock-cells = <1>;
2256 compatible = "mediatek,mt8195-smi-larb";
2257 reg = <0 0x14e04000 0 0x1000>;
2258 mediatek,larb-id = <7>;
2262 clock-names = "apb", "smi";
2263 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2267 compatible = "mediatek,mt8195-smi-larb";
2268 reg = <0 0x14e05000 0 0x1000>;
2269 mediatek,larb-id = <8>;
2274 clock-names = "apb", "smi", "gals";
2275 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2279 compatible = "mediatek,mt8195-vppsys1", "syscon";
2280 reg = <0 0x14f00000 0 0x1000>;
2281 #clock-cells = <1>;
2282 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2286 compatible = "mediatek,mt8195-vpp-mutex";
2287 reg = <0 0x14f01000 0 0x1000>;
2289 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2291 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2295 compatible = "mediatek,mt8195-smi-larb";
2296 reg = <0 0x14f02000 0 0x1000>;
2297 mediatek,larb-id = <5>;
2302 clock-names = "apb", "smi", "gals";
2303 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2307 compatible = "mediatek,mt8195-smi-larb";
2308 reg = <0 0x14f03000 0 0x1000>;
2309 mediatek,larb-id = <6>;
2314 clock-names = "apb", "smi", "gals";
2315 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2319 compatible = "mediatek,mt8195-mdp3-split";
2320 reg = <0 0x14f06000 0 0x1000>;
2321 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2325 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2329 compatible = "mediatek,mt8195-mdp3-tcc";
2330 reg = <0 0x14f07000 0 0x1000>;
2331 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2335 dma-controller@14f08000 {
2336 compatible = "mediatek,mt8195-mdp3-rdma";
2337 reg = <0 0x14f08000 0 0x1000>;
2338 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2339 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2343 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2344 #dma-cells = <1>;
2347 dma-controller@14f09000 {
2348 compatible = "mediatek,mt8195-mdp3-rdma";
2349 reg = <0 0x14f09000 0 0x1000>;
2350 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2351 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2355 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2356 #dma-cells = <1>;
2359 dma-controller@14f0a000 {
2360 compatible = "mediatek,mt8195-mdp3-rdma";
2361 reg = <0 0x14f0a000 0 0x1000>;
2362 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2363 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2367 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2368 #dma-cells = <1>;
2372 compatible = "mediatek,mt8195-mdp3-fg";
2373 reg = <0 0x14f0b000 0 0x1000>;
2374 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2379 compatible = "mediatek,mt8195-mdp3-fg";
2380 reg = <0 0x14f0c000 0 0x1000>;
2381 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2386 compatible = "mediatek,mt8195-mdp3-fg";
2387 reg = <0 0x14f0d000 0 0x1000>;
2388 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2393 compatible = "mediatek,mt8195-mdp3-hdr";
2394 reg = <0 0x14f0e000 0 0x1000>;
2395 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2400 compatible = "mediatek,mt8195-mdp3-hdr";
2401 reg = <0 0x14f0f000 0 0x1000>;
2402 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2407 compatible = "mediatek,mt8195-mdp3-hdr";
2408 reg = <0 0x14f10000 0 0x1000>;
2409 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2414 compatible = "mediatek,mt8195-mdp3-aal";
2415 reg = <0 0x14f11000 0 0x1000>;
2417 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2419 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2423 compatible = "mediatek,mt8195-mdp3-aal";
2424 reg = <0 0x14f12000 0 0x1000>;
2426 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2428 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2432 compatible = "mediatek,mt8195-mdp3-aal";
2433 reg = <0 0x14f13000 0 0x1000>;
2435 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2437 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2441 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2442 reg = <0 0x14f14000 0 0x1000>;
2443 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2444 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2450 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2451 reg = <0 0x14f15000 0 0x1000>;
2452 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2453 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2459 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2460 reg = <0 0x14f16000 0 0x1000>;
2461 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2462 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2468 compatible = "mediatek,mt8195-mdp3-tdshp";
2469 reg = <0 0x14f17000 0 0x1000>;
2470 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2475 compatible = "mediatek,mt8195-mdp3-tdshp";
2476 reg = <0 0x14f18000 0 0x1000>;
2477 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2482 compatible = "mediatek,mt8195-mdp3-tdshp";
2483 reg = <0 0x14f19000 0 0x1000>;
2484 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2489 compatible = "mediatek,mt8195-mdp3-merge";
2490 reg = <0 0x14f1a000 0 0x1000>;
2491 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2493 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2497 compatible = "mediatek,mt8195-mdp3-merge";
2498 reg = <0 0x14f1b000 0 0x1000>;
2499 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2501 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2505 compatible = "mediatek,mt8195-mdp3-color";
2506 reg = <0 0x14f1c000 0 0x1000>;
2508 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2510 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2514 compatible = "mediatek,mt8195-mdp3-color";
2515 reg = <0 0x14f1d000 0 0x1000>;
2516 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2519 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2523 compatible = "mediatek,mt8195-mdp3-color";
2524 reg = <0 0x14f1e000 0 0x1000>;
2526 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2528 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2532 compatible = "mediatek,mt8195-mdp3-ovl";
2533 reg = <0 0x14f1f000 0 0x1000>;
2535 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2537 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2542 compatible = "mediatek,mt8195-mdp3-padding";
2543 reg = <0 0x14f20000 0 0x1000>;
2544 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2546 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2550 compatible = "mediatek,mt8195-mdp3-padding";
2551 reg = <0 0x14f21000 0 0x1000>;
2552 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2554 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2558 compatible = "mediatek,mt8195-mdp3-padding";
2559 reg = <0 0x14f22000 0 0x1000>;
2560 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2562 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2565 dma-controller@14f23000 {
2566 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2567 reg = <0 0x14f23000 0 0x1000>;
2568 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2569 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2573 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2574 #dma-cells = <1>;
2577 dma-controller@14f24000 {
2578 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2579 reg = <0 0x14f24000 0 0x1000>;
2580 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2581 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2585 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2586 #dma-cells = <1>;
2589 dma-controller@14f25000 {
2590 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2591 reg = <0 0x14f25000 0 0x1000>;
2592 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2593 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2597 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2598 #dma-cells = <1>;
2601 imgsys: clock-controller@15000000 {
2602 compatible = "mediatek,mt8195-imgsys";
2603 reg = <0 0x15000000 0 0x1000>;
2604 #clock-cells = <1>;
2608 compatible = "mediatek,mt8195-smi-larb";
2609 reg = <0 0x15001000 0 0x1000>;
2610 mediatek,larb-id = <9>;
2615 clock-names = "apb", "smi", "gals";
2616 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2620 compatible = "mediatek,mt8195-smi-sub-common";
2621 reg = <0 0x15002000 0 0x1000>;
2625 clock-names = "apb", "smi", "gals0";
2627 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2631 compatible = "mediatek,mt8195-smi-sub-common";
2632 reg = <0 0x15003000 0 0x1000>;
2636 clock-names = "apb", "smi", "gals0";
2638 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2641 imgsys1_dip_top: clock-controller@15110000 {
2642 compatible = "mediatek,mt8195-imgsys1_dip_top";
2643 reg = <0 0x15110000 0 0x1000>;
2644 #clock-cells = <1>;
2648 compatible = "mediatek,mt8195-smi-larb";
2649 reg = <0 0x15120000 0 0x1000>;
2650 mediatek,larb-id = <10>;
2654 clock-names = "apb", "smi";
2655 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2658 imgsys1_dip_nr: clock-controller@15130000 {
2659 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2660 reg = <0 0x15130000 0 0x1000>;
2661 #clock-cells = <1>;
2664 imgsys1_wpe: clock-controller@15220000 {
2665 compatible = "mediatek,mt8195-imgsys1_wpe";
2666 reg = <0 0x15220000 0 0x1000>;
2667 #clock-cells = <1>;
2671 compatible = "mediatek,mt8195-smi-larb";
2672 reg = <0 0x15230000 0 0x1000>;
2673 mediatek,larb-id = <11>;
2677 clock-names = "apb", "smi";
2678 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2681 ipesys: clock-controller@15330000 {
2682 compatible = "mediatek,mt8195-ipesys";
2683 reg = <0 0x15330000 0 0x1000>;
2684 #clock-cells = <1>;
2688 compatible = "mediatek,mt8195-smi-larb";
2689 reg = <0 0x15340000 0 0x1000>;
2690 mediatek,larb-id = <12>;
2694 clock-names = "apb", "smi";
2695 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2698 camsys: clock-controller@16000000 {
2699 compatible = "mediatek,mt8195-camsys";
2700 reg = <0 0x16000000 0 0x1000>;
2701 #clock-cells = <1>;
2705 compatible = "mediatek,mt8195-smi-larb";
2706 reg = <0 0x16001000 0 0x1000>;
2707 mediatek,larb-id = <13>;
2712 clock-names = "apb", "smi", "gals";
2713 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2717 compatible = "mediatek,mt8195-smi-larb";
2718 reg = <0 0x16002000 0 0x1000>;
2719 mediatek,larb-id = <14>;
2723 clock-names = "apb", "smi";
2724 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2728 compatible = "mediatek,mt8195-smi-sub-common";
2729 reg = <0 0x16004000 0 0x1000>;
2733 clock-names = "apb", "smi", "gals0";
2735 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2739 compatible = "mediatek,mt8195-smi-sub-common";
2740 reg = <0 0x16005000 0 0x1000>;
2744 clock-names = "apb", "smi", "gals0";
2746 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2750 compatible = "mediatek,mt8195-smi-larb";
2751 reg = <0 0x16012000 0 0x1000>;
2752 mediatek,larb-id = <16>;
2756 clock-names = "apb", "smi";
2757 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2761 compatible = "mediatek,mt8195-smi-larb";
2762 reg = <0 0x16013000 0 0x1000>;
2763 mediatek,larb-id = <17>;
2767 clock-names = "apb", "smi";
2768 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2772 compatible = "mediatek,mt8195-smi-larb";
2773 reg = <0 0x16014000 0 0x1000>;
2774 mediatek,larb-id = <27>;
2778 clock-names = "apb", "smi";
2779 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2783 compatible = "mediatek,mt8195-smi-larb";
2784 reg = <0 0x16015000 0 0x1000>;
2785 mediatek,larb-id = <28>;
2789 clock-names = "apb", "smi";
2790 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2793 camsys_rawa: clock-controller@1604f000 {
2794 compatible = "mediatek,mt8195-camsys_rawa";
2795 reg = <0 0x1604f000 0 0x1000>;
2796 #clock-cells = <1>;
2799 camsys_yuva: clock-controller@1606f000 {
2800 compatible = "mediatek,mt8195-camsys_yuva";
2801 reg = <0 0x1606f000 0 0x1000>;
2802 #clock-cells = <1>;
2805 camsys_rawb: clock-controller@1608f000 {
2806 compatible = "mediatek,mt8195-camsys_rawb";
2807 reg = <0 0x1608f000 0 0x1000>;
2808 #clock-cells = <1>;
2811 camsys_yuvb: clock-controller@160af000 {
2812 compatible = "mediatek,mt8195-camsys_yuvb";
2813 reg = <0 0x160af000 0 0x1000>;
2814 #clock-cells = <1>;
2817 camsys_mraw: clock-controller@16140000 {
2818 compatible = "mediatek,mt8195-camsys_mraw";
2819 reg = <0 0x16140000 0 0x1000>;
2820 #clock-cells = <1>;
2824 compatible = "mediatek,mt8195-smi-larb";
2825 reg = <0 0x16141000 0 0x1000>;
2826 mediatek,larb-id = <25>;
2831 clock-names = "apb", "smi", "gals";
2832 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2836 compatible = "mediatek,mt8195-smi-larb";
2837 reg = <0 0x16142000 0 0x1000>;
2838 mediatek,larb-id = <26>;
2842 clock-names = "apb", "smi";
2843 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2847 ccusys: clock-controller@17200000 {
2848 compatible = "mediatek,mt8195-ccusys";
2849 reg = <0 0x17200000 0 0x1000>;
2850 #clock-cells = <1>;
2854 compatible = "mediatek,mt8195-smi-larb";
2855 reg = <0 0x17201000 0 0x1000>;
2856 mediatek,larb-id = <18>;
2860 clock-names = "apb", "smi";
2861 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2864 video-codec@18000000 {
2865 compatible = "mediatek,mt8195-vcodec-dec";
2868 #address-cells = <2>;
2869 #size-cells = <2>;
2870 reg = <0 0x18000000 0 0x1000>,
2874 video-codec@2000 {
2875 compatible = "mediatek,mtk-vcodec-lat-soc";
2876 reg = <0 0x2000 0 0x800>;
2883 clock-names = "sel", "vdec", "lat", "top";
2884 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2885 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2886 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2889 video-codec@10000 {
2890 compatible = "mediatek,mtk-vcodec-lat";
2891 reg = <0 0x10000 0 0x800>;
2903 clock-names = "sel", "vdec", "lat", "top";
2904 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2905 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2906 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2909 video-codec@25000 {
2910 compatible = "mediatek,mtk-vcodec-core";
2911 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */
2927 clock-names = "sel", "vdec", "lat", "top";
2928 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2929 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2930 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2935 compatible = "mediatek,mt8195-smi-larb";
2936 reg = <0 0x1800d000 0 0x1000>;
2937 mediatek,larb-id = <24>;
2941 clock-names = "apb", "smi";
2942 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2946 compatible = "mediatek,mt8195-smi-larb";
2947 reg = <0 0x1800e000 0 0x1000>;
2948 mediatek,larb-id = <23>;
2952 clock-names = "apb", "smi";
2953 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2956 vdecsys_soc: clock-controller@1800f000 {
2957 compatible = "mediatek,mt8195-vdecsys_soc";
2958 reg = <0 0x1800f000 0 0x1000>;
2959 #clock-cells = <1>;
2963 compatible = "mediatek,mt8195-smi-larb";
2964 reg = <0 0x1802e000 0 0x1000>;
2965 mediatek,larb-id = <21>;
2969 clock-names = "apb", "smi";
2970 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2973 vdecsys: clock-controller@1802f000 {
2974 compatible = "mediatek,mt8195-vdecsys";
2975 reg = <0 0x1802f000 0 0x1000>;
2976 #clock-cells = <1>;
2980 compatible = "mediatek,mt8195-smi-larb";
2981 reg = <0 0x1803e000 0 0x1000>;
2982 mediatek,larb-id = <22>;
2986 clock-names = "apb", "smi";
2987 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2990 vdecsys_core1: clock-controller@1803f000 {
2991 compatible = "mediatek,mt8195-vdecsys_core1";
2992 reg = <0 0x1803f000 0 0x1000>;
2993 #clock-cells = <1>;
2996 apusys_pll: clock-controller@190f3000 {
2997 compatible = "mediatek,mt8195-apusys_pll";
2998 reg = <0 0x190f3000 0 0x1000>;
2999 #clock-cells = <1>;
3002 vencsys: clock-controller@1a000000 {
3003 compatible = "mediatek,mt8195-vencsys";
3004 reg = <0 0x1a000000 0 0x1000>;
3005 #clock-cells = <1>;
3009 compatible = "mediatek,mt8195-smi-larb";
3010 reg = <0 0x1a010000 0 0x1000>;
3011 mediatek,larb-id = <19>;
3015 clock-names = "apb", "smi";
3016 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3019 venc: video-codec@1a020000 {
3020 compatible = "mediatek,mt8195-vcodec-enc";
3021 reg = <0 0x1a020000 0 0x10000>;
3034 clock-names = "venc_sel";
3035 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3036 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3037 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3038 #address-cells = <2>;
3039 #size-cells = <2>;
3042 jpgdec-master {
3043 compatible = "mediatek,mt8195-jpgdec";
3044 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3051 #address-cells = <2>;
3052 #size-cells = <2>;
3056 compatible = "mediatek,mt8195-jpgdec-hw";
3057 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
3066 clock-names = "jpgdec";
3067 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3071 compatible = "mediatek,mt8195-jpgdec-hw";
3072 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
3081 clock-names = "jpgdec";
3082 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3086 compatible = "mediatek,mt8195-jpgdec-hw";
3087 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
3096 clock-names = "jpgdec";
3097 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3101 vencsys_core1: clock-controller@1b000000 {
3102 compatible = "mediatek,mt8195-vencsys_core1";
3103 reg = <0 0x1b000000 0 0x1000>;
3104 #clock-cells = <1>;
3108 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3109 reg = <0 0x1c01a000 0 0x1000>;
3111 #clock-cells = <1>;
3112 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3116 jpgenc-master {
3117 compatible = "mediatek,mt8195-jpgenc";
3118 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3123 #address-cells = <2>;
3124 #size-cells = <2>;
3128 compatible = "mediatek,mt8195-jpgenc-hw";
3129 reg = <0 0x1a030000 0 0x10000>;
3136 clock-names = "jpgenc";
3137 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3141 compatible = "mediatek,mt8195-jpgenc-hw";
3142 reg = <0 0x1b030000 0 0x10000>;
3149 clock-names = "jpgenc";
3150 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3155 compatible = "mediatek,mt8195-smi-larb";
3156 reg = <0 0x1b010000 0 0x1000>;
3157 mediatek,larb-id = <20>;
3162 clock-names = "apb", "smi", "gals";
3163 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3167 compatible = "mediatek,mt8195-disp-ovl";
3168 reg = <0 0x1c000000 0 0x1000>;
3170 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3173 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3176 #address-cells = <1>;
3177 #size-cells = <0>;
3180 reg = <0>;
3185 reg = <1>;
3187 remote-endpoint = <&rdma0_in>;
3194 compatible = "mediatek,mt8195-disp-rdma";
3195 reg = <0 0x1c002000 0 0x1000>;
3197 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3200 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3203 #address-cells = <1>;
3204 #size-cells = <0>;
3207 reg = <0>;
3209 remote-endpoint = <&ovl0_out>;
3214 reg = <1>;
3216 remote-endpoint = <&color0_in>;
3223 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3224 reg = <0 0x1c003000 0 0x1000>;
3226 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3228 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3231 #address-cells = <1>;
3232 #size-cells = <0>;
3235 reg = <0>;
3237 remote-endpoint = <&rdma0_out>;
3242 reg = <1>;
3244 remote-endpoint = <&ccorr0_in>;
3251 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3252 reg = <0 0x1c004000 0 0x1000>;
3254 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3256 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3259 #address-cells = <1>;
3260 #size-cells = <0>;
3263 reg = <0>;
3265 remote-endpoint = <&color0_out>;
3270 reg = <1>;
3272 remote-endpoint = <&aal0_in>;
3279 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3280 reg = <0 0x1c005000 0 0x1000>;
3282 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3284 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3287 #address-cells = <1>;
3288 #size-cells = <0>;
3291 reg = <0>;
3293 remote-endpoint = <&ccorr0_out>;
3298 reg = <1>;
3300 remote-endpoint = <&gamma0_in>;
3307 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3308 reg = <0 0x1c006000 0 0x1000>;
3310 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3312 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3315 #address-cells = <1>;
3316 #size-cells = <0>;
3319 reg = <0>;
3321 remote-endpoint = <&aal0_out>;
3326 reg = <1>;
3328 remote-endpoint = <&dither0_in>;
3335 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3336 reg = <0 0x1c007000 0 0x1000>;
3338 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3340 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3343 #address-cells = <1>;
3344 #size-cells = <0>;
3347 reg = <0>;
3349 remote-endpoint = <&gamma0_out>;
3354 reg = <1>;
3361 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3362 reg = <0 0x1c008000 0 0x1000>;
3364 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3368 clock-names = "engine", "digital", "hs";
3370 phy-names = "dphy";
3375 compatible = "mediatek,mt8195-disp-dsc";
3376 reg = <0 0x1c009000 0 0x1000>;
3378 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3380 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3384 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3385 reg = <0 0x1c012000 0 0x1000>;
3387 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3391 clock-names = "engine", "digital", "hs";
3393 phy-names = "dphy";
3398 compatible = "mediatek,mt8195-disp-merge";
3399 reg = <0 0x1c014000 0 0x1000>;
3401 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3403 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3406 dp_intf0: dp-intf@1c015000 {
3407 compatible = "mediatek,mt8195-dp-intf";
3408 reg = <0 0x1c015000 0 0x1000>;
3410 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3414 clock-names = "pixel", "engine", "pll";
3419 compatible = "mediatek,mt8195-disp-mutex";
3420 reg = <0 0x1c016000 0 0x1000>;
3422 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3424 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3425 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3429 compatible = "mediatek,mt8195-smi-larb";
3430 reg = <0 0x1c018000 0 0x1000>;
3431 mediatek,larb-id = <0>;
3436 clock-names = "apb", "smi", "gals";
3437 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3441 compatible = "mediatek,mt8195-smi-larb";
3442 reg = <0 0x1c019000 0 0x1000>;
3443 mediatek,larb-id = <1>;
3448 clock-names = "apb", "smi", "gals";
3449 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3453 compatible = "mediatek,mt8195-vdosys1", "syscon";
3454 reg = <0 0x1c100000 0 0x1000>;
3456 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3457 #clock-cells = <1>;
3458 #reset-cells = <1>;
3462 compatible = "mediatek,mt8195-smi-common-vdo";
3463 reg = <0 0x1c01b000 0 0x1000>;
3468 clock-names = "apb", "smi", "gals0", "gals1";
3469 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3474 compatible = "mediatek,mt8195-iommu-vdo";
3475 reg = <0 0x1c01f000 0 0x1000>;
3481 #iommu-cells = <1>;
3483 clock-names = "bclk";
3484 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3488 compatible = "mediatek,mt8195-disp-mutex";
3489 reg = <0 0x1c101000 0 0x1000>;
3491 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3493 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3494 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3498 compatible = "mediatek,mt8195-smi-larb";
3499 reg = <0 0x1c102000 0 0x1000>;
3500 mediatek,larb-id = <2>;
3505 clock-names = "apb", "smi", "gals";
3506 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3510 compatible = "mediatek,mt8195-smi-larb";
3511 reg = <0 0x1c103000 0 0x1000>;
3512 mediatek,larb-id = <3>;
3517 clock-names = "apb", "smi", "gals";
3518 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3521 vdo1_rdma0: dma-controller@1c104000 {
3522 compatible = "mediatek,mt8195-vdo1-rdma";
3523 reg = <0 0x1c104000 0 0x1000>;
3526 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3528 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3529 #dma-cells = <1>;
3532 vdo1_rdma1: dma-controller@1c105000 {
3533 compatible = "mediatek,mt8195-vdo1-rdma";
3534 reg = <0 0x1c105000 0 0x1000>;
3537 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3539 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3540 #dma-cells = <1>;
3543 vdo1_rdma2: dma-controller@1c106000 {
3544 compatible = "mediatek,mt8195-vdo1-rdma";
3545 reg = <0 0x1c106000 0 0x1000>;
3548 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3550 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3551 #dma-cells = <1>;
3554 vdo1_rdma3: dma-controller@1c107000 {
3555 compatible = "mediatek,mt8195-vdo1-rdma";
3556 reg = <0 0x1c107000 0 0x1000>;
3559 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3561 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3562 #dma-cells = <1>;
3565 vdo1_rdma4: dma-controller@1c108000 {
3566 compatible = "mediatek,mt8195-vdo1-rdma";
3567 reg = <0 0x1c108000 0 0x1000>;
3570 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3572 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3573 #dma-cells = <1>;
3576 vdo1_rdma5: dma-controller@1c109000 {
3577 compatible = "mediatek,mt8195-vdo1-rdma";
3578 reg = <0 0x1c109000 0 0x1000>;
3581 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3583 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3584 #dma-cells = <1>;
3587 vdo1_rdma6: dma-controller@1c10a000 {
3588 compatible = "mediatek,mt8195-vdo1-rdma";
3589 reg = <0 0x1c10a000 0 0x1000>;
3592 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3594 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3595 #dma-cells = <1>;
3598 vdo1_rdma7: dma-controller@1c10b000 {
3599 compatible = "mediatek,mt8195-vdo1-rdma";
3600 reg = <0 0x1c10b000 0 0x1000>;
3603 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3605 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3606 #dma-cells = <1>;
3609 merge1: vpp-merge@1c10c000 {
3610 compatible = "mediatek,mt8195-disp-merge";
3611 reg = <0 0x1c10c000 0 0x1000>;
3615 clock-names = "merge","merge_async";
3616 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3617 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3618 mediatek,merge-mute;
3622 merge2: vpp-merge@1c10d000 {
3623 compatible = "mediatek,mt8195-disp-merge";
3624 reg = <0 0x1c10d000 0 0x1000>;
3628 clock-names = "merge","merge_async";
3629 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3630 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3631 mediatek,merge-mute;
3635 merge3: vpp-merge@1c10e000 {
3636 compatible = "mediatek,mt8195-disp-merge";
3637 reg = <0 0x1c10e000 0 0x1000>;
3641 clock-names = "merge","merge_async";
3642 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3643 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3644 mediatek,merge-mute;
3648 merge4: vpp-merge@1c10f000 {
3649 compatible = "mediatek,mt8195-disp-merge";
3650 reg = <0 0x1c10f000 0 0x1000>;
3654 clock-names = "merge","merge_async";
3655 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3656 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3657 mediatek,merge-mute;
3661 merge5: vpp-merge@1c110000 {
3662 compatible = "mediatek,mt8195-disp-merge";
3663 reg = <0 0x1c110000 0 0x1000>;
3667 clock-names = "merge","merge_async";
3668 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3669 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3670 mediatek,merge-fifo-en;
3674 dp_intf1: dp-intf@1c113000 {
3675 compatible = "mediatek,mt8195-dp-intf";
3676 reg = <0 0x1c113000 0 0x1000>;
3678 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3682 clock-names = "pixel", "engine", "pll";
3686 ethdr0: hdr-engine@1c114000 {
3687 compatible = "mediatek,mt8195-disp-ethdr";
3688 reg = <0 0x1c114000 0 0x1000>,
3695 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3697 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3717 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3721 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3730 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3734 edp_tx: edp-tx@1c500000 {
3735 compatible = "mediatek,mt8195-edp-tx";
3736 reg = <0 0x1c500000 0 0x8000>;
3737 nvmem-cells = <&dp_calibration>;
3738 nvmem-cell-names = "dp_calibration_data";
3739 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3741 max-linkrate-mhz = <8100>;
3745 dp_tx: dp-tx@1c600000 {
3746 compatible = "mediatek,mt8195-dp-tx";
3747 reg = <0 0x1c600000 0 0x8000>;
3748 nvmem-cells = <&dp_calibration>;
3749 nvmem-cell-names = "dp_calibration_data";
3750 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3752 max-linkrate-mhz = <8100>;
3757 thermal_zones: thermal-zones {
3758 cpu0-thermal {
3759 polling-delay = <1000>;
3760 polling-delay-passive = <250>;
3761 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3764 cpu0_alert: trip-alert {
3770 cpu0_crit: trip-crit {
3777 cooling-maps {
3780 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3788 cpu1-thermal {
3789 polling-delay = <1000>;
3790 polling-delay-passive = <250>;
3791 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3794 cpu1_alert: trip-alert {
3800 cpu1_crit: trip-crit {
3807 cooling-maps {
3810 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3818 cpu2-thermal {
3819 polling-delay = <1000>;
3820 polling-delay-passive = <250>;
3821 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3824 cpu2_alert: trip-alert {
3830 cpu2_crit: trip-crit {
3837 cooling-maps {
3840 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3848 cpu3-thermal {
3849 polling-delay = <1000>;
3850 polling-delay-passive = <250>;
3851 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3854 cpu3_alert: trip-alert {
3860 cpu3_crit: trip-crit {
3867 cooling-maps {
3870 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3878 cpu4-thermal {
3879 polling-delay = <1000>;
3880 polling-delay-passive = <250>;
3881 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3884 cpu4_alert: trip-alert {
3890 cpu4_crit: trip-crit {
3897 cooling-maps {
3900 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3908 cpu5-thermal {
3909 polling-delay = <1000>;
3910 polling-delay-passive = <250>;
3911 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3914 cpu5_alert: trip-alert {
3920 cpu5_crit: trip-crit {
3927 cooling-maps {
3930 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3938 cpu6-thermal {
3939 polling-delay = <1000>;
3940 polling-delay-passive = <250>;
3941 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3944 cpu6_alert: trip-alert {
3950 cpu6_crit: trip-crit {
3957 cooling-maps {
3960 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3968 cpu7-thermal {
3969 polling-delay = <1000>;
3970 polling-delay-passive = <250>;
3971 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3974 cpu7_alert: trip-alert {
3980 cpu7_crit: trip-crit {
3987 cooling-maps {
3990 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998 vpu0-thermal {
3999 polling-delay = <1000>;
4000 polling-delay-passive = <250>;
4001 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
4004 vpu0_alert: trip-alert {
4010 vpu0_crit: trip-crit {
4018 vpu1-thermal {
4019 polling-delay = <1000>;
4020 polling-delay-passive = <250>;
4021 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
4024 vpu1_alert: trip-alert {
4030 vpu1_crit: trip-crit {
4038 gpu-thermal {
4039 polling-delay = <1000>;
4040 polling-delay-passive = <250>;
4041 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
4044 gpu0_alert: trip-alert {
4050 gpu0_crit: trip-crit {
4058 gpu1-thermal {
4059 polling-delay = <1000>;
4060 polling-delay-passive = <250>;
4061 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
4064 gpu1_alert: trip-alert {
4070 gpu1_crit: trip-crit {
4078 vdec-thermal {
4079 polling-delay = <1000>;
4080 polling-delay-passive = <250>;
4081 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
4084 vdec_alert: trip-alert {
4090 vdec_crit: trip-crit {
4098 img-thermal {
4099 polling-delay = <1000>;
4100 polling-delay-passive = <250>;
4101 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
4104 img_alert: trip-alert {
4110 img_crit: trip-crit {
4118 infra-thermal {
4119 polling-delay = <1000>;
4120 polling-delay-passive = <250>;
4121 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
4124 infra_alert: trip-alert {
4130 infra_crit: trip-crit {
4138 cam0-thermal {
4139 polling-delay = <1000>;
4140 polling-delay-passive = <250>;
4141 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
4144 cam0_alert: trip-alert {
4150 cam0_crit: trip-crit {
4158 cam1-thermal {
4159 polling-delay = <1000>;
4160 polling-delay-passive = <250>;
4161 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
4164 cam1_alert: trip-alert {
4170 cam1_crit: trip-crit {