Lines Matching +full:mt8195 +full:- +full:disp +full:- +full:ethdr
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
629 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
630 "vdosys0-2", "vdosys0-3",
631 "vdosys0-4", "vdosys0-5";
633 #address-cells = <1>;
634 #size-cells = <0>;
635 #power-domain-cells = <1>;
637 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
642 clock-names = "vppsys1", "vppsys1-0",
643 "vppsys1-1";
645 #power-domain-cells = <0>;
648 power-domain@MT8195_POWER_DOMAIN_WPESYS {
654 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
655 "wepsys-3";
657 #power-domain-cells = <0>;
660 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
663 clock-names = "vdec0-0";
665 #address-cells = <1>;
666 #size-cells = <0>;
667 #power-domain-cells = <0>;
669 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
672 clock-names = "vdec1-0";
674 #power-domain-cells = <0>;
677 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
680 clock-names = "vdec2-0";
682 #power-domain-cells = <0>;
686 power-domain@MT8195_POWER_DOMAIN_VENC {
689 clock-names = "venc0-larb";
691 #address-cells = <1>;
692 #size-cells = <0>;
693 #power-domain-cells = <0>;
695 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
698 clock-names = "venc1-larb";
700 #power-domain-cells = <0>;
704 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
710 clock-names = "vdosys1", "vdosys1-0",
711 "vdosys1-1", "vdosys1-2";
713 #address-cells = <1>;
714 #size-cells = <0>;
715 #power-domain-cells = <1>;
717 power-domain@MT8195_POWER_DOMAIN_DP_TX {
720 #power-domain-cells = <0>;
723 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
726 #power-domain-cells = <0>;
729 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
732 clock-names = "hdmi_tx";
733 #power-domain-cells = <0>;
737 power-domain@MT8195_POWER_DOMAIN_IMG {
741 clock-names = "img-0", "img-1";
743 #address-cells = <1>;
744 #size-cells = <0>;
745 #power-domain-cells = <1>;
747 power-domain@MT8195_POWER_DOMAIN_DIP {
749 #power-domain-cells = <0>;
752 power-domain@MT8195_POWER_DOMAIN_IPE {
757 clock-names = "ipe", "ipe-0", "ipe-1";
759 #power-domain-cells = <0>;
763 power-domain@MT8195_POWER_DOMAIN_CAM {
770 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
771 "cam-4";
773 #address-cells = <1>;
774 #size-cells = <0>;
775 #power-domain-cells = <1>;
777 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
779 #power-domain-cells = <0>;
782 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
784 #power-domain-cells = <0>;
787 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
789 #power-domain-cells = <0>;
795 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
798 #power-domain-cells = <0>;
801 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
804 #power-domain-cells = <0>;
807 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
809 #power-domain-cells = <0>;
812 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
814 #power-domain-cells = <0>;
817 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
821 clock-names = "csi_rx_top", "csi_rx_top1";
822 #power-domain-cells = <0>;
825 power-domain@MT8195_POWER_DOMAIN_ETHER {
828 clock-names = "ether";
829 #power-domain-cells = <0>;
832 power-domain@MT8195_POWER_DOMAIN_ADSP {
836 clock-names = "adsp", "adsp1";
837 #address-cells = <1>;
838 #size-cells = <0>;
840 #power-domain-cells = <1>;
842 power-domain@MT8195_POWER_DOMAIN_AUDIO {
848 clock-names = "audio", "audio1", "audio2",
851 #power-domain-cells = <0>;
858 compatible = "mediatek,mt8195-wdt";
859 mediatek,disable-extrst;
861 #reset-cells = <1>;
865 compatible = "mediatek,mt8195-apmixedsys", "syscon";
867 #clock-cells = <1>;
871 compatible = "mediatek,mt8195-timer",
872 "mediatek,mt6765-timer";
879 compatible = "mediatek,mt8195-pwrap", "syscon";
881 reg-names = "pwrap";
885 clock-names = "spi", "wrap";
886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
891 compatible = "mediatek,mt8195-spmi";
894 reg-names = "pmif", "spmimst";
898 clock-names = "pmif_sys_ck",
901 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
902 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
905 iommu_infra: infra-iommu@10315000 {
906 compatible = "mediatek,mt8195-iommu-infra";
913 #iommu-cells = <1>;
917 compatible = "mediatek,mt8195-gce";
920 #mbox-cells = <2>;
925 compatible = "mediatek,mt8195-gce";
928 #mbox-cells = <2>;
933 compatible = "mediatek,mt8195-scp";
937 reg-names = "sram", "cfg", "l1tcm";
942 scp_adsp: clock-controller@10720000 {
943 compatible = "mediatek,mt8195-scp_adsp";
945 #clock-cells = <1>;
949 compatible = "mediatek,mt8195-dsp";
952 reg-names = "cfg", "sram";
959 clock-names = "adsp_sel",
965 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
966 mbox-names = "rx", "tx";
972 compatible = "mediatek,mt8195-adsp-mbox";
973 #mbox-cells = <0>;
979 compatible = "mediatek,mt8195-adsp-mbox";
980 #mbox-cells = <0>;
985 afe: mt8195-afe-pcm@10890000 {
986 compatible = "mediatek,mt8195-audio";
989 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
992 reset-names = "audiosys";
1012 clock-names = "clk26m",
1035 compatible = "mediatek,mt8195-uart",
1036 "mediatek,mt6577-uart";
1040 clock-names = "baud", "bus";
1045 compatible = "mediatek,mt8195-uart",
1046 "mediatek,mt6577-uart";
1050 clock-names = "baud", "bus";
1055 compatible = "mediatek,mt8195-uart",
1056 "mediatek,mt6577-uart";
1060 clock-names = "baud", "bus";
1065 compatible = "mediatek,mt8195-uart",
1066 "mediatek,mt6577-uart";
1070 clock-names = "baud", "bus";
1075 compatible = "mediatek,mt8195-uart",
1076 "mediatek,mt6577-uart";
1080 clock-names = "baud", "bus";
1085 compatible = "mediatek,mt8195-uart",
1086 "mediatek,mt6577-uart";
1090 clock-names = "baud", "bus";
1095 compatible = "mediatek,mt8195-auxadc",
1096 "mediatek,mt8173-auxadc";
1099 clock-names = "main";
1100 #io-channel-cells = <1>;
1105 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1107 #clock-cells = <1>;
1111 compatible = "mediatek,mt8195-spi",
1112 "mediatek,mt6765-spi";
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1120 clock-names = "parent-clk", "sel-clk", "spi-clk";
1124 lvts_ap: thermal-sensor@1100b000 {
1125 compatible = "mediatek,mt8195-lvts-ap";
1130 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1131 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1132 #thermal-sensor-cells = <1>;
1136 compatible = "mediatek,mt8195-svs";
1140 clock-names = "main";
1141 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1142 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1144 reset-names = "svs_rst";
1148 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1152 #pwm-cells = <2>;
1155 clock-names = "main", "mm";
1160 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1163 #pwm-cells = <2>;
1166 clock-names = "main", "mm";
1171 compatible = "mediatek,mt8195-spi",
1172 "mediatek,mt6765-spi";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1180 clock-names = "parent-clk", "sel-clk", "spi-clk";
1185 compatible = "mediatek,mt8195-spi",
1186 "mediatek,mt6765-spi";
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1194 clock-names = "parent-clk", "sel-clk", "spi-clk";
1199 compatible = "mediatek,mt8195-spi",
1200 "mediatek,mt6765-spi";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1208 clock-names = "parent-clk", "sel-clk", "spi-clk";
1213 compatible = "mediatek,mt8195-spi",
1214 "mediatek,mt6765-spi";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1222 clock-names = "parent-clk", "sel-clk", "spi-clk";
1227 compatible = "mediatek,mt8195-spi",
1228 "mediatek,mt6765-spi";
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1236 clock-names = "parent-clk", "sel-clk", "spi-clk";
1241 compatible = "mediatek,mt8195-spi-slave";
1245 clock-names = "spi";
1246 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1247 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1252 compatible = "mediatek,mt8195-spi-slave";
1256 clock-names = "spi";
1257 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1258 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1263 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1266 interrupt-names = "macirq";
1267 clock-names = "axi",
1279 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1282 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1285 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1287 snps,axi-config = <&stmmac_axi_setup>;
1288 snps,mtl-rx-config = <&mtl_rx_setup>;
1289 snps,mtl-tx-config = <&mtl_tx_setup>;
1292 snps,clk-csr = <0>;
1296 compatible = "snps,dwmac-mdio";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1301 stmmac_axi_setup: stmmac-axi-config {
1307 mtl_rx_setup: rx-queues-config {
1308 snps,rx-queues-to-use = <4>;
1309 snps,rx-sched-sp;
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1315 snps,dcb-algorithm;
1316 snps,map-to-dma-channel = <0x0>;
1319 snps,dcb-algorithm;
1320 snps,map-to-dma-channel = <0x0>;
1323 snps,dcb-algorithm;
1324 snps,map-to-dma-channel = <0x0>;
1328 mtl_tx_setup: tx-queues-config {
1329 snps,tx-queues-to-use = <4>;
1330 snps,tx-sched-wrr;
1333 snps,dcb-algorithm;
1338 snps,dcb-algorithm;
1343 snps,dcb-algorithm;
1348 snps,dcb-algorithm;
1355 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1357 reg-names = "mac", "ippc";
1359 #address-cells = <2>;
1360 #size-cells = <2>;
1365 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1367 wakeup-source;
1368 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1372 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1374 reg-names = "mac";
1376 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1378 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1385 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1391 compatible = "mediatek,mt8195-mmc",
1392 "mediatek,mt8183-mmc";
1399 clock-names = "source", "hclk", "source_cg";
1404 compatible = "mediatek,mt8195-mmc",
1405 "mediatek,mt8183-mmc";
1412 clock-names = "source", "hclk", "source_cg";
1413 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1414 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1419 compatible = "mediatek,mt8195-mmc",
1420 "mediatek,mt8183-mmc";
1427 clock-names = "source", "hclk", "source_cg";
1428 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1429 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1433 lvts_mcu: thermal-sensor@11278000 {
1434 compatible = "mediatek,mt8195-lvts-mcu";
1439 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1440 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1441 #thermal-sensor-cells = <1>;
1445 compatible = "mediatek,mt8195-xhci",
1446 "mediatek,mtk-xhci";
1449 reg-names = "mac", "ippc";
1452 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1454 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1461 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1463 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1464 wakeup-source;
1469 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1471 reg-names = "mac", "ippc";
1473 #address-cells = <2>;
1474 #size-cells = <2>;
1476 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1477 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1481 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1483 wakeup-source;
1484 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1488 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1490 reg-names = "mac";
1492 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1493 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1495 clock-names = "sys_ck";
1501 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1503 reg-names = "mac", "ippc";
1505 #address-cells = <2>;
1506 #size-cells = <2>;
1508 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1509 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1513 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1515 wakeup-source;
1516 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1520 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1522 reg-names = "mac";
1524 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1525 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1527 clock-names = "sys_ck";
1533 compatible = "mediatek,mt8195-pcie",
1534 "mediatek,mt8192-pcie";
1536 #address-cells = <3>;
1537 #size-cells = <2>;
1539 reg-names = "pcie-mac";
1541 bus-range = <0x00 0xff>;
1547 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1548 iommu-map-mask = <0x0>;
1556 clock-names = "pl_250m", "tl_26m", "tl_96m",
1558 assigned-clocks = <&topckgen CLK_TOP_TL>;
1559 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1562 phy-names = "pcie-phy";
1564 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1567 reset-names = "mac";
1569 #interrupt-cells = <1>;
1570 interrupt-map-mask = <0 0 0 7>;
1571 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1577 pcie_intc0: interrupt-controller {
1578 interrupt-controller;
1579 #address-cells = <0>;
1580 #interrupt-cells = <1>;
1585 compatible = "mediatek,mt8195-pcie",
1586 "mediatek,mt8192-pcie";
1588 #address-cells = <3>;
1589 #size-cells = <2>;
1591 reg-names = "pcie-mac";
1593 bus-range = <0x00 0xff>;
1599 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1600 iommu-map-mask = <0x0>;
1609 clock-names = "pl_250m", "tl_26m", "tl_96m",
1611 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1612 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1615 phy-names = "pcie-phy";
1616 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1618 #interrupt-cells = <1>;
1619 interrupt-map-mask = <0 0 0 7>;
1620 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1626 pcie_intc1: interrupt-controller {
1627 interrupt-controller;
1628 #address-cells = <0>;
1629 #interrupt-cells = <1>;
1634 compatible = "mediatek,mt8195-nor",
1635 "mediatek,mt8173-nor";
1641 clock-names = "spi", "sf", "axi";
1642 #address-cells = <1>;
1643 #size-cells = <0>;
1648 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1650 #address-cells = <1>;
1651 #size-cells = <1>;
1652 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1656 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1660 u3_intr_p0: usb3-intr@185 {
1664 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1668 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1672 comb_intr_p1: usb3-intr@187 {
1676 u2_intr_p0: usb2-intr-p0@188,1 {
1680 u2_intr_p1: usb2-intr-p1@188,2 {
1684 u2_intr_p2: usb2-intr-p2@189,1 {
1688 u2_intr_p3: usb2-intr-p3@189,2 {
1692 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1696 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1700 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1704 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1708 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1712 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1716 pciephy_glb_intr: pciephy-glb-intr@193 {
1720 dp_calibration: dp-data@1ac {
1723 lvts_efuse_data1: lvts1-calib@1bc {
1726 lvts_efuse_data2: lvts2-calib@1d0 {
1729 svs_calib_data: svs-calib@580 {
1732 socinfo-data1@7a0 {
1737 u3phy2: t-phy@11c40000 {
1738 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1739 #address-cells = <1>;
1740 #size-cells = <1>;
1744 u2port2: usb-phy@0 {
1747 clock-names = "ref";
1748 #phy-cells = <1>;
1752 u3phy3: t-phy@11c50000 {
1753 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1754 #address-cells = <1>;
1755 #size-cells = <1>;
1759 u2port3: usb-phy@0 {
1762 clock-names = "ref";
1763 #phy-cells = <1>;
1767 mipi_tx0: dsi-phy@11c80000 {
1768 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1771 clock-output-names = "mipi_tx0_pll";
1772 #clock-cells = <0>;
1773 #phy-cells = <0>;
1777 mipi_tx1: dsi-phy@11c90000 {
1778 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1781 clock-output-names = "mipi_tx1_pll";
1782 #clock-cells = <0>;
1783 #phy-cells = <0>;
1788 compatible = "mediatek,mt8195-i2c",
1789 "mediatek,mt8192-i2c";
1793 clock-div = <1>;
1796 clock-names = "main", "dma";
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1803 compatible = "mediatek,mt8195-i2c",
1804 "mediatek,mt8192-i2c";
1808 clock-div = <1>;
1811 clock-names = "main", "dma";
1812 #address-cells = <1>;
1813 #size-cells = <0>;
1818 compatible = "mediatek,mt8195-i2c",
1819 "mediatek,mt8192-i2c";
1823 clock-div = <1>;
1826 clock-names = "main", "dma";
1827 #address-cells = <1>;
1828 #size-cells = <0>;
1832 imp_iic_wrap_s: clock-controller@11d03000 {
1833 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1835 #clock-cells = <1>;
1839 compatible = "mediatek,mt8195-i2c",
1840 "mediatek,mt8192-i2c";
1844 clock-div = <1>;
1847 clock-names = "main", "dma";
1848 #address-cells = <1>;
1849 #size-cells = <0>;
1854 compatible = "mediatek,mt8195-i2c",
1855 "mediatek,mt8192-i2c";
1859 clock-div = <1>;
1862 clock-names = "main", "dma";
1863 #address-cells = <1>;
1864 #size-cells = <0>;
1869 compatible = "mediatek,mt8195-i2c",
1870 "mediatek,mt8192-i2c";
1874 clock-div = <1>;
1877 clock-names = "main", "dma";
1878 #address-cells = <1>;
1879 #size-cells = <0>;
1884 compatible = "mediatek,mt8195-i2c",
1885 "mediatek,mt8192-i2c";
1889 clock-div = <1>;
1892 clock-names = "main", "dma";
1893 #address-cells = <1>;
1894 #size-cells = <0>;
1899 compatible = "mediatek,mt8195-i2c",
1900 "mediatek,mt8192-i2c";
1904 clock-div = <1>;
1907 clock-names = "main", "dma";
1908 #address-cells = <1>;
1909 #size-cells = <0>;
1913 imp_iic_wrap_w: clock-controller@11e05000 {
1914 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1916 #clock-cells = <1>;
1919 u3phy1: t-phy@11e30000 {
1920 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1921 #address-cells = <1>;
1922 #size-cells = <1>;
1924 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1927 u2port1: usb-phy@0 {
1931 clock-names = "ref", "da_ref";
1932 #phy-cells = <1>;
1935 u3port1: usb-phy@700 {
1939 clock-names = "ref", "da_ref";
1940 nvmem-cells = <&comb_intr_p1>,
1943 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1944 #phy-cells = <1>;
1948 u3phy0: t-phy@11e40000 {
1949 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1950 #address-cells = <1>;
1951 #size-cells = <1>;
1955 u2port0: usb-phy@0 {
1959 clock-names = "ref", "da_ref";
1960 #phy-cells = <1>;
1963 u3port0: usb-phy@700 {
1967 clock-names = "ref", "da_ref";
1968 nvmem-cells = <&u3_intr_p0>,
1971 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1972 #phy-cells = <1>;
1977 compatible = "mediatek,mt8195-pcie-phy";
1979 reg-names = "sif";
1980 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1984 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1988 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1989 #phy-cells = <0>;
1993 ufsphy: ufs-phy@11fa0000 {
1994 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1997 clock-names = "unipro", "mp";
1998 #phy-cells = <0>;
2003 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2004 "arm,mali-valhall-jm";
2011 interrupt-names = "job", "mmu", "gpu";
2012 operating-points-v2 = <&gpu_opp_table>;
2013 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2018 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2022 mfgcfg: clock-controller@13fbf000 {
2023 compatible = "mediatek,mt8195-mfgcfg";
2025 #clock-cells = <1>;
2029 compatible = "mediatek,mt8195-vppsys0", "syscon";
2031 #clock-cells = <1>;
2032 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2035 dma-controller@14001000 {
2036 compatible = "mediatek,mt8195-mdp3-rdma";
2038 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2039 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2042 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2050 #dma-cells = <1>;
2054 compatible = "mediatek,mt8195-mdp3-fg";
2056 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2061 compatible = "mediatek,mt8195-mdp3-stitch";
2063 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2068 compatible = "mediatek,mt8195-mdp3-hdr";
2070 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2075 compatible = "mediatek,mt8195-mdp3-aal";
2078 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2080 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2084 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2086 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2087 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2093 compatible = "mediatek,mt8195-mdp3-tdshp";
2095 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2100 compatible = "mediatek,mt8195-mdp3-color";
2103 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2105 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2109 compatible = "mediatek,mt8195-mdp3-ovl";
2112 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2114 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2119 compatible = "mediatek,mt8195-mdp3-padding";
2121 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2123 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2127 compatible = "mediatek,mt8195-mdp3-tcc";
2129 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2133 dma-controller@1400c000 {
2134 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2136 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2137 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2141 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2142 #dma-cells = <1>;
2146 compatible = "mediatek,mt8195-vpp-mutex";
2149 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2151 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2155 compatible = "mediatek,mt8195-smi-sub-common";
2160 clock-names = "apb", "smi", "gals0";
2162 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2166 compatible = "mediatek,mt8195-smi-sub-common";
2171 clock-names = "apb", "smi", "gals0";
2173 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2177 compatible = "mediatek,mt8195-smi-common-vpp";
2183 clock-names = "apb", "smi", "gals0", "gals1";
2184 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2188 compatible = "mediatek,mt8195-smi-larb";
2190 mediatek,larb-id = <4>;
2194 clock-names = "apb", "smi";
2195 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2199 compatible = "mediatek,mt8195-iommu-vpp";
2207 clock-names = "bclk";
2208 #iommu-cells = <1>;
2209 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2212 wpesys: clock-controller@14e00000 {
2213 compatible = "mediatek,mt8195-wpesys";
2215 #clock-cells = <1>;
2218 wpesys_vpp0: clock-controller@14e02000 {
2219 compatible = "mediatek,mt8195-wpesys_vpp0";
2221 #clock-cells = <1>;
2224 wpesys_vpp1: clock-controller@14e03000 {
2225 compatible = "mediatek,mt8195-wpesys_vpp1";
2227 #clock-cells = <1>;
2231 compatible = "mediatek,mt8195-smi-larb";
2233 mediatek,larb-id = <7>;
2237 clock-names = "apb", "smi";
2238 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2242 compatible = "mediatek,mt8195-smi-larb";
2244 mediatek,larb-id = <8>;
2249 clock-names = "apb", "smi", "gals";
2250 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2254 compatible = "mediatek,mt8195-vppsys1", "syscon";
2256 #clock-cells = <1>;
2257 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2261 compatible = "mediatek,mt8195-vpp-mutex";
2264 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2266 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2270 compatible = "mediatek,mt8195-smi-larb";
2272 mediatek,larb-id = <5>;
2277 clock-names = "apb", "smi", "gals";
2278 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2282 compatible = "mediatek,mt8195-smi-larb";
2284 mediatek,larb-id = <6>;
2289 clock-names = "apb", "smi", "gals";
2290 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2294 compatible = "mediatek,mt8195-mdp3-split";
2296 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2300 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2304 compatible = "mediatek,mt8195-mdp3-tcc";
2306 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2310 dma-controller@14f08000 {
2311 compatible = "mediatek,mt8195-mdp3-rdma";
2313 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2314 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2318 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2319 #dma-cells = <1>;
2322 dma-controller@14f09000 {
2323 compatible = "mediatek,mt8195-mdp3-rdma";
2325 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2326 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2330 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2331 #dma-cells = <1>;
2334 dma-controller@14f0a000 {
2335 compatible = "mediatek,mt8195-mdp3-rdma";
2337 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2338 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2342 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2343 #dma-cells = <1>;
2347 compatible = "mediatek,mt8195-mdp3-fg";
2349 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2354 compatible = "mediatek,mt8195-mdp3-fg";
2356 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2361 compatible = "mediatek,mt8195-mdp3-fg";
2363 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2368 compatible = "mediatek,mt8195-mdp3-hdr";
2370 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2375 compatible = "mediatek,mt8195-mdp3-hdr";
2377 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2382 compatible = "mediatek,mt8195-mdp3-hdr";
2384 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2389 compatible = "mediatek,mt8195-mdp3-aal";
2392 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2394 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2398 compatible = "mediatek,mt8195-mdp3-aal";
2401 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2403 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2407 compatible = "mediatek,mt8195-mdp3-aal";
2410 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2412 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2416 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2418 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2419 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2425 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2427 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2428 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2434 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2436 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2437 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2443 compatible = "mediatek,mt8195-mdp3-tdshp";
2445 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2450 compatible = "mediatek,mt8195-mdp3-tdshp";
2452 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2457 compatible = "mediatek,mt8195-mdp3-tdshp";
2459 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2464 compatible = "mediatek,mt8195-mdp3-merge";
2466 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2468 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2472 compatible = "mediatek,mt8195-mdp3-merge";
2474 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2476 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2480 compatible = "mediatek,mt8195-mdp3-color";
2483 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2485 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2489 compatible = "mediatek,mt8195-mdp3-color";
2491 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2494 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2498 compatible = "mediatek,mt8195-mdp3-color";
2501 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2503 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2507 compatible = "mediatek,mt8195-mdp3-ovl";
2510 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2512 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2517 compatible = "mediatek,mt8195-mdp3-padding";
2519 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2521 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2525 compatible = "mediatek,mt8195-mdp3-padding";
2527 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2529 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2533 compatible = "mediatek,mt8195-mdp3-padding";
2535 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2537 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2540 dma-controller@14f23000 {
2541 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2543 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2544 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2548 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2549 #dma-cells = <1>;
2552 dma-controller@14f24000 {
2553 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2555 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2556 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2560 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2561 #dma-cells = <1>;
2564 dma-controller@14f25000 {
2565 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2567 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2568 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2572 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2573 #dma-cells = <1>;
2576 imgsys: clock-controller@15000000 {
2577 compatible = "mediatek,mt8195-imgsys";
2579 #clock-cells = <1>;
2583 compatible = "mediatek,mt8195-smi-larb";
2585 mediatek,larb-id = <9>;
2590 clock-names = "apb", "smi", "gals";
2591 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2595 compatible = "mediatek,mt8195-smi-sub-common";
2600 clock-names = "apb", "smi", "gals0";
2602 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2606 compatible = "mediatek,mt8195-smi-sub-common";
2611 clock-names = "apb", "smi", "gals0";
2613 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2616 imgsys1_dip_top: clock-controller@15110000 {
2617 compatible = "mediatek,mt8195-imgsys1_dip_top";
2619 #clock-cells = <1>;
2623 compatible = "mediatek,mt8195-smi-larb";
2625 mediatek,larb-id = <10>;
2629 clock-names = "apb", "smi";
2630 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2633 imgsys1_dip_nr: clock-controller@15130000 {
2634 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2636 #clock-cells = <1>;
2639 imgsys1_wpe: clock-controller@15220000 {
2640 compatible = "mediatek,mt8195-imgsys1_wpe";
2642 #clock-cells = <1>;
2646 compatible = "mediatek,mt8195-smi-larb";
2648 mediatek,larb-id = <11>;
2652 clock-names = "apb", "smi";
2653 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2656 ipesys: clock-controller@15330000 {
2657 compatible = "mediatek,mt8195-ipesys";
2659 #clock-cells = <1>;
2663 compatible = "mediatek,mt8195-smi-larb";
2665 mediatek,larb-id = <12>;
2669 clock-names = "apb", "smi";
2670 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2673 camsys: clock-controller@16000000 {
2674 compatible = "mediatek,mt8195-camsys";
2676 #clock-cells = <1>;
2680 compatible = "mediatek,mt8195-smi-larb";
2682 mediatek,larb-id = <13>;
2687 clock-names = "apb", "smi", "gals";
2688 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2692 compatible = "mediatek,mt8195-smi-larb";
2694 mediatek,larb-id = <14>;
2698 clock-names = "apb", "smi";
2699 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2703 compatible = "mediatek,mt8195-smi-sub-common";
2708 clock-names = "apb", "smi", "gals0";
2710 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2714 compatible = "mediatek,mt8195-smi-sub-common";
2719 clock-names = "apb", "smi", "gals0";
2721 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2725 compatible = "mediatek,mt8195-smi-larb";
2727 mediatek,larb-id = <16>;
2731 clock-names = "apb", "smi";
2732 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2736 compatible = "mediatek,mt8195-smi-larb";
2738 mediatek,larb-id = <17>;
2742 clock-names = "apb", "smi";
2743 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2747 compatible = "mediatek,mt8195-smi-larb";
2749 mediatek,larb-id = <27>;
2753 clock-names = "apb", "smi";
2754 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2758 compatible = "mediatek,mt8195-smi-larb";
2760 mediatek,larb-id = <28>;
2764 clock-names = "apb", "smi";
2765 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2768 camsys_rawa: clock-controller@1604f000 {
2769 compatible = "mediatek,mt8195-camsys_rawa";
2771 #clock-cells = <1>;
2774 camsys_yuva: clock-controller@1606f000 {
2775 compatible = "mediatek,mt8195-camsys_yuva";
2777 #clock-cells = <1>;
2780 camsys_rawb: clock-controller@1608f000 {
2781 compatible = "mediatek,mt8195-camsys_rawb";
2783 #clock-cells = <1>;
2786 camsys_yuvb: clock-controller@160af000 {
2787 compatible = "mediatek,mt8195-camsys_yuvb";
2789 #clock-cells = <1>;
2792 camsys_mraw: clock-controller@16140000 {
2793 compatible = "mediatek,mt8195-camsys_mraw";
2795 #clock-cells = <1>;
2799 compatible = "mediatek,mt8195-smi-larb";
2801 mediatek,larb-id = <25>;
2806 clock-names = "apb", "smi", "gals";
2807 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2811 compatible = "mediatek,mt8195-smi-larb";
2813 mediatek,larb-id = <26>;
2817 clock-names = "apb", "smi";
2818 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2822 ccusys: clock-controller@17200000 {
2823 compatible = "mediatek,mt8195-ccusys";
2825 #clock-cells = <1>;
2829 compatible = "mediatek,mt8195-smi-larb";
2831 mediatek,larb-id = <18>;
2835 clock-names = "apb", "smi";
2836 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2839 video-codec@18000000 {
2840 compatible = "mediatek,mt8195-vcodec-dec";
2843 #address-cells = <2>;
2844 #size-cells = <2>;
2849 video-codec@2000 {
2850 compatible = "mediatek,mtk-vcodec-lat-soc";
2858 clock-names = "sel", "vdec", "lat", "top";
2859 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2860 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2861 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2864 video-codec@10000 {
2865 compatible = "mediatek,mtk-vcodec-lat";
2878 clock-names = "sel", "vdec", "lat", "top";
2879 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2880 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2881 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2884 video-codec@25000 {
2885 compatible = "mediatek,mtk-vcodec-core";
2902 clock-names = "sel", "vdec", "lat", "top";
2903 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2904 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2905 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2910 compatible = "mediatek,mt8195-smi-larb";
2912 mediatek,larb-id = <24>;
2916 clock-names = "apb", "smi";
2917 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2921 compatible = "mediatek,mt8195-smi-larb";
2923 mediatek,larb-id = <23>;
2927 clock-names = "apb", "smi";
2928 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2931 vdecsys_soc: clock-controller@1800f000 {
2932 compatible = "mediatek,mt8195-vdecsys_soc";
2934 #clock-cells = <1>;
2938 compatible = "mediatek,mt8195-smi-larb";
2940 mediatek,larb-id = <21>;
2944 clock-names = "apb", "smi";
2945 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2948 vdecsys: clock-controller@1802f000 {
2949 compatible = "mediatek,mt8195-vdecsys";
2951 #clock-cells = <1>;
2955 compatible = "mediatek,mt8195-smi-larb";
2957 mediatek,larb-id = <22>;
2961 clock-names = "apb", "smi";
2962 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2965 vdecsys_core1: clock-controller@1803f000 {
2966 compatible = "mediatek,mt8195-vdecsys_core1";
2968 #clock-cells = <1>;
2971 apusys_pll: clock-controller@190f3000 {
2972 compatible = "mediatek,mt8195-apusys_pll";
2974 #clock-cells = <1>;
2977 vencsys: clock-controller@1a000000 {
2978 compatible = "mediatek,mt8195-vencsys";
2980 #clock-cells = <1>;
2984 compatible = "mediatek,mt8195-smi-larb";
2986 mediatek,larb-id = <19>;
2990 clock-names = "apb", "smi";
2991 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2994 venc: video-codec@1a020000 {
2995 compatible = "mediatek,mt8195-vcodec-enc";
3009 clock-names = "venc_sel";
3010 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3011 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3012 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3013 #address-cells = <2>;
3014 #size-cells = <2>;
3017 jpgdec-master {
3018 compatible = "mediatek,mt8195-jpgdec";
3019 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3026 #address-cells = <2>;
3027 #size-cells = <2>;
3031 compatible = "mediatek,mt8195-jpgdec-hw";
3041 clock-names = "jpgdec";
3042 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3046 compatible = "mediatek,mt8195-jpgdec-hw";
3056 clock-names = "jpgdec";
3057 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3061 compatible = "mediatek,mt8195-jpgdec-hw";
3071 clock-names = "jpgdec";
3072 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3076 vencsys_core1: clock-controller@1b000000 {
3077 compatible = "mediatek,mt8195-vencsys_core1";
3079 #clock-cells = <1>;
3083 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3086 #clock-cells = <1>;
3087 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3091 jpgenc-master {
3092 compatible = "mediatek,mt8195-jpgenc";
3093 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3098 #address-cells = <2>;
3099 #size-cells = <2>;
3103 compatible = "mediatek,mt8195-jpgenc-hw";
3111 clock-names = "jpgenc";
3112 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3116 compatible = "mediatek,mt8195-jpgenc-hw";
3124 clock-names = "jpgenc";
3125 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3130 compatible = "mediatek,mt8195-smi-larb";
3132 mediatek,larb-id = <20>;
3137 clock-names = "apb", "smi", "gals";
3138 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3142 compatible = "mediatek,mt8195-disp-ovl";
3145 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3148 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3151 #address-cells = <1>;
3152 #size-cells = <0>;
3162 remote-endpoint = <&rdma0_in>;
3169 compatible = "mediatek,mt8195-disp-rdma";
3172 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3175 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3178 #address-cells = <1>;
3179 #size-cells = <0>;
3184 remote-endpoint = <&ovl0_out>;
3191 remote-endpoint = <&color0_in>;
3198 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3201 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3203 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3206 #address-cells = <1>;
3207 #size-cells = <0>;
3212 remote-endpoint = <&rdma0_out>;
3219 remote-endpoint = <&ccorr0_in>;
3226 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3229 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3231 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3234 #address-cells = <1>;
3235 #size-cells = <0>;
3240 remote-endpoint = <&color0_out>;
3247 remote-endpoint = <&aal0_in>;
3254 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3257 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3259 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3262 #address-cells = <1>;
3263 #size-cells = <0>;
3268 remote-endpoint = <&ccorr0_out>;
3275 remote-endpoint = <&gamma0_in>;
3282 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3285 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3287 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3290 #address-cells = <1>;
3291 #size-cells = <0>;
3296 remote-endpoint = <&aal0_out>;
3303 remote-endpoint = <&dither0_in>;
3310 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3313 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3315 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3318 #address-cells = <1>;
3319 #size-cells = <0>;
3324 remote-endpoint = <&gamma0_out>;
3336 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3339 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3343 clock-names = "engine", "digital", "hs";
3345 phy-names = "dphy";
3350 compatible = "mediatek,mt8195-disp-dsc";
3353 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3355 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3359 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3362 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3366 clock-names = "engine", "digital", "hs";
3368 phy-names = "dphy";
3373 compatible = "mediatek,mt8195-disp-merge";
3376 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3378 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3381 dp_intf0: dp-intf@1c015000 {
3382 compatible = "mediatek,mt8195-dp-intf";
3385 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3389 clock-names = "pixel", "engine", "pll";
3394 compatible = "mediatek,mt8195-disp-mutex";
3397 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3399 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3400 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3404 compatible = "mediatek,mt8195-smi-larb";
3406 mediatek,larb-id = <0>;
3411 clock-names = "apb", "smi", "gals";
3412 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3416 compatible = "mediatek,mt8195-smi-larb";
3418 mediatek,larb-id = <1>;
3423 clock-names = "apb", "smi", "gals";
3424 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3428 compatible = "mediatek,mt8195-vdosys1", "syscon";
3431 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3432 #clock-cells = <1>;
3433 #reset-cells = <1>;
3437 compatible = "mediatek,mt8195-smi-common-vdo";
3443 clock-names = "apb", "smi", "gals0", "gals1";
3444 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3449 compatible = "mediatek,mt8195-iommu-vdo";
3456 #iommu-cells = <1>;
3458 clock-names = "bclk";
3459 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3463 compatible = "mediatek,mt8195-disp-mutex";
3466 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3468 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3469 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3473 compatible = "mediatek,mt8195-smi-larb";
3475 mediatek,larb-id = <2>;
3480 clock-names = "apb", "smi", "gals";
3481 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3485 compatible = "mediatek,mt8195-smi-larb";
3487 mediatek,larb-id = <3>;
3492 clock-names = "apb", "smi", "gals";
3493 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3496 vdo1_rdma0: dma-controller@1c104000 {
3497 compatible = "mediatek,mt8195-vdo1-rdma";
3501 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3503 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3504 #dma-cells = <1>;
3507 vdo1_rdma1: dma-controller@1c105000 {
3508 compatible = "mediatek,mt8195-vdo1-rdma";
3512 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3514 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3515 #dma-cells = <1>;
3518 vdo1_rdma2: dma-controller@1c106000 {
3519 compatible = "mediatek,mt8195-vdo1-rdma";
3523 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3525 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3526 #dma-cells = <1>;
3529 vdo1_rdma3: dma-controller@1c107000 {
3530 compatible = "mediatek,mt8195-vdo1-rdma";
3534 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3536 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3537 #dma-cells = <1>;
3540 vdo1_rdma4: dma-controller@1c108000 {
3541 compatible = "mediatek,mt8195-vdo1-rdma";
3545 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3547 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3548 #dma-cells = <1>;
3551 vdo1_rdma5: dma-controller@1c109000 {
3552 compatible = "mediatek,mt8195-vdo1-rdma";
3556 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3558 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3559 #dma-cells = <1>;
3562 vdo1_rdma6: dma-controller@1c10a000 {
3563 compatible = "mediatek,mt8195-vdo1-rdma";
3567 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3569 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3570 #dma-cells = <1>;
3573 vdo1_rdma7: dma-controller@1c10b000 {
3574 compatible = "mediatek,mt8195-vdo1-rdma";
3578 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3580 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3581 #dma-cells = <1>;
3584 merge1: vpp-merge@1c10c000 {
3585 compatible = "mediatek,mt8195-disp-merge";
3590 clock-names = "merge","merge_async";
3591 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3592 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3593 mediatek,merge-mute;
3597 merge2: vpp-merge@1c10d000 {
3598 compatible = "mediatek,mt8195-disp-merge";
3603 clock-names = "merge","merge_async";
3604 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3605 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3606 mediatek,merge-mute;
3610 merge3: vpp-merge@1c10e000 {
3611 compatible = "mediatek,mt8195-disp-merge";
3616 clock-names = "merge","merge_async";
3617 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3618 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3619 mediatek,merge-mute;
3623 merge4: vpp-merge@1c10f000 {
3624 compatible = "mediatek,mt8195-disp-merge";
3629 clock-names = "merge","merge_async";
3630 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3631 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3632 mediatek,merge-mute;
3636 merge5: vpp-merge@1c110000 {
3637 compatible = "mediatek,mt8195-disp-merge";
3642 clock-names = "merge","merge_async";
3643 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3644 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3645 mediatek,merge-fifo-en;
3649 dp_intf1: dp-intf@1c113000 {
3650 compatible = "mediatek,mt8195-dp-intf";
3653 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3657 clock-names = "pixel", "engine", "pll";
3661 ethdr0: hdr-engine@1c114000 {
3662 compatible = "mediatek,mt8195-disp-ethdr";
3670 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3672 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3692 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3696 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3699 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
3705 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3709 edp_tx: edp-tx@1c500000 {
3710 compatible = "mediatek,mt8195-edp-tx";
3712 nvmem-cells = <&dp_calibration>;
3713 nvmem-cell-names = "dp_calibration_data";
3714 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3716 max-linkrate-mhz = <8100>;
3720 dp_tx: dp-tx@1c600000 {
3721 compatible = "mediatek,mt8195-dp-tx";
3723 nvmem-cells = <&dp_calibration>;
3724 nvmem-cell-names = "dp_calibration_data";
3725 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3727 max-linkrate-mhz = <8100>;
3732 thermal_zones: thermal-zones {
3733 cpu0-thermal {
3734 polling-delay = <1000>;
3735 polling-delay-passive = <250>;
3736 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3739 cpu0_alert: trip-alert {
3745 cpu0_crit: trip-crit {
3752 cooling-maps {
3755 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3763 cpu1-thermal {
3764 polling-delay = <1000>;
3765 polling-delay-passive = <250>;
3766 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3769 cpu1_alert: trip-alert {
3775 cpu1_crit: trip-crit {
3782 cooling-maps {
3785 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3793 cpu2-thermal {
3794 polling-delay = <1000>;
3795 polling-delay-passive = <250>;
3796 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3799 cpu2_alert: trip-alert {
3805 cpu2_crit: trip-crit {
3812 cooling-maps {
3815 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3823 cpu3-thermal {
3824 polling-delay = <1000>;
3825 polling-delay-passive = <250>;
3826 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3829 cpu3_alert: trip-alert {
3835 cpu3_crit: trip-crit {
3842 cooling-maps {
3845 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3853 cpu4-thermal {
3854 polling-delay = <1000>;
3855 polling-delay-passive = <250>;
3856 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3859 cpu4_alert: trip-alert {
3865 cpu4_crit: trip-crit {
3872 cooling-maps {
3875 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3883 cpu5-thermal {
3884 polling-delay = <1000>;
3885 polling-delay-passive = <250>;
3886 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3889 cpu5_alert: trip-alert {
3895 cpu5_crit: trip-crit {
3902 cooling-maps {
3905 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3913 cpu6-thermal {
3914 polling-delay = <1000>;
3915 polling-delay-passive = <250>;
3916 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3919 cpu6_alert: trip-alert {
3925 cpu6_crit: trip-crit {
3932 cooling-maps {
3935 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3943 cpu7-thermal {
3944 polling-delay = <1000>;
3945 polling-delay-passive = <250>;
3946 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3949 cpu7_alert: trip-alert {
3955 cpu7_crit: trip-crit {
3962 cooling-maps {
3965 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3973 vpu0-thermal {
3974 polling-delay = <1000>;
3975 polling-delay-passive = <250>;
3976 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3979 vpu0_alert: trip-alert {
3985 vpu0_crit: trip-crit {
3993 vpu1-thermal {
3994 polling-delay = <1000>;
3995 polling-delay-passive = <250>;
3996 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3999 vpu1_alert: trip-alert {
4005 vpu1_crit: trip-crit {
4013 gpu-thermal {
4014 polling-delay = <1000>;
4015 polling-delay-passive = <250>;
4016 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
4019 gpu0_alert: trip-alert {
4025 gpu0_crit: trip-crit {
4033 gpu1-thermal {
4034 polling-delay = <1000>;
4035 polling-delay-passive = <250>;
4036 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
4039 gpu1_alert: trip-alert {
4045 gpu1_crit: trip-crit {
4053 vdec-thermal {
4054 polling-delay = <1000>;
4055 polling-delay-passive = <250>;
4056 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
4059 vdec_alert: trip-alert {
4065 vdec_crit: trip-crit {
4073 img-thermal {
4074 polling-delay = <1000>;
4075 polling-delay-passive = <250>;
4076 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
4079 img_alert: trip-alert {
4085 img_crit: trip-crit {
4093 infra-thermal {
4094 polling-delay = <1000>;
4095 polling-delay-passive = <250>;
4096 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
4099 infra_alert: trip-alert {
4105 infra_crit: trip-crit {
4113 cam0-thermal {
4114 polling-delay = <1000>;
4115 polling-delay-passive = <250>;
4116 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
4119 cam0_alert: trip-alert {
4125 cam0_crit: trip-crit {
4133 cam1-thermal {
4134 polling-delay = <1000>;
4135 polling-delay-passive = <250>;
4136 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
4139 cam1_alert: trip-alert {
4145 cam1_crit: trip-crit {