Lines Matching +full:mt8183 +full:- +full:mdp3 +full:- +full:rdma
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
623 clock-names = "vdec1-0";
625 #power-domain-cells = <0>;
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
631 clock-names = "venc1-larb";
633 #power-domain-cells = <0>;
636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 "vdosys0-2", "vdosys0-3",
647 "vdosys0-4", "vdosys0-5";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 #power-domain-cells = <1>;
653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
658 clock-names = "vppsys1", "vppsys1-0",
659 "vppsys1-1";
661 #power-domain-cells = <0>;
664 power-domain@MT8195_POWER_DOMAIN_WPESYS {
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 "wepsys-3";
673 #power-domain-cells = <0>;
676 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
679 clock-names = "vdec0-0";
681 #power-domain-cells = <0>;
684 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
687 clock-names = "vdec2-0";
689 #power-domain-cells = <0>;
692 power-domain@MT8195_POWER_DOMAIN_VENC {
695 clock-names = "venc0-larb";
697 #power-domain-cells = <0>;
700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 #power-domain-cells = <1>;
713 power-domain@MT8195_POWER_DOMAIN_DP_TX {
716 #power-domain-cells = <0>;
719 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
722 #power-domain-cells = <0>;
725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
728 clock-names = "hdmi_tx";
729 #power-domain-cells = <0>;
733 power-domain@MT8195_POWER_DOMAIN_IMG {
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 #power-domain-cells = <1>;
743 power-domain@MT8195_POWER_DOMAIN_DIP {
745 #power-domain-cells = <0>;
748 power-domain@MT8195_POWER_DOMAIN_IPE {
753 clock-names = "ipe", "ipe-0", "ipe-1";
755 #power-domain-cells = <0>;
759 power-domain@MT8195_POWER_DOMAIN_CAM {
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 "cam-4";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <1>;
773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
775 #power-domain-cells = <0>;
778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
780 #power-domain-cells = <0>;
783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
785 #power-domain-cells = <0>;
791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
794 #power-domain-cells = <0>;
797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
800 #power-domain-cells = <0>;
803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
805 #power-domain-cells = <0>;
808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
810 #power-domain-cells = <0>;
813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
817 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power-domain-cells = <0>;
821 power-domain@MT8195_POWER_DOMAIN_ETHER {
824 clock-names = "ether";
825 #power-domain-cells = <0>;
828 power-domain@MT8195_POWER_DOMAIN_ADSP {
832 clock-names = "adsp", "adsp1";
833 #address-cells = <1>;
834 #size-cells = <0>;
836 #power-domain-cells = <1>;
838 power-domain@MT8195_POWER_DOMAIN_AUDIO {
844 clock-names = "audio", "audio1", "audio2",
847 #power-domain-cells = <0>;
854 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrst;
857 #reset-cells = <1>;
861 compatible = "mediatek,mt8195-apmixedsys", "syscon";
863 #clock-cells = <1>;
867 compatible = "mediatek,mt8195-timer",
868 "mediatek,mt6765-timer";
875 compatible = "mediatek,mt8195-pwrap", "syscon";
877 reg-names = "pwrap";
881 clock-names = "spi", "wrap";
882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
887 compatible = "mediatek,mt8195-spmi";
890 reg-names = "pmif", "spmimst";
894 clock-names = "pmif_sys_ck",
897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
901 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek,mt8195-iommu-infra";
909 #iommu-cells = <1>;
913 compatible = "mediatek,mt8195-gce";
916 #mbox-cells = <2>;
921 compatible = "mediatek,mt8195-gce";
924 #mbox-cells = <2>;
929 compatible = "mediatek,mt8195-scp";
933 reg-names = "sram", "cfg", "l1tcm";
938 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek,mt8195-scp_adsp";
941 #clock-cells = <1>;
945 compatible = "mediatek,mt8195-dsp";
948 reg-names = "cfg", "sram";
955 clock-names = "adsp_sel",
961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx";
968 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>;
975 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>;
981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek,mt8195-audio";
985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
988 reset-names = "audiosys";
1008 clock-names = "clk26m",
1031 compatible = "mediatek,mt8195-uart",
1032 "mediatek,mt6577-uart";
1036 clock-names = "baud", "bus";
1041 compatible = "mediatek,mt8195-uart",
1042 "mediatek,mt6577-uart";
1046 clock-names = "baud", "bus";
1051 compatible = "mediatek,mt8195-uart",
1052 "mediatek,mt6577-uart";
1056 clock-names = "baud", "bus";
1061 compatible = "mediatek,mt8195-uart",
1062 "mediatek,mt6577-uart";
1066 clock-names = "baud", "bus";
1071 compatible = "mediatek,mt8195-uart",
1072 "mediatek,mt6577-uart";
1076 clock-names = "baud", "bus";
1081 compatible = "mediatek,mt8195-uart",
1082 "mediatek,mt6577-uart";
1086 clock-names = "baud", "bus";
1091 compatible = "mediatek,mt8195-auxadc",
1092 "mediatek,mt8173-auxadc";
1095 clock-names = "main";
1096 #io-channel-cells = <1>;
1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1103 #clock-cells = <1>;
1107 compatible = "mediatek,mt8195-spi",
1108 "mediatek,mt6765-spi";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1116 clock-names = "parent-clk", "sel-clk", "spi-clk";
1120 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediatek,mt8195-lvts-ap";
1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1132 compatible = "mediatek,mt8195-svs";
1136 clock-names = "main";
1137 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1138 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1140 reset-names = "svs_rst";
1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1147 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148 #pwm-cells = <2>;
1151 clock-names = "main", "mm";
1156 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1159 #pwm-cells = <2>;
1162 clock-names = "main", "mm";
1167 compatible = "mediatek,mt8195-spi",
1168 "mediatek,mt6765-spi";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1176 clock-names = "parent-clk", "sel-clk", "spi-clk";
1181 compatible = "mediatek,mt8195-spi",
1182 "mediatek,mt6765-spi";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1190 clock-names = "parent-clk", "sel-clk", "spi-clk";
1195 compatible = "mediatek,mt8195-spi",
1196 "mediatek,mt6765-spi";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1204 clock-names = "parent-clk", "sel-clk", "spi-clk";
1209 compatible = "mediatek,mt8195-spi",
1210 "mediatek,mt6765-spi";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1218 clock-names = "parent-clk", "sel-clk", "spi-clk";
1223 compatible = "mediatek,mt8195-spi",
1224 "mediatek,mt6765-spi";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1232 clock-names = "parent-clk", "sel-clk", "spi-clk";
1237 compatible = "mediatek,mt8195-spi-slave";
1241 clock-names = "spi";
1242 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1248 compatible = "mediatek,mt8195-spi-slave";
1252 clock-names = "spi";
1253 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1259 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1262 interrupt-names = "macirq";
1263 clock-names = "axi",
1275 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1278 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1281 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1283 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = <&mtl_tx_setup>;
1288 snps,clk-csr = <0>;
1292 compatible = "snps,dwmac-mdio";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1297 stmmac_axi_setup: stmmac-axi-config {
1303 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched-sp;
1307 snps,dcb-algorithm;
1308 snps,map-to-dma-channel = <0x0>;
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1315 snps,dcb-algorithm;
1316 snps,map-to-dma-channel = <0x0>;
1319 snps,dcb-algorithm;
1320 snps,map-to-dma-channel = <0x0>;
1324 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched-wrr;
1329 snps,dcb-algorithm;
1334 snps,dcb-algorithm;
1339 snps,dcb-algorithm;
1344 snps,dcb-algorithm;
1351 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1353 reg-names = "mac", "ippc";
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1361 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1363 wakeup-source;
1364 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1368 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1370 reg-names = "mac";
1372 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1374 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1381 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1387 compatible = "mediatek,mt8195-mmc",
1388 "mediatek,mt8183-mmc";
1395 clock-names = "source", "hclk", "source_cg";
1400 compatible = "mediatek,mt8195-mmc",
1401 "mediatek,mt8183-mmc";
1408 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1415 compatible = "mediatek,mt8195-mmc",
1416 "mediatek,mt8183-mmc";
1423 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1429 lvts_mcu: thermal-sensor@11278000 {
1430 compatible = "mediatek,mt8195-lvts-mcu";
1435 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1436 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1437 #thermal-sensor-cells = <1>;
1441 compatible = "mediatek,mt8195-xhci",
1442 "mediatek,mtk-xhci";
1445 reg-names = "mac", "ippc";
1448 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1457 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1459 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source;
1465 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1467 reg-names = "mac", "ippc";
1469 #address-cells = <2>;
1470 #size-cells = <2>;
1472 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1473 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1477 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1479 wakeup-source;
1480 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1484 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1486 reg-names = "mac";
1488 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1489 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1491 clock-names = "sys_ck";
1497 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1499 reg-names = "mac", "ippc";
1501 #address-cells = <2>;
1502 #size-cells = <2>;
1504 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1505 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1509 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1511 wakeup-source;
1512 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1516 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1518 reg-names = "mac";
1520 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1521 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1523 clock-names = "sys_ck";
1529 compatible = "mediatek,mt8195-pcie",
1530 "mediatek,mt8192-pcie";
1532 #address-cells = <3>;
1533 #size-cells = <2>;
1535 reg-names = "pcie-mac";
1537 bus-range = <0x00 0xff>;
1543 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1544 iommu-map-mask = <0x0>;
1552 clock-names = "pl_250m", "tl_26m", "tl_96m",
1554 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1558 phy-names = "pcie-phy";
1560 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1563 reset-names = "mac";
1565 #interrupt-cells = <1>;
1566 interrupt-map-mask = <0 0 0 7>;
1567 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1573 pcie_intc0: interrupt-controller {
1574 interrupt-controller;
1575 #address-cells = <0>;
1576 #interrupt-cells = <1>;
1581 compatible = "mediatek,mt8195-pcie",
1582 "mediatek,mt8192-pcie";
1584 #address-cells = <3>;
1585 #size-cells = <2>;
1587 reg-names = "pcie-mac";
1589 bus-range = <0x00 0xff>;
1595 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1596 iommu-map-mask = <0x0>;
1605 clock-names = "pl_250m", "tl_26m", "tl_96m",
1607 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1611 phy-names = "pcie-phy";
1612 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1615 reset-names = "mac";
1617 #interrupt-cells = <1>;
1618 interrupt-map-mask = <0 0 0 7>;
1619 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1625 pcie_intc1: interrupt-controller {
1626 interrupt-controller;
1627 #address-cells = <0>;
1628 #interrupt-cells = <1>;
1633 compatible = "mediatek,mt8195-nor",
1634 "mediatek,mt8173-nor";
1640 clock-names = "spi", "sf", "axi";
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1647 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1649 #address-cells = <1>;
1650 #size-cells = <1>;
1651 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1655 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1659 u3_intr_p0: usb3-intr@185 {
1663 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1667 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1671 comb_intr_p1: usb3-intr@187 {
1675 u2_intr_p0: usb2-intr-p0@188,1 {
1679 u2_intr_p1: usb2-intr-p1@188,2 {
1683 u2_intr_p2: usb2-intr-p2@189,1 {
1687 u2_intr_p3: usb2-intr-p3@189,2 {
1691 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1695 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1699 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1703 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1707 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1711 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1715 pciephy_glb_intr: pciephy-glb-intr@193 {
1719 dp_calibration: dp-data@1ac {
1722 lvts_efuse_data1: lvts1-calib@1bc {
1725 lvts_efuse_data2: lvts2-calib@1d0 {
1728 svs_calib_data: svs-calib@580 {
1731 socinfo-data1@7a0 {
1736 u3phy2: t-phy@11c40000 {
1737 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1738 #address-cells = <1>;
1739 #size-cells = <1>;
1743 u2port2: usb-phy@0 {
1746 clock-names = "ref";
1747 #phy-cells = <1>;
1751 u3phy3: t-phy@11c50000 {
1752 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1753 #address-cells = <1>;
1754 #size-cells = <1>;
1758 u2port3: usb-phy@0 {
1761 clock-names = "ref";
1762 #phy-cells = <1>;
1766 mipi_tx0: dsi-phy@11c80000 {
1767 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1770 clock-output-names = "mipi_tx0_pll";
1771 #clock-cells = <0>;
1772 #phy-cells = <0>;
1776 mipi_tx1: dsi-phy@11c90000 {
1777 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1780 clock-output-names = "mipi_tx1_pll";
1781 #clock-cells = <0>;
1782 #phy-cells = <0>;
1787 compatible = "mediatek,mt8195-i2c",
1788 "mediatek,mt8192-i2c";
1792 clock-div = <1>;
1795 clock-names = "main", "dma";
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1802 compatible = "mediatek,mt8195-i2c",
1803 "mediatek,mt8192-i2c";
1807 clock-div = <1>;
1810 clock-names = "main", "dma";
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1817 compatible = "mediatek,mt8195-i2c",
1818 "mediatek,mt8192-i2c";
1822 clock-div = <1>;
1825 clock-names = "main", "dma";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1831 imp_iic_wrap_s: clock-controller@11d03000 {
1832 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1834 #clock-cells = <1>;
1838 compatible = "mediatek,mt8195-i2c",
1839 "mediatek,mt8192-i2c";
1843 clock-div = <1>;
1846 clock-names = "main", "dma";
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1853 compatible = "mediatek,mt8195-i2c",
1854 "mediatek,mt8192-i2c";
1858 clock-div = <1>;
1861 clock-names = "main", "dma";
1862 #address-cells = <1>;
1863 #size-cells = <0>;
1868 compatible = "mediatek,mt8195-i2c",
1869 "mediatek,mt8192-i2c";
1873 clock-div = <1>;
1876 clock-names = "main", "dma";
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1883 compatible = "mediatek,mt8195-i2c",
1884 "mediatek,mt8192-i2c";
1888 clock-div = <1>;
1891 clock-names = "main", "dma";
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1898 compatible = "mediatek,mt8195-i2c",
1899 "mediatek,mt8192-i2c";
1903 clock-div = <1>;
1906 clock-names = "main", "dma";
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1912 imp_iic_wrap_w: clock-controller@11e05000 {
1913 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1915 #clock-cells = <1>;
1918 u3phy1: t-phy@11e30000 {
1919 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1920 #address-cells = <1>;
1921 #size-cells = <1>;
1923 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1926 u2port1: usb-phy@0 {
1930 clock-names = "ref", "da_ref";
1931 #phy-cells = <1>;
1934 u3port1: usb-phy@700 {
1938 clock-names = "ref", "da_ref";
1939 nvmem-cells = <&comb_intr_p1>,
1942 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1943 #phy-cells = <1>;
1947 u3phy0: t-phy@11e40000 {
1948 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1949 #address-cells = <1>;
1950 #size-cells = <1>;
1954 u2port0: usb-phy@0 {
1958 clock-names = "ref", "da_ref";
1959 #phy-cells = <1>;
1962 u3port0: usb-phy@700 {
1966 clock-names = "ref", "da_ref";
1967 nvmem-cells = <&u3_intr_p0>,
1970 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1971 #phy-cells = <1>;
1976 compatible = "mediatek,mt8195-pcie-phy";
1978 reg-names = "sif";
1979 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1983 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1987 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1988 #phy-cells = <0>;
1992 ufsphy: ufs-phy@11fa0000 {
1993 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1996 clock-names = "unipro", "mp";
1997 #phy-cells = <0>;
2002 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2003 "arm,mali-valhall-jm";
2010 interrupt-names = "job", "mmu", "gpu";
2011 operating-points-v2 = <&gpu_opp_table>;
2012 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2017 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2021 mfgcfg: clock-controller@13fbf000 {
2022 compatible = "mediatek,mt8195-mfgcfg";
2024 #clock-cells = <1>;
2028 compatible = "mediatek,mt8195-vppsys0", "syscon";
2030 #clock-cells = <1>;
2031 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2034 dma-controller@14001000 {
2035 compatible = "mediatek,mt8195-mdp3-rdma";
2037 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2038 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2041 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2049 #dma-cells = <1>;
2053 compatible = "mediatek,mt8195-mdp3-fg";
2055 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2060 compatible = "mediatek,mt8195-mdp3-stitch";
2062 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2067 compatible = "mediatek,mt8195-mdp3-hdr";
2069 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2074 compatible = "mediatek,mt8195-mdp3-aal";
2077 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2079 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2083 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2085 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2086 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2092 compatible = "mediatek,mt8195-mdp3-tdshp";
2094 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2099 compatible = "mediatek,mt8195-mdp3-color";
2102 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2104 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2108 compatible = "mediatek,mt8195-mdp3-ovl";
2111 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2113 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2118 compatible = "mediatek,mt8195-mdp3-padding";
2120 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2122 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2126 compatible = "mediatek,mt8195-mdp3-tcc";
2128 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2132 dma-controller@1400c000 {
2133 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2135 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2136 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2140 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2141 #dma-cells = <1>;
2145 compatible = "mediatek,mt8195-vpp-mutex";
2148 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2150 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2154 compatible = "mediatek,mt8195-smi-sub-common";
2159 clock-names = "apb", "smi", "gals0";
2161 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2165 compatible = "mediatek,mt8195-smi-sub-common";
2170 clock-names = "apb", "smi", "gals0";
2172 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2176 compatible = "mediatek,mt8195-smi-common-vpp";
2182 clock-names = "apb", "smi", "gals0", "gals1";
2183 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2187 compatible = "mediatek,mt8195-smi-larb";
2189 mediatek,larb-id = <4>;
2193 clock-names = "apb", "smi";
2194 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2198 compatible = "mediatek,mt8195-iommu-vpp";
2206 clock-names = "bclk";
2207 #iommu-cells = <1>;
2208 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2211 wpesys: clock-controller@14e00000 {
2212 compatible = "mediatek,mt8195-wpesys";
2214 #clock-cells = <1>;
2217 wpesys_vpp0: clock-controller@14e02000 {
2218 compatible = "mediatek,mt8195-wpesys_vpp0";
2220 #clock-cells = <1>;
2223 wpesys_vpp1: clock-controller@14e03000 {
2224 compatible = "mediatek,mt8195-wpesys_vpp1";
2226 #clock-cells = <1>;
2230 compatible = "mediatek,mt8195-smi-larb";
2232 mediatek,larb-id = <7>;
2236 clock-names = "apb", "smi";
2237 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2241 compatible = "mediatek,mt8195-smi-larb";
2243 mediatek,larb-id = <8>;
2248 clock-names = "apb", "smi", "gals";
2249 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2253 compatible = "mediatek,mt8195-vppsys1", "syscon";
2255 #clock-cells = <1>;
2256 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2260 compatible = "mediatek,mt8195-vpp-mutex";
2263 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2265 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2269 compatible = "mediatek,mt8195-smi-larb";
2271 mediatek,larb-id = <5>;
2276 clock-names = "apb", "smi", "gals";
2277 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2281 compatible = "mediatek,mt8195-smi-larb";
2283 mediatek,larb-id = <6>;
2288 clock-names = "apb", "smi", "gals";
2289 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2293 compatible = "mediatek,mt8195-mdp3-split";
2295 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2299 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2303 compatible = "mediatek,mt8195-mdp3-tcc";
2305 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2309 dma-controller@14f08000 {
2310 compatible = "mediatek,mt8195-mdp3-rdma";
2312 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2313 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2317 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2318 #dma-cells = <1>;
2321 dma-controller@14f09000 {
2322 compatible = "mediatek,mt8195-mdp3-rdma";
2324 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2325 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2329 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2330 #dma-cells = <1>;
2333 dma-controller@14f0a000 {
2334 compatible = "mediatek,mt8195-mdp3-rdma";
2336 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2337 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2341 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2342 #dma-cells = <1>;
2346 compatible = "mediatek,mt8195-mdp3-fg";
2348 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2353 compatible = "mediatek,mt8195-mdp3-fg";
2355 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2360 compatible = "mediatek,mt8195-mdp3-fg";
2362 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2367 compatible = "mediatek,mt8195-mdp3-hdr";
2369 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2374 compatible = "mediatek,mt8195-mdp3-hdr";
2376 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2381 compatible = "mediatek,mt8195-mdp3-hdr";
2383 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2388 compatible = "mediatek,mt8195-mdp3-aal";
2391 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2393 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2397 compatible = "mediatek,mt8195-mdp3-aal";
2400 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2402 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2406 compatible = "mediatek,mt8195-mdp3-aal";
2409 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2411 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2415 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2417 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2418 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2424 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2426 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2427 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2433 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2435 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2436 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2442 compatible = "mediatek,mt8195-mdp3-tdshp";
2444 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2449 compatible = "mediatek,mt8195-mdp3-tdshp";
2451 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2456 compatible = "mediatek,mt8195-mdp3-tdshp";
2458 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2463 compatible = "mediatek,mt8195-mdp3-merge";
2465 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2467 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2471 compatible = "mediatek,mt8195-mdp3-merge";
2473 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2475 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2479 compatible = "mediatek,mt8195-mdp3-color";
2482 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2484 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2488 compatible = "mediatek,mt8195-mdp3-color";
2490 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2493 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2497 compatible = "mediatek,mt8195-mdp3-color";
2500 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2502 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2506 compatible = "mediatek,mt8195-mdp3-ovl";
2509 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2511 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2516 compatible = "mediatek,mt8195-mdp3-padding";
2518 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2520 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2524 compatible = "mediatek,mt8195-mdp3-padding";
2526 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2528 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2532 compatible = "mediatek,mt8195-mdp3-padding";
2534 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2536 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2539 dma-controller@14f23000 {
2540 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2542 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2543 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2547 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2548 #dma-cells = <1>;
2551 dma-controller@14f24000 {
2552 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2554 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2555 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2559 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2560 #dma-cells = <1>;
2563 dma-controller@14f25000 {
2564 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2566 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2567 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2571 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2572 #dma-cells = <1>;
2575 imgsys: clock-controller@15000000 {
2576 compatible = "mediatek,mt8195-imgsys";
2578 #clock-cells = <1>;
2582 compatible = "mediatek,mt8195-smi-larb";
2584 mediatek,larb-id = <9>;
2589 clock-names = "apb", "smi", "gals";
2590 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2594 compatible = "mediatek,mt8195-smi-sub-common";
2599 clock-names = "apb", "smi", "gals0";
2601 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2605 compatible = "mediatek,mt8195-smi-sub-common";
2610 clock-names = "apb", "smi", "gals0";
2612 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2615 imgsys1_dip_top: clock-controller@15110000 {
2616 compatible = "mediatek,mt8195-imgsys1_dip_top";
2618 #clock-cells = <1>;
2622 compatible = "mediatek,mt8195-smi-larb";
2624 mediatek,larb-id = <10>;
2628 clock-names = "apb", "smi";
2629 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2632 imgsys1_dip_nr: clock-controller@15130000 {
2633 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2635 #clock-cells = <1>;
2638 imgsys1_wpe: clock-controller@15220000 {
2639 compatible = "mediatek,mt8195-imgsys1_wpe";
2641 #clock-cells = <1>;
2645 compatible = "mediatek,mt8195-smi-larb";
2647 mediatek,larb-id = <11>;
2651 clock-names = "apb", "smi";
2652 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2655 ipesys: clock-controller@15330000 {
2656 compatible = "mediatek,mt8195-ipesys";
2658 #clock-cells = <1>;
2662 compatible = "mediatek,mt8195-smi-larb";
2664 mediatek,larb-id = <12>;
2668 clock-names = "apb", "smi";
2669 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2672 camsys: clock-controller@16000000 {
2673 compatible = "mediatek,mt8195-camsys";
2675 #clock-cells = <1>;
2679 compatible = "mediatek,mt8195-smi-larb";
2681 mediatek,larb-id = <13>;
2686 clock-names = "apb", "smi", "gals";
2687 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2691 compatible = "mediatek,mt8195-smi-larb";
2693 mediatek,larb-id = <14>;
2697 clock-names = "apb", "smi";
2698 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2702 compatible = "mediatek,mt8195-smi-sub-common";
2707 clock-names = "apb", "smi", "gals0";
2709 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2713 compatible = "mediatek,mt8195-smi-sub-common";
2718 clock-names = "apb", "smi", "gals0";
2720 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2724 compatible = "mediatek,mt8195-smi-larb";
2726 mediatek,larb-id = <16>;
2730 clock-names = "apb", "smi";
2731 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2735 compatible = "mediatek,mt8195-smi-larb";
2737 mediatek,larb-id = <17>;
2741 clock-names = "apb", "smi";
2742 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2746 compatible = "mediatek,mt8195-smi-larb";
2748 mediatek,larb-id = <27>;
2752 clock-names = "apb", "smi";
2753 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2757 compatible = "mediatek,mt8195-smi-larb";
2759 mediatek,larb-id = <28>;
2763 clock-names = "apb", "smi";
2764 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2767 camsys_rawa: clock-controller@1604f000 {
2768 compatible = "mediatek,mt8195-camsys_rawa";
2770 #clock-cells = <1>;
2773 camsys_yuva: clock-controller@1606f000 {
2774 compatible = "mediatek,mt8195-camsys_yuva";
2776 #clock-cells = <1>;
2779 camsys_rawb: clock-controller@1608f000 {
2780 compatible = "mediatek,mt8195-camsys_rawb";
2782 #clock-cells = <1>;
2785 camsys_yuvb: clock-controller@160af000 {
2786 compatible = "mediatek,mt8195-camsys_yuvb";
2788 #clock-cells = <1>;
2791 camsys_mraw: clock-controller@16140000 {
2792 compatible = "mediatek,mt8195-camsys_mraw";
2794 #clock-cells = <1>;
2798 compatible = "mediatek,mt8195-smi-larb";
2800 mediatek,larb-id = <25>;
2805 clock-names = "apb", "smi", "gals";
2806 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2810 compatible = "mediatek,mt8195-smi-larb";
2812 mediatek,larb-id = <26>;
2816 clock-names = "apb", "smi";
2817 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2821 ccusys: clock-controller@17200000 {
2822 compatible = "mediatek,mt8195-ccusys";
2824 #clock-cells = <1>;
2828 compatible = "mediatek,mt8195-smi-larb";
2830 mediatek,larb-id = <18>;
2834 clock-names = "apb", "smi";
2835 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2838 video-codec@18000000 {
2839 compatible = "mediatek,mt8195-vcodec-dec";
2842 #address-cells = <2>;
2843 #size-cells = <2>;
2848 video-codec@2000 {
2849 compatible = "mediatek,mtk-vcodec-lat-soc";
2857 clock-names = "sel", "vdec", "lat", "top";
2858 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2859 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2860 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2863 video-codec@10000 {
2864 compatible = "mediatek,mtk-vcodec-lat";
2877 clock-names = "sel", "vdec", "lat", "top";
2878 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2879 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2880 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2883 video-codec@25000 {
2884 compatible = "mediatek,mtk-vcodec-core";
2901 clock-names = "sel", "vdec", "lat", "top";
2902 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2903 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2904 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2909 compatible = "mediatek,mt8195-smi-larb";
2911 mediatek,larb-id = <24>;
2915 clock-names = "apb", "smi";
2916 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2920 compatible = "mediatek,mt8195-smi-larb";
2922 mediatek,larb-id = <23>;
2926 clock-names = "apb", "smi";
2927 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2930 vdecsys_soc: clock-controller@1800f000 {
2931 compatible = "mediatek,mt8195-vdecsys_soc";
2933 #clock-cells = <1>;
2937 compatible = "mediatek,mt8195-smi-larb";
2939 mediatek,larb-id = <21>;
2943 clock-names = "apb", "smi";
2944 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2947 vdecsys: clock-controller@1802f000 {
2948 compatible = "mediatek,mt8195-vdecsys";
2950 #clock-cells = <1>;
2954 compatible = "mediatek,mt8195-smi-larb";
2956 mediatek,larb-id = <22>;
2960 clock-names = "apb", "smi";
2961 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2964 vdecsys_core1: clock-controller@1803f000 {
2965 compatible = "mediatek,mt8195-vdecsys_core1";
2967 #clock-cells = <1>;
2970 apusys_pll: clock-controller@190f3000 {
2971 compatible = "mediatek,mt8195-apusys_pll";
2973 #clock-cells = <1>;
2976 vencsys: clock-controller@1a000000 {
2977 compatible = "mediatek,mt8195-vencsys";
2979 #clock-cells = <1>;
2983 compatible = "mediatek,mt8195-smi-larb";
2985 mediatek,larb-id = <19>;
2989 clock-names = "apb", "smi";
2990 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2993 venc: video-codec@1a020000 {
2994 compatible = "mediatek,mt8195-vcodec-enc";
3008 clock-names = "venc_sel";
3009 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3010 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3011 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3012 #address-cells = <2>;
3013 #size-cells = <2>;
3016 jpgdec-master {
3017 compatible = "mediatek,mt8195-jpgdec";
3018 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3025 #address-cells = <2>;
3026 #size-cells = <2>;
3030 compatible = "mediatek,mt8195-jpgdec-hw";
3040 clock-names = "jpgdec";
3041 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3045 compatible = "mediatek,mt8195-jpgdec-hw";
3055 clock-names = "jpgdec";
3056 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3060 compatible = "mediatek,mt8195-jpgdec-hw";
3070 clock-names = "jpgdec";
3071 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3075 vencsys_core1: clock-controller@1b000000 {
3076 compatible = "mediatek,mt8195-vencsys_core1";
3078 #clock-cells = <1>;
3082 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3085 #clock-cells = <1>;
3086 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3090 jpgenc-master {
3091 compatible = "mediatek,mt8195-jpgenc";
3092 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3097 #address-cells = <2>;
3098 #size-cells = <2>;
3102 compatible = "mediatek,mt8195-jpgenc-hw";
3110 clock-names = "jpgenc";
3111 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3115 compatible = "mediatek,mt8195-jpgenc-hw";
3123 clock-names = "jpgenc";
3124 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3129 compatible = "mediatek,mt8195-smi-larb";
3131 mediatek,larb-id = <20>;
3136 clock-names = "apb", "smi", "gals";
3137 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3141 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3144 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3147 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3150 rdma0: rdma@1c002000 {
3151 compatible = "mediatek,mt8195-disp-rdma";
3154 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3157 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3161 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3164 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3166 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3170 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3173 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3175 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3179 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3182 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3184 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3188 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3191 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3193 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3197 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3200 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3202 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3206 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3209 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3213 clock-names = "engine", "digital", "hs";
3215 phy-names = "dphy";
3220 compatible = "mediatek,mt8195-disp-dsc";
3223 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3225 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3229 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3232 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3236 clock-names = "engine", "digital", "hs";
3238 phy-names = "dphy";
3243 compatible = "mediatek,mt8195-disp-merge";
3246 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3248 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3251 dp_intf0: dp-intf@1c015000 {
3252 compatible = "mediatek,mt8195-dp-intf";
3258 clock-names = "pixel", "engine", "pll";
3263 compatible = "mediatek,mt8195-disp-mutex";
3266 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3268 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3269 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3273 compatible = "mediatek,mt8195-smi-larb";
3275 mediatek,larb-id = <0>;
3280 clock-names = "apb", "smi", "gals";
3281 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3285 compatible = "mediatek,mt8195-smi-larb";
3287 mediatek,larb-id = <1>;
3292 clock-names = "apb", "smi", "gals";
3293 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3297 compatible = "mediatek,mt8195-vdosys1", "syscon";
3300 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3301 #clock-cells = <1>;
3302 #reset-cells = <1>;
3306 compatible = "mediatek,mt8195-smi-common-vdo";
3312 clock-names = "apb", "smi", "gals0", "gals1";
3313 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3318 compatible = "mediatek,mt8195-iommu-vdo";
3325 #iommu-cells = <1>;
3327 clock-names = "bclk";
3328 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3332 compatible = "mediatek,mt8195-disp-mutex";
3334 reg-names = "vdo1_mutex";
3336 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3338 clock-names = "vdo1_mutex";
3339 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3340 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3344 compatible = "mediatek,mt8195-smi-larb";
3346 mediatek,larb-id = <2>;
3351 clock-names = "apb", "smi", "gals";
3352 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3356 compatible = "mediatek,mt8195-smi-larb";
3358 mediatek,larb-id = <3>;
3363 clock-names = "apb", "smi", "gals";
3364 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3367 vdo1_rdma0: dma-controller@1c104000 {
3368 compatible = "mediatek,mt8195-vdo1-rdma";
3372 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3374 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3375 #dma-cells = <1>;
3378 vdo1_rdma1: dma-controller@1c105000 {
3379 compatible = "mediatek,mt8195-vdo1-rdma";
3383 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3385 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3386 #dma-cells = <1>;
3389 vdo1_rdma2: dma-controller@1c106000 {
3390 compatible = "mediatek,mt8195-vdo1-rdma";
3394 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3396 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3397 #dma-cells = <1>;
3400 vdo1_rdma3: dma-controller@1c107000 {
3401 compatible = "mediatek,mt8195-vdo1-rdma";
3405 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3407 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3408 #dma-cells = <1>;
3411 vdo1_rdma4: dma-controller@1c108000 {
3412 compatible = "mediatek,mt8195-vdo1-rdma";
3416 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3418 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3419 #dma-cells = <1>;
3422 vdo1_rdma5: dma-controller@1c109000 {
3423 compatible = "mediatek,mt8195-vdo1-rdma";
3427 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3429 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3430 #dma-cells = <1>;
3433 vdo1_rdma6: dma-controller@1c10a000 {
3434 compatible = "mediatek,mt8195-vdo1-rdma";
3438 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3440 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3441 #dma-cells = <1>;
3444 vdo1_rdma7: dma-controller@1c10b000 {
3445 compatible = "mediatek,mt8195-vdo1-rdma";
3449 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3451 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3452 #dma-cells = <1>;
3455 merge1: vpp-merge@1c10c000 {
3456 compatible = "mediatek,mt8195-disp-merge";
3461 clock-names = "merge","merge_async";
3462 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3463 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3464 mediatek,merge-mute;
3468 merge2: vpp-merge@1c10d000 {
3469 compatible = "mediatek,mt8195-disp-merge";
3474 clock-names = "merge","merge_async";
3475 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3476 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3477 mediatek,merge-mute;
3481 merge3: vpp-merge@1c10e000 {
3482 compatible = "mediatek,mt8195-disp-merge";
3487 clock-names = "merge","merge_async";
3488 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3489 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3490 mediatek,merge-mute;
3494 merge4: vpp-merge@1c10f000 {
3495 compatible = "mediatek,mt8195-disp-merge";
3500 clock-names = "merge","merge_async";
3501 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3502 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3503 mediatek,merge-mute;
3507 merge5: vpp-merge@1c110000 {
3508 compatible = "mediatek,mt8195-disp-merge";
3513 clock-names = "merge","merge_async";
3514 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3515 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3516 mediatek,merge-fifo-en;
3520 dp_intf1: dp-intf@1c113000 {
3521 compatible = "mediatek,mt8195-dp-intf";
3524 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3528 clock-names = "pixel", "engine", "pll";
3532 ethdr0: hdr-engine@1c114000 {
3533 compatible = "mediatek,mt8195-disp-ethdr";
3541 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3543 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3563 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3567 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3576 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3580 edp_tx: edp-tx@1c500000 {
3581 compatible = "mediatek,mt8195-edp-tx";
3583 nvmem-cells = <&dp_calibration>;
3584 nvmem-cell-names = "dp_calibration_data";
3585 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3587 max-linkrate-mhz = <8100>;
3591 dp_tx: dp-tx@1c600000 {
3592 compatible = "mediatek,mt8195-dp-tx";
3594 nvmem-cells = <&dp_calibration>;
3595 nvmem-cell-names = "dp_calibration_data";
3596 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3598 max-linkrate-mhz = <8100>;
3603 thermal_zones: thermal-zones {
3604 cpu0-thermal {
3605 polling-delay = <1000>;
3606 polling-delay-passive = <250>;
3607 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3610 cpu0_alert: trip-alert {
3616 cpu0_crit: trip-crit {
3623 cooling-maps {
3626 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3634 cpu1-thermal {
3635 polling-delay = <1000>;
3636 polling-delay-passive = <250>;
3637 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3640 cpu1_alert: trip-alert {
3646 cpu1_crit: trip-crit {
3653 cooling-maps {
3656 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3664 cpu2-thermal {
3665 polling-delay = <1000>;
3666 polling-delay-passive = <250>;
3667 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3670 cpu2_alert: trip-alert {
3676 cpu2_crit: trip-crit {
3683 cooling-maps {
3686 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3694 cpu3-thermal {
3695 polling-delay = <1000>;
3696 polling-delay-passive = <250>;
3697 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3700 cpu3_alert: trip-alert {
3706 cpu3_crit: trip-crit {
3713 cooling-maps {
3716 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3724 cpu4-thermal {
3725 polling-delay = <1000>;
3726 polling-delay-passive = <250>;
3727 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3730 cpu4_alert: trip-alert {
3736 cpu4_crit: trip-crit {
3743 cooling-maps {
3746 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3754 cpu5-thermal {
3755 polling-delay = <1000>;
3756 polling-delay-passive = <250>;
3757 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3760 cpu5_alert: trip-alert {
3766 cpu5_crit: trip-crit {
3773 cooling-maps {
3776 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3784 cpu6-thermal {
3785 polling-delay = <1000>;
3786 polling-delay-passive = <250>;
3787 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3790 cpu6_alert: trip-alert {
3796 cpu6_crit: trip-crit {
3803 cooling-maps {
3806 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3814 cpu7-thermal {
3815 polling-delay = <1000>;
3816 polling-delay-passive = <250>;
3817 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3820 cpu7_alert: trip-alert {
3826 cpu7_crit: trip-crit {
3833 cooling-maps {
3836 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3844 vpu0-thermal {
3845 polling-delay = <1000>;
3846 polling-delay-passive = <250>;
3847 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3850 vpu0_alert: trip-alert {
3856 vpu0_crit: trip-crit {
3864 vpu1-thermal {
3865 polling-delay = <1000>;
3866 polling-delay-passive = <250>;
3867 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3870 vpu1_alert: trip-alert {
3876 vpu1_crit: trip-crit {
3884 gpu-thermal {
3885 polling-delay = <1000>;
3886 polling-delay-passive = <250>;
3887 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3890 gpu0_alert: trip-alert {
3896 gpu0_crit: trip-crit {
3904 gpu1-thermal {
3905 polling-delay = <1000>;
3906 polling-delay-passive = <250>;
3907 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3910 gpu1_alert: trip-alert {
3916 gpu1_crit: trip-crit {
3924 vdec-thermal {
3925 polling-delay = <1000>;
3926 polling-delay-passive = <250>;
3927 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3930 vdec_alert: trip-alert {
3936 vdec_crit: trip-crit {
3944 img-thermal {
3945 polling-delay = <1000>;
3946 polling-delay-passive = <250>;
3947 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3950 img_alert: trip-alert {
3956 img_crit: trip-crit {
3964 infra-thermal {
3965 polling-delay = <1000>;
3966 polling-delay-passive = <250>;
3967 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3970 infra_alert: trip-alert {
3976 infra_crit: trip-crit {
3984 cam0-thermal {
3985 polling-delay = <1000>;
3986 polling-delay-passive = <250>;
3987 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3990 cam0_alert: trip-alert {
3996 cam0_crit: trip-crit {
4004 cam1-thermal {
4005 polling-delay = <1000>;
4006 polling-delay-passive = <250>;
4007 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
4010 cam1_alert: trip-alert {
4016 cam1_crit: trip-crit {